[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

NeHuang added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:339 if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) && llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { I think we also need to check for `ArchDefi

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

NeHuang marked an inline comment as done. NeHuang added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:339 if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) && llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { l

[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel

NeHuang accepted this revision as: NeHuang. NeHuang added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80757/new/ https://reviews.llvm.org/D80757 ___ cfe-commits mailing list cfe-commi

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

NeHuang added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156 + + // This transformation is only valid if the we are loading either a byte, + // halfword, word, or doubleword. nit: if we are loading either a byte ===

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

NeHuang added a comment. Overall seems fine to me, but of course, please wait to hear from Amy. Just some nits for the test case. Comment at: llvm/test/CodeGen/PowerPC/p10-vector-shift.ll:9 +; RUN: FileCheck %s + +define dso_local <1 x i128> @test_vec_slq(<1 x i128> %a, <1 x

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

NeHuang added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr10 -ppc-asm-f

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

NeHuang added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13422 + return DAG.getMemIntrinsicNode(PPCISD::LXVRZX, dl, +DAG.getVTList(MVT::v1i128, MVT::Other), +LoadOps, MemoryType, LD->get

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

NeHuang added a comment. Overall LGTM. I only have some nits comment. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:136 +vector unsigned char test_vexpandm_uc(void) { + // CHECK: @llvm.ppc.altivec.vexpandbm(<16 x i8> %{{.+}}) nit: can we change the

[PATCH] D82609: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

NeHuang added inline comments. Comment at: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll:59 + +define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vdivesw: nit: do we also need `_intrinsic` in the name as the test cases for the v

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGd40e8091bd1f: [PowerPC] Add PowerPC rotate related builtins and emit target independent code… (authored by NeHuang). Changed prior to commit: http

[PATCH] D106021: [PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. NeHuang marked an inline comment as done. Closed by commit rG4eb107ccbad7: [PowerPC] Add PowerPC population count, reversed load and store related… (authored by NeHuang

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang updated this revision to Diff 359467. NeHuang added a comment. Herald added subscribers: llvm-commits, hiraditya. Address review comment to rework 32 bit handling. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.ll

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

NeHuang accepted this revision. NeHuang added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103986/new/ https://reviews.llvm.org/D103986 ___ cfe-commits mailing list cfe-commits@lists.llv

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang updated this revision to Diff 359843. NeHuang added a comment. Address review comments from Nemanja. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.llvm.org/D105194 Files: clang/include/clang/Basic/BuiltinsPPC.

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang marked 4 inline comments as done. NeHuang added a comment. Rebased the patch with ToT. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.llvm.org/D105194 ___ cfe-commits m

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang updated this revision to Diff 360109. NeHuang added a comment. clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.llvm.org/D105194 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Basic/Tar

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1a762f93f816: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL… (authored by NeHuang). Repository: rG LLVM Github Monorep

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang added a comment. Thanks @jroelofs for moving the test cases! Those cases were added in https://reviews.llvm.org/D105946 and I have notified the author. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.llvm.org/D105

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

NeHuang added subscribers: jroelofs, NeHuang. NeHuang added a comment. @jroelofs committed `f6769b663a0d4432b5e00e0c03904a5dfba7b077` to move the backend test cases from `CodeGen` -> `CodeGen/PowerPC` so they don't fail when the PPC backend isn't built. Repository: rG LLVM Github Monorepo C

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

NeHuang created this revision. NeHuang added reviewers: nemanjai, PowerPC. NeHuang added a project: LLVM. Herald added subscribers: shchenz, kbarton, hiraditya. NeHuang requested review of this revision. Herald added a project: clang. Herald added subscribers: llvm-commits, cfe-commits. This patch

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

NeHuang updated this revision to Diff 360803. NeHuang added a comment. - Addressed review comments from Lei - Rebased the patch Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106484/new/ https://reviews.llvm.org/D106484 Files: clang/include/clang

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

NeHuang marked an inline comment as done. NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c:31 + return __builtin_ppc_stbcx(c_addr, c); +} lei wrote: > Why not just add this tc to > `clang/test/CodeGen/builtins-ppc-xlcom

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. NeHuang marked an inline comment as done. Closed by commit rG26ea4a443243: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility (authored by NeHua

[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

NeHuang accepted this revision as: NeHuang. NeHuang added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106817/new/ https://reviews.llvm.org/D106817

[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

NeHuang updated this revision to Diff 407877. NeHuang marked an inline comment as done. NeHuang added a comment. Address review comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117355/new/ https://reviews.llvm.org/D117355 Files: llvm/lib/

[PATCH] D82035: [PowerPC] Add Sema checks for MMA types

NeHuang added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:10339 + if (Context.getTargetInfo().getTriple().isPPC64()) +CheckPPCMMAType(RetValExp->getType(), ReturnLoc); } CheckPPCMMAType returns bool value. Do we need add it in the if condit

[PATCH] D90173: [PowerPC] Exploit splat instruction xxsplti32dx in Power10

NeHuang added a comment. Please clang-format the patch to pass pre-merge checks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90173/new/ https://reviews.llvm.org/D90173 ___ cfe-commits mailing list cfe-

[PATCH] D91279: [PowerPC] DForm instructions should be preferred when using zero register

NeHuang added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp:417 + + // should prefer D-form if LXVX / STXVX uses a ZERO or ZERO8 + if (MI.getOpcode() == PPC::LXVX || MI.getOpcode() == PPC::STXVX) { amyk wrote: > Ple

[PATCH] D90173: [PowerPC] Exploit splat instruction xxsplti32dx in Power10

NeHuang requested changes to this revision. NeHuang added inline comments. This revision now requires changes to proceed. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9189 HasAnyUndefs, 0, !Subtarget.isLittleEndian()); + bool LE = Subtarget

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang created this revision. Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai. NeHuang requested review of this revision. Herald added projects: clang, LLVM. Herald added subscribers: llvm-commits, cfe-commits. This is patch is in a series of patches to provide builtins for compat

[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:27 char test_lbarx(volatile unsigned char *a) { // CHECK-LABEL: @test_lbarx Do you also need to update the input argument type here as well to match t

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

NeHuang added a comment. Do we already have a backend test case for `fdiv` emitting a software estimate when `-Ofast` is used? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106959/new/ https://reviews.llvm.org/D106959

[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

NeHuang added inline comments. Comment at: clang/test/Sema/ppc-mma-builtins.c:1 +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ +// RUN: -target-feature -mma -fsyntax-only %s -verify can you please add `// REQUIRES: powerpc-register

[PATCH] D108823: [PowerPC] Mark splat immediate instructions as rematerializable

This revision was automatically updated to reflect the committed changes. Closed by commit rG6e1aaf18af6c: [PowerPC] Mark splat immediate instructions as rematerializable (authored by NeHuang). Changed prior to commit: https://reviews.llvm.org/D108823?vs=369101&id=374892#toc Repository: rG L

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang updated this revision to Diff 350991. NeHuang added a comment. - Renamed the XLCompat builtin as `__builtin_ppc_*` and add them to `definedXLCompatMacros` and update the test cases. - Report error in SemaChecking when 64 bit only builtins run on a 32 bit target and update the test cases.

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang updated this revision to Diff 351989. NeHuang added a comment. Rebased the patch with changes in https://reviews.llvm.org/D104125 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102875/new/ https://reviews.llvm.org/D102875 Files: clang/inc

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang updated this revision to Diff 352560. NeHuang added a comment. - Add AIX 32&64 bit run line checks (front and back end test cases) - Create builtin-ppc-xlcompat-error.c for arguments related error check, add error test case for `__builtin_ppc_cmprb` - Remove 32 bit linux run line checks -

[PATCH] D104664: [PowerPC][NFC] Clean up builtin sema checks

NeHuang accepted this revision. NeHuang added a comment. This revision is now accepted and ready to land. LGTM. Please give it some time (~24hrs) before commit to wait for the other reviewers' comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

NeHuang created this revision. NeHuang added reviewers: nemanjai, stefanp, PowerPC. NeHuang added projects: LLVM, clang. Herald added subscribers: shchenz, kbarton. NeHuang requested review of this revision. Herald added a subscriber: cfe-commits. This patch is in a series of patches to provide bu

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang updated this revision to Diff 354081. NeHuang added a comment. - Added Sema check for the pwr9 only builtins and updated the test cases. - Rebased the patch with ToT. - Cleaned up the test cases and address review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

NeHuang updated this revision to Diff 354082. NeHuang added a comment. - Rebased the patch with ToT and the patch https://reviews.llvm.org/D102875 - Create the patch with all contexts. (Thanks @qiucf) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

NeHuang added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3426 + case PPC::BI__builtin_ppc_addex: { +if (SemaFeatureCheck(*this, TheCall, "power9-vector", + diag::err_ppc_builtin_only_on_arch, "9") || I think we start

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1 +// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \ +// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s `// REQUIRES: powerpc-registered-target` ==

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

NeHuang added inline comments. Comment at: llvm/test/CodeGen/PowerPC/O3-pipeline.ll:211 ret void -} \ No newline at end of file +} unrelated change? Comment at: llvm/test/CodeGen/PowerPC/int-ppc-ftdivdp.ll:7 +; RUN: llc -verify-machineinstrs

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:45 + // CHECK-AIX-NEXT: ret { double, double } %.fca.1.insert + return __cmplxl(lda, ldb); +} nemanjai wrote: > We really only need this test case and we should be abl

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

NeHuang created this revision. NeHuang added reviewers: nemanjai, stefanp, PowerPC. NeHuang added a project: LLVM. Herald added subscribers: shchenz, kbarton, hiraditya. NeHuang requested review of this revision. When depth > 0, callee frame address is used to compute the return address of callee

[PATCH] D107461: [PowerPC] Do not define __PRIVILEGED__

NeHuang added inline comments. Comment at: clang/test/Driver/ppc-mprivileged-support-check.c:25 +// HASPRIV: test() #0 { +// HASPRIV: attributes #0 { +// HASPRIV-SAME: +privileged maybe check for `attributes #0 = {` Repository: rG LLVM Github Monorepo CHAN

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv.c:17 +// CHECK-LABEL: @test_swdiv( +// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8 +// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8 nit: alig

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

NeHuang updated this revision to Diff 364856. NeHuang added a comment. - Rebased with ToT - Clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107646/new/ https://reviews.llvm.org/D107646 Files: llvm/lib/Target/PowerPC/PPCISelLowering.cp

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

NeHuang updated this revision to Diff 365470. NeHuang added a comment. Address review comments on the test case. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107646/new/ https://reviews.llvm.org/D107646 Files: llvm/lib/Target/PowerPC/PPCISelLow

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

NeHuang added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107002/new/ https://reviews.llvm.org/D107002 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cg

[PATCH] D107461: [PowerPC] Do not define __PRIVILEGED__

NeHuang accepted this revision as: NeHuang. NeHuang added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107461/new/ https://reviews.llvm.org/D107461 ___ cfe-commits mailing list cfe-commi

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

NeHuang accepted this revision. NeHuang added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107138/new/ https://reviews.llvm.org/D107138 ___ cfe-commits mailing list cfe-commits@lists.llv

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

NeHuang updated this revision to Diff 365761. NeHuang added a comment. Address review comment from Nemanja. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107646/new/ https://reviews.llvm.org/D107646 Files: llvm/lib/Target/PowerPC/PPCISelLowering

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

This revision was automatically updated to reflect the committed changes. Closed by commit rG99e00663d4cd: [PowerPC] Fix return address computation for "__builtin_return_address" (authored by NeHuang). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10

[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

NeHuang created this revision. NeHuang added reviewers: stefanp, nemanjai, PowerPC. NeHuang added a project: LLVM. Herald added subscribers: shchenz, kbarton, hiraditya. NeHuang requested review of this revision. This patch adds a fix to do early if conversion to select when conditional branch no

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang created this revision. NeHuang added reviewers: nemanjai, stefanp, lei, PowerPC. NeHuang added a project: LLVM. Herald added subscribers: shchenz, kbarton. NeHuang requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. This patch is in a s

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

NeHuang requested changes to this revision. NeHuang added inline comments. This revision now requires changes to proceed. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:32 -// builtins for compatibility with the XL compiler +// XL Compatibility built-ins BUILTIN(__built

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

NeHuang added a comment. Overall looks good. Some nits as below. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-fp.c:9 +// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s + +double test_fric(double a) { - You can define three extern variables for

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

NeHuang added inline comments. Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll:18 + +define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr #0 { +; CHECK-PWR7-LABEL: test_fsel you can remove `#0`, `#1` and `#2` Repos

[PATCH] D105360: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c:240 +void test_icbt() { + __icbt(c); } From the document, `__icbt` only valid when -qarch is set to target pwr8 or higher processors. It looks like target cpu sema check

[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

NeHuang added a comment. Please add the sema check & error test case for the two 64 bit only builtins `ldarx` and `stdcx` Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64-only.ll:10 +declare i64 @llvm.ppc.ldarx(i8*) +define dso_local i64 @t

[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c:1 +// RUN: not %clang_cc1 -triple=powerpc-unknown-aix -O2 -S -emit-llvm %s -o - 2>&1 |\ +// RUN: FileCheck %s --check-prefix=CHECK32-ERROR `-S`

[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

NeHuang accepted this revision as: NeHuang. NeHuang added a comment. This revision is now accepted and ready to land. Overall LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105236/new/ https://reviews.llvm.org/D105236

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang updated this revision to Diff 356701. NeHuang marked 4 inline comments as done. NeHuang added a comment. Address review comments on the test case. Target cpu sema checking covered in front end test cases. will keep current coverage in backend test. Repository: rG LLVM Github Monorepo

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

NeHuang resigned from this revision. NeHuang added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c:2 +// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \ +// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s +// RUN: %clang_cc

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

NeHuang accepted this revision. NeHuang added a comment. This revision is now accepted and ready to land. LGTM. Thanks for addressing the comments! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103668/new/ https://reviews.llvm.org/D103668

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang added a comment. gentle ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102875/new/ https://reviews.llvm.org/D102875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

NeHuang added a comment. gentle ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104744/new/ https://reviews.llvm.org/D104744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang added a comment. gentle ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.llvm.org/D105194 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang updated this revision to Diff 357625. NeHuang marked 3 inline comments as done. NeHuang added a comment. Address review comments on test case and remove change not needed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102875/new/ https://re

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3356 + case PPC::BI__builtin_ppc_maddld: +return SemaFeatureCheck(*this, TheCall, "power9-vector", +diag::err_ppc_builtin_only_on_pwr9); amyk wrote: > This

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang updated this revision to Diff 357626. NeHuang added a comment. Remove entry check in test case. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.llvm.org/D105194 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang added a comment. Need to merge with https://reviews.llvm.org/D105501 changes once approved for pwr9 (or later processor) only sema checking. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102875/new/ https://reviews.llvm.org/D102875 __

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll:9 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ +; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64 + amyk wrote: > Does it ma

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG10e0cdfc6526: [PowerPC][NFC] Power ISA features for Semachecking (authored by NeHuang). Changed prior to commit: https://reviews.llvm.org/D105501?

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

NeHuang updated this revision to Diff 358397. NeHuang marked 4 inline comments as done. NeHuang added a comment. Addressed review comments from Nemanja. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102875/new/ https://reviews.llvm.org/D102875 Fil

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG18c19414eb70: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for… (authored by NeHuang). Changed prior to commit: htt

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15081 } + case PPC::BI__builtin_ppc_cmpb: { +llvm::Type *Ty = Ops[0]->getType(); nemanjai wrote: > I find it rather surprising that we are emitting this complex sequence for > thi

[PATCH] D106021: [PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility

NeHuang created this revision. NeHuang added reviewers: nemanjai, stefanp, PowerPC. NeHuang added a project: LLVM. Herald added subscribers: shchenz, kbarton, hiraditya. NeHuang requested review of this revision. Herald added a project: clang. Herald added subscribers: llvm-commits, cfe-commits. T

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

NeHuang marked an inline comment as done. NeHuang added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15081 } + case PPC::BI__builtin_ppc_cmpb: { +llvm::Type *Ty = Ops[0]->getType(); NeHuang wrote: > nemanjai wrote: > > I find it rather sur

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

NeHuang updated this revision to Diff 358761. NeHuang marked 4 inline comments as done. NeHuang added a comment. Address review comments from Nemanja. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104744/new/ https://reviews.llvm.org/D104744 Files

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

NeHuang updated this revision to Diff 383506. NeHuang added a comment. Addressed review comments from @nemanjai and @amyk Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112285/new/ https://reviews.llvm.org/D112285 Files: llvm/lib/Target/PowerPC/

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

NeHuang added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:131 +; CHECK: # %bb.0: +; CHECK-NEXT:tdi 3, 3, 32767 +; CHECK-NEXT:blr amyk wrote: > amyk wrote: > > nemanjai wrote: > > > Can we add `-pp

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

NeHuang updated this revision to Diff 384479. NeHuang marked 5 inline comments as done. NeHuang added a comment. Addressed review comments from @amy Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112285/new/ https://reviews.llvm.org/D112285 Files:

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

NeHuang updated this revision to Diff 384768. NeHuang marked 3 inline comments as done. NeHuang added a comment. Address review comments from @nemanjai Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112285/new/ https://reviews.llvm.org/D112285 File

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

NeHuang updated this revision to Diff 385282. NeHuang marked 3 inline comments as done. NeHuang added a comment. Address review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 Files: llvm/lib/T

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

This revision was automatically updated to reflect the committed changes. NeHuang marked 5 inline comments as done. Closed by commit rG18fe0a0d9eb1: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics… (authored by NeHuang). Changed prior to commit: https://reviews.llv

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

NeHuang marked 7 inline comments as done. NeHuang added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1020 +// We can only do the optimization for the "reg + reg" form. +if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8))) +

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

NeHuang updated this revision to Diff 387652. NeHuang added a comment. Addressed review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 Files: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp llvm/t

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGae27ca9a6783: [PowerPC] PPC backend optimization on conditional trap intrustions (authored by NeHuang). Repository: rG LLVM Github Monorepo CHANG

[PATCH] D114088: [PowerPC] Add BCD add/sub/cmp builtins

NeHuang added a comment. - Comment at: clang/lib/Headers/altivec.h:19050 +} + +static __inline__ long __bcdcmpeq(vector unsigned char __a, Do we need to add a case for "__CR6_SO_REV"? It is defined in line 25 but not used. Comment at: llvm/l

[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

NeHuang added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117355/new/ https://reviews.llvm.org/D117355 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

NeHuang created this revision. Herald added a reviewer: aaron.ballman. NeHuang requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. Add front end diagnostics to report error for unimplemented TLS models set by - compiler option `-ftls-model` -

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

NeHuang updated this revision to Diff 343683. NeHuang added a comment. Update the test case. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102070/new/ https://reviews.llvm.org/D102070 Files: clang/include/clang/Basic/DiagnosticDriverKinds.td c

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

NeHuang updated this revision to Diff 343743. NeHuang added a comment. Addressed review comment for the diagnostic message and update the test cases. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102070/new/ https://reviews.llvm.org/D102070 Files:

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

NeHuang updated this revision to Diff 344258. NeHuang added a comment. Address review comment for the diagnostic message. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102070/new/ https://reviews.llvm.org/D102070 Files: clang/include/clang/Basic

[PATCH] D102070: [AIX][TLS] Diagnose use of unimplemented TLS models

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG46475a79f85b: [AIX][TLS] Diagnose use of unimplemented TLS models (authored by NeHuang). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST A

[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

NeHuang created this revision. NeHuang added reviewers: nemanjai, stefanp, amyk, PowerPC. NeHuang added a project: LLVM. Herald added subscribers: shchenz, kbarton, hiraditya. NeHuang requested review of this revision. This patch adds the fix for undef virtual register reading failure when trap o

[PATCH] D90173: [PowerPC] Exploit splat instruction xxsplti32dx in Power10

NeHuang accepted this revision as: NeHuang. NeHuang added a comment. LGTM and please wait for Nemanja's approval before committing this patch. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90173/new/ https://reviews.llvm.org/D90173 ___ cfe-co

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