Author: Tomas Matheson
Date: 2024-05-10T09:57:06+01:00
New Revision: e6d29be566d19a6558597ed1ede4783e85485749
URL:
https://github.com/llvm/llvm-project/commit/e6d29be566d19a6558597ed1ede4783e85485749
DIFF:
https://github.com/llvm/llvm-project/commit/e6d29be566d19a6558597ed1ede4783e85485749.diff
https://github.com/tmatheson-arm commented:
This might need reworked since I landed
https://github.com/llvm/llvm-project/pull/90987.. Ping me internally if I can
help.
https://github.com/llvm/llvm-project/pull/90612
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@@ -22,6 +22,14 @@
// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-CPA %s
// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
"-target-feature" "+v9.5a"{{.*}} "-target-feature" "+cpa"
+// RUN: %clang
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/90612
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@@ -1942,12 +1942,10 @@ def : RWSysReg<"PM",0b11, 0b000,
0b0100, 0b0011, 0b001>;
// 2023 ISA Extension
// AArch64 Floating-point Mode Register controls behaviors of the FP8
-// instructions (FEAT_FPMR)
tmatheson-arm wrote:
The comment `(FEAT_
@@ -1996,7 +1996,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_D128, AArch64::AEK_LSE128,
AArch64::AEK_SPECRES2, AArch64::AEK_RASv2,
AArch64::AEK_ITE, AArch64::AEK_GCS,
- AArch64::AEK_FPMR, AArch64::AEK_
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/90612
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@@ -812,178 +812,270 @@ def ProcessorFeatures {
list Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
}
+class AArch64Processor<
+ string n,
+ Architecture64 arch,
+ SchedMachineModel m,
+ list f,
+ list tunef,
+ list default_extensions
+> : ProcessorModel {
+ //
tmatheson-arm wrote:
Summary of the PR after the recent changes:
- `CPUInfo` in `TargetParser` is now generated from `AArch64Processors.td`
- The printed order of CPUs has changed, due to definition order.
- `+perfmon` now appears in `target-features` for some CPUs. This is because
`FeaturePerf
@@ -812,178 +812,270 @@ def ProcessorFeatures {
list Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
}
+class AArch64Processor<
+ string n,
+ Architecture64 arch,
+ SchedMachineModel m,
+ list f,
+ list tunef,
+ list default_extensions
+> : ProcessorModel {
+ //
@@ -56,43 +52,64 @@ class Extension<
// The FMV priority
int FMVPriority = _FMVPriority;
+
+// Indicates if the extension is available on the command line.
+string IsFMVOnly = _IsFMVOnly;
}
// Some extensions are available for FMV but can not be controlled
@@ -94,19 +94,21 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
else
OS << ", \"" << Alias << "\"";
OS << ", AArch64::" << AEK;
-if (AEK == "AEK_NONE") {
+auto Name = Rec->getValueAsString("Name");
+if (Name.empty()) {
--
@@ -56,43 +52,64 @@ class Extension<
// The FMV priority
int FMVPriority = _FMVPriority;
+
+// Indicates if the extension is available on the command line.
+string IsFMVOnly = _IsFMVOnly;
tmatheson-arm wrote:
```suggestion
bit IsFMVOnly =
@@ -56,43 +52,64 @@ class Extension<
// The FMV priority
int FMVPriority = _FMVPriority;
+
+// Indicates if the extension is available on the command line.
+string IsFMVOnly = _IsFMVOnly;
}
// Some extensions are available for FMV but can not be controlled
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92600
>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/2] [AArch64] set AppleA14 architecture version to 8.5
--
tmatheson-arm wrote:
Thanks @AtariDreams for pointing that out. They do both seem to be "8.5 without
BTI". I had a look at what current versions of clang/llvm do in this regard:
Current builds of clang set `__ARM_FEATURE_BTI` for these processors:
```
$ clang-19 ~/hello.c --target=aarch64 -marc
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/92600
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@@ -618,187 +618,210 @@ def TuneAmpere1B : SubtargetFeature<"ampere1b",
"ARMProcFamily", "Ampere1B",
def ProcessorFeatures {
- list A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
+ list A53 = [HasV8_0aOps, FeatureCRC, FeatureSHA2,
FeatureAES,
@@ -0,0 +1,592 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -t
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/92882
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@@ -0,0 +1,84 @@
+// Function MultiVersioning (FMV) properties
+
+// Something you can add to target_version or target_clones
+class FMVExtension {
+// Name, as spelled in target_version or target_clones. e.g. "memtag"
+string Name = n;
+
+// A C++ expression giving th
https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/90612
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@@ -718,12 +718,16 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
+ // Apple A14 a
https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/101192
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Author: Tomas Matheson
Date: 2021-04-30T13:48:05+01:00
New Revision: b14a6f06cc8763830a25023edf5b9ccee18e426a
URL:
https://github.com/llvm/llvm-project/commit/b14a6f06cc8763830a25023edf5b9ccee18e426a
DIFF:
https://github.com/llvm/llvm-project/commit/b14a6f06cc8763830a25023edf5b9ccee18e426a.diff
Author: Simon Tatham
Date: 2021-12-31T16:43:53Z
New Revision: d50072f74e3ee50b750a618fcdf05739dec9542d
URL:
https://github.com/llvm/llvm-project/commit/d50072f74e3ee50b750a618fcdf05739dec9542d
DIFF:
https://github.com/llvm/llvm-project/commit/d50072f74e3ee50b750a618fcdf05739dec9542d.diff
LOG:
Author: Tomas Matheson
Date: 2022-01-03T16:02:36Z
New Revision: 4435d1819efec06e11461799fe83d6f148b098f4
URL:
https://github.com/llvm/llvm-project/commit/4435d1819efec06e11461799fe83d6f148b098f4
DIFF:
https://github.com/llvm/llvm-project/commit/4435d1819efec06e11461799fe83d6f148b098f4.diff
LOG
Author: Tomas Matheson
Date: 2022-01-04T15:22:10Z
New Revision: 8aea5d5951dc7d2130ad671423830a45e215c540
URL:
https://github.com/llvm/llvm-project/commit/8aea5d5951dc7d2130ad671423830a45e215c540
DIFF:
https://github.com/llvm/llvm-project/commit/8aea5d5951dc7d2130ad671423830a45e215c540.diff
LOG
Author: Tomas Matheson
Date: 2021-10-15T16:10:46+01:00
New Revision: 096ace55804d21a187b37448376ecd51c8e810e1
URL:
https://github.com/llvm/llvm-project/commit/096ace55804d21a187b37448376ecd51c8e810e1
DIFF:
https://github.com/llvm/llvm-project/commit/096ace55804d21a187b37448376ecd51c8e810e1.diff
tmatheson-arm wrote:
@jroelofs @ahmedbougacha Are you happy with the FEAT_CCIDX changes to Apple
processors?
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/18] [AArch64] Add a check for invalid default features
@@ -0,0 +1,90 @@
+// Use --implicit-check-not to ensure no additional CPUs are in this list
+
+// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --implicit-check-not={{[a-zA-Z0-9]}}
+// RUN: not %clang_cc1 -triple arm64--- -tune-cp
https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/104435
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@@ -0,0 +1,90 @@
+// Use --implicit-check-not to ensure no additional CPUs are in this list
+
+// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --implicit-check-not={{[a-zA-Z0-9]}}
+// RUN: not %clang_cc1 -triple arm64--- -tune-cp
tmatheson-arm wrote:
/cherry-pick 362142c4bb5cc657151f592e507f552d5b9f7dde
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/95805
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@@ -161,6 +162,39 @@ static int PrintSupportedExtensions(std::string TargetStr)
{
return 0;
}
+static int PrintEnabledExtensions(const TargetOptions& TargetOpts) {
+ std::string Error;
+ const llvm::Target *TheTarget =
+ llvm::TargetRegistry::lookupTarget(TargetOpts.
@@ -14,23 +14,36 @@
class Extension<
string TargetFeatureName,// String used for -target-feature and
-march, unless overridden.
string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
+ string ArchitectureFeatureName, // The extension's "FE
@@ -1841,7 +1868,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PROFILE, AArch64::AEK_RAND,
AArch64::AEK_FP16FML, AArch64::AEK_I8MM,
AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PER
https://github.com/tmatheson-arm commented:
LGTM, just some minor suggestions/clarifications.
https://github.com/llvm/llvm-project/pull/95805
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@@ -154,17 +156,39 @@ std::optional
AArch64::parseCpu(StringRef Name) {
return {};
}
-void AArch64::PrintSupportedExtensions(StringMap DescMap) {
+void AArch64::PrintSupportedExtensions() {
outs() << "All available -march extensions for AArch64\n\n"
<< "" <
@@ -116,12 +116,18 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisible
@@ -161,6 +162,39 @@ static int PrintSupportedExtensions(std::string TargetStr)
{
return 0;
}
+static int PrintEnabledExtensions(const TargetOptions& TargetOpts) {
+ std::string Error;
+ const llvm::Target *TheTarget =
+ llvm::TargetRegistry::lookupTarget(TargetOpts.
@@ -14,23 +14,36 @@
class Extension<
tmatheson-arm wrote:
The comment needs updating, something like:
> A SubtargetFeature that represents one or more Architecture Extensions, as
> defined in the Arm ARM and typically named `FEAT_*`. Each has an `AEK_*`
> entr
@@ -19,3 +19,17 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM
@@ -19,3 +19,17 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM
@@ -154,17 +156,39 @@ std::optional
AArch64::parseCpu(StringRef Name) {
return {};
}
-void AArch64::PrintSupportedExtensions(StringMap DescMap) {
+void AArch64::PrintSupportedExtensions() {
outs() << "All available -march extensions for AArch64\n\n"
<< "" <
@@ -1130,7 +1130,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_MTE, AArch64::AEK_SSBS,
AArch64::AEK_FP16,AArch64::AEK_FP16FML,
AArch64::AEK_SB, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA,
https://github.com/tmatheson-arm approved this pull request.
LGTM. Shame the order of the `-target-features` has to change again, but I can
see why (there are non-user-visible extensions in the ExtensionInfo table now,
which also need sorted).
https://github.com/llvm/llvm-project/pull/95805
__
tmatheson-arm wrote:
And please add a test to cover whatever broke.
https://github.com/llvm/llvm-project/pull/96832
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https://github.com/tmatheson-arm approved this pull request.
LGTM, I've added some thoughts but it's fine as it is.
https://github.com/llvm/llvm-project/pull/96249
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https://github.com/llvm/llvm-project/pull/96249
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@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35,
cortex-a34,
@@ -304,8 +304,21 @@ struct Alias {
StringRef Name;
};
-inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"},
- {"grace", "neoverse-v2"}};
+inline constexpr Alias CpuAliases[] = {
+{"cobalt-100", "neoverse-n2"},
+
@@ -88,10 +88,14 @@ StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
void AArch64::fillValidCPUArchList(SmallVectorImpl &Values) {
for (const auto &C : CpuInfos)
- Values.push_back(C.Name);
+Values.push_back(C.Name);
for (const auto &Alias : CpuAliases
@@ -304,8 +304,21 @@ struct Alias {
StringRef Name;
};
-inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"},
- {"grace", "neoverse-v2"}};
+inline constexpr Alias CpuAliases[] = {
tmatheson-arm wrote:
We
@@ -11523,10 +11525,16 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
const auto *OldTVA = OldFD->getAttr();
// If the old decl is NOT MultiVersioned yet, and we don't cause that
// to change, this is a simple redeclaration.
- if ((NewTA &
@@ -102,8 +102,9 @@ int __attribute__((target_version("sha2"))) combine(void) {
return 1; }
// expected-error@+1 {{multiversioned function declaration has a different
calling convention}}
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void)
{ return 2
@@ -11523,10 +11525,16 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
const auto *OldTVA = OldFD->getAttr();
// If the old decl is NOT MultiVersioned yet, and we don't cause that
// to change, this is a simple redeclaration.
- if ((NewTA &
@@ -11498,11 +11502,9 @@ static void patchDefaultTargetVersion(FunctionDecl
*From, FunctionDecl *To) {
if (MVKindTo == MultiVersionKind::None &&
(MVKindFrom == MultiVersionKind::TargetVersion ||
- MVKindFrom == MultiVersionKind::TargetClones)) {
-To->setIsMu
@@ -102,8 +102,9 @@ int __attribute__((target_version("sha2"))) combine(void) {
return 1; }
// expected-error@+1 {{multiversioned function declaration has a different
calling convention}}
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void)
{ return 2
tmatheson-arm wrote:
The only thing `AArch64TargetInfo::initFeatureMap` adds is features from the
selected CPU. IMHO this was not an appropriate place to be doing that. Since
#94279 the CPU features are added either by
`AArch64TargetInfo::parseTargetAttr` when dealing with
`__attribute(target
tmatheson-arm wrote:
I think a test demonstrating the problem would be the fastest way forward.
https://github.com/llvm/llvm-project/pull/96832
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@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35,
cortex-a34,
@@ -11465,6 +11465,10 @@ static bool CheckMultiVersionFirstFunction(Sema &S,
FunctionDecl *FD) {
// otherwise it is treated as a normal function.
if (TA && !TA->isDefaultVersion())
return false;
+ // The target_version attribute only causes Multiversioning if this
+
@@ -11523,10 +11525,17 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
const auto *OldTVA = OldFD->getAttr();
// If the old decl is NOT MultiVersioned yet, and we don't cause that
// to change, this is a simple redeclaration.
- if ((NewTA &
@@ -11576,22 +11584,6 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
}
}
- if (NewTVA) {
tmatheson-arm wrote:
If you are reasoning based on that, it might be good to add an assert checking
it:
```
assert(!OldTVA || OldT
@@ -11523,10 +11525,17 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
const auto *OldTVA = OldFD->getAttr();
// If the old decl is NOT MultiVersioned yet, and we don't cause that
// to change, this is a simple redeclaration.
- if ((NewTA &
@@ -11947,24 +11939,8 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
FunctionDecl *OldFD = OldDecl->getAsFunction();
- if (!OldFD->isMultiVersion() && MVKind == MultiVersionKind::None) {
-if (NewTVA || !OldFD->getAttr())
- return false;
-
@@ -11465,6 +11465,10 @@ static bool CheckMultiVersionFirstFunction(Sema &S,
FunctionDecl *FD) {
// otherwise it is treated as a normal function.
if (TA && !TA->isDefaultVersion())
return false;
+ // The target_version attribute only causes Multiversioning if this
+
https://github.com/tmatheson-arm deleted
https://github.com/llvm/llvm-project/pull/96628
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@@ -102,8 +102,9 @@ int __attribute__((target_version("sha2"))) combine(void) {
return 1; }
// expected-error@+1 {{multiversioned function declaration has a different
calling convention}}
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void)
{ return 2
@@ -102,8 +102,9 @@ int __attribute__((target_version("sha2"))) combine(void) {
return 1; }
// expected-error@+1 {{multiversioned function declaration has a different
calling convention}}
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void)
{ return 2
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/96628
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@@ -73,8 +73,6 @@ enum CPUFeatures {
FEAT_SSBS,
FEAT_SSBS2,
FEAT_BTI,
- FEAT_LS64,
- FEAT_LS64_V,
tmatheson-arm wrote:
@Wilco1 could you explain the scenario you are worried about in more detail?
What you posted above appears to be a snippet of a gene
https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/111386
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@@ -1125,31 +1125,32 @@ int caller(void) { return
used_def_without_default_decl() + used_decl_without_de
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+ls64,+neon" }
// C
https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/110297
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@@ -59,7 +59,7 @@ enum CPUFeatures {
FEAT_SVE_F32MM,
FEAT_SVE_F64MM,
FEAT_SVE2,
- FEAT_SVE_AES,
+ RESERVED_FEAT_SVE_AES, // previously used and now ABI legacy
tmatheson-arm wrote:
It would be nice to have a more complete explanation of these reserved v
https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/111673
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@@ -87,9 +86,8 @@ def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16",
"+sve,+bf16,+fullfp16,+fp-armv8,
def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16",
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM",
"+sve,+i8mm,+fullfp16,+fp-armv8,+
https://github.com/tmatheson-arm deleted
https://github.com/llvm/llvm-project/pull/109299
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https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/108383
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@@ -1059,7 +1059,7 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullFP16 = true;
HasFP16FML = true;
}
-if (Feature == "+mte")
+if (Feature == "+mte2")
tmatheson-arm wrote:
This breaks backwards compatibilit
@@ -1059,7 +1059,7 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullFP16 = true;
HasFP16FML = true;
}
-if (Feature == "+mte")
+if (Feature == "+mte2")
tmatheson-arm wrote:
Won't this break existing IR with
@@ -73,8 +73,6 @@ enum CPUFeatures {
FEAT_SSBS,
FEAT_SSBS2,
FEAT_BTI,
- FEAT_LS64,
- FEAT_LS64_V,
tmatheson-arm wrote:
> If object A uses bit 36, object B uses bit 35 and the runtime uses bit 34,
> how is it ever going to work?
Using them for what?
https://github.com/tmatheson-arm approved this pull request.
I'm surprised how complicated this was to do, but LGTM.
https://github.com/llvm/llvm-project/pull/118581
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https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/125063
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tmatheson-arm wrote:
I've just noticed 2/3 of these are redundant now since the existing neon
functions have been removed. I'll remove them.
https://github.com/llvm/llvm-project/pull/125063
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https
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/125063
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https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/125063
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https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/125063
>From 87d539860c11d7e0f021410b5947b5c25c8870d7 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 30 Jan 2025 15:37:08 +
Subject: [PATCH] [NFC] remove string literals from AArch64Types.def
---
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/125063
>From 87d539860c11d7e0f021410b5947b5c25c8870d7 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 30 Jan 2025 15:37:08 +
Subject: [PATCH 1/2] [NFC] remove string literals from AArch64Types.def
-
https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/125063
- Rename AArch64SVEACLETypes.def to AArch64Types.def
- Remove string literals from the macro calls
- Rename macros so that the hierarchy makes sense
>From 63159e8e82b56850213fb0e2479bd708f008ea81 Mon Sep
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/125063
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https://github.com/tmatheson-arm approved this pull request.
Makes sense to me.
https://github.com/llvm/llvm-project/pull/120753
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tmatheson-arm wrote:
Actually this is being added as a mandatory dependency of 9.4, should it not be
added as one of the default features instead?
https://github.com/llvm/llvm-project/pull/120753
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https://github.com/tmatheson-arm approved this pull request.
LGTM, assuming no objections to CPU changes.
https://github.com/llvm/llvm-project/pull/123336
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tmatheson-arm wrote:
I think so, but I would rather do it as a separate PR. There are a couple of
other things that could do with tidying up too.
https://github.com/llvm/llvm-project/pull/126945
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