https://github.com/tmatheson-arm approved this pull request.
LGMT, surprised this didn't blow up earlier.
https://github.com/llvm/llvm-project/pull/75783
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https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/75947
- [AArch64] add missing test case for v9.4-A
- [AArch64] Add FEAT_PAuthLR assembler support
- [AArch64] Codegen support for FEAT_PAuthLR
>From 3b1722f0cf3c0dd80ca5736724c77c36608b112b Mon Sep 17 00:00:00 2
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From a6039367acca5de4c925925c1cefc56097ae496a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From a6039367acca5de4c925925c1cefc56097ae496a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From 29eb3db45ac1782d6cdcff106bd6088f06bbc680 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/
Author: Tomas Matheson
Date: 2023-12-21T14:18:33Z
New Revision: 92dc23c0e054183e8adf41aad2a2609cefc392c0
URL:
https://github.com/llvm/llvm-project/commit/92dc23c0e054183e8adf41aad2a2609cefc392c0
DIFF:
https://github.com/llvm/llvm-project/commit/92dc23c0e054183e8adf41aad2a2609cefc392c0.diff
LOG
Author: Tomas Matheson
Date: 2023-12-21T14:18:33Z
New Revision: 5992ce90b8c0fac06436c3c86621fbf6d5398ee5
URL:
https://github.com/llvm/llvm-project/commit/5992ce90b8c0fac06436c3c86621fbf6d5398ee5
DIFF:
https://github.com/llvm/llvm-project/commit/5992ce90b8c0fac06436c3c86621fbf6d5398ee5.diff
LOG
tmatheson-arm wrote:
Manually merged to avoid squashing the commits:
92dc23c0e054183e8adf41aad2a2609cefc392c0
934b1099cbf14fa3f86a269dff957da8e5fb619f
5992ce90b8c0fac06436c3c86621fbf6d5398ee5
https://github.com/llvm/llvm-project/pull/75947
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Author: Tomas Matheson
Date: 2023-12-21T16:25:55Z
New Revision: 9f0f5587426a4ff24b240018cf8bf3acc3c566ae
URL:
https://github.com/llvm/llvm-project/commit/9f0f5587426a4ff24b240018cf8bf3acc3c566ae
DIFF:
https://github.com/llvm/llvm-project/commit/9f0f5587426a4ff24b240018cf8bf3acc3c566ae.diff
LOG
Author: Tomas Matheson
Date: 2023-12-21T18:32:55Z
New Revision: 7bd17212ef23a72ea224a037126d33d3e02553fe
URL:
https://github.com/llvm/llvm-project/commit/7bd17212ef23a72ea224a037126d33d3e02553fe
DIFF:
https://github.com/llvm/llvm-project/commit/7bd17212ef23a72ea224a037126d33d3e02553fe.diff
LOG
https://github.com/tmatheson-arm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/76237
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LGTM
https://github.com/llvm/llvm-project/pull/83277
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@@ -1369,13 +1369,20 @@ class TargetInfo : public TransferrableTargetInfo,
}
struct BranchProtectionInfo {
-LangOptions::SignReturnAddressScopeKind SignReturnAddr =
-LangOptions::SignReturnAddressScopeKind::None;
-LangOptions::SignReturnAddressKeyKind SignK
https://github.com/tmatheson-arm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/82785
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https://github.com/llvm/llvm-project/pull/83277
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https://github.com/llvm/llvm-project/pull/78270
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https://github.com/tmatheson-arm commented:
This looks like a great improvement over the existing system to me.
https://github.com/llvm/llvm-project/pull/78270
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@@ -3,8 +3,7 @@
// FEAT_D128 is optional (off by default) for v9.4a and older, and can be
enabled using +d128
// RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a%s 2>&1
| FileCheck %s --check-prefix=NOT_ENABLED
// RUN: %clang -### --target=aarch64-none-elf
@@ -308,6 +312,104 @@ inline constexpr ExtensionInfo Extensions[] = {
};
// clang-format on
+struct ExtensionSet {
+ // Set of extensions which are currently enabled.
+ ExtensionBitset Enabled;
+ // Set of extensions which have been enabled or disabled at any point. Used
+
@@ -1,20 +1,21 @@
// RAS is off by default for v8a, but can be enabled by +ras (this is not
architecturally valid)
// RUN: %clang --target=aarch64-none-elf -march=armv8a+ras -### -c %s 2>&1 |
FileCheck --check-prefix=CHECK-RAS %s
+// RUN: %clang --target=aarch64-none-elf -marc
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ retu
@@ -1,25 +1,25 @@
// RUN: %clang --target=aarch64 -### -c %s 2>&1 | FileCheck
-check-prefix=GENERIC-V8A %s
// RUN: %clang --target=aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck
-check-prefix=GENERIC-V8A %s
-// GENERIC-V8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ retu
@@ -1,9 +1,9 @@
// RUN: %clang -### --target=aarch64-none-elf -march=armv8.4a+memtag %s 2>&1 |
FileCheck %s
// RUN: %clang -### --target=aarch64-none-elf -march=armv8.5a+memtag %s 2>&1 |
FileCheck %s
+// RUN: %clang -### --target=aarch64-none-elf -mcpu=cortex-a510 %s 2>&1 |
F
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ retu
@@ -711,10 +819,10 @@ StringRef getArchExtFeature(StringRef ArchExt);
StringRef resolveCPUAlias(StringRef CPU);
// Information by Name
-std::optional getArchForCpu(StringRef CPU);
tmatheson-arm wrote:
Why the switch back to raw pointers from std::optional? Th
@@ -1,49 +1,51 @@
// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 |
FileCheck %s --check-prefix=SME-IMPLY
-// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+bf16"
+// SME-IMPLY: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme"
// RUN:
@@ -308,6 +312,104 @@ inline constexpr ExtensionInfo Extensions[] = {
};
// clang-format on
+struct ExtensionSet {
+ // Set of extensions which are currently enabled.
+ ExtensionBitset Enabled;
+ // Set of extensions which have been enabled or disabled at any point. Used
+
@@ -1,20 +1,21 @@
// RAS is off by default for v8a, but can be enabled by +ras (this is not
architecturally valid)
// RUN: %clang --target=aarch64-none-elf -march=armv8a+ras -### -c %s 2>&1 |
FileCheck --check-prefix=CHECK-RAS %s
+// RUN: %clang --target=aarch64-none-elf -marc
@@ -3,15 +3,14 @@
// FEAT_ITE is optional (off by default) for v8.9a/9.4a and older, and can be
enabled using +ite
// RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a %s 2>&1 |
FileCheck %s --check-prefix=NOT_ENABLED
// RUN: %clang -### --target=aarch64-none-
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ retu
Author: Tomas Matheson
Date: 2021-01-28T09:19:19Z
New Revision: 01b9e613c28b833327ab4de93d0638a5c8d3514f
URL:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f
DIFF:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f.diff
LOG
Author: Tomas Matheson
Date: 2021-01-28T09:19:19Z
New Revision: 01b9e613c28b833327ab4de93d0638a5c8d3514f
URL:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f
DIFF:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f.diff
LOG
Author: Tomas Matheson
Date: 2022-11-09T11:52:35Z
New Revision: 103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
URL:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94
DIFF:
https://github.com/llvm/llvm-project/commit/103bbddde66f4157b52c2b6d7532c1dd0dfcaf94.diff
LOG
Author: Tomas Matheson
Date: 2022-11-25T18:59:07Z
New Revision: a6aaa969f7caec58a994142f8d855861cf3a1463
URL:
https://github.com/llvm/llvm-project/commit/a6aaa969f7caec58a994142f8d855861cf3a1463
DIFF:
https://github.com/llvm/llvm-project/commit/a6aaa969f7caec58a994142f8d855861cf3a1463.diff
LOG
Author: Tomas Matheson
Date: 2022-12-01T12:50:17Z
New Revision: f57f086714bc7a1399acf05d5ca1d665237cd725
URL:
https://github.com/llvm/llvm-project/commit/f57f086714bc7a1399acf05d5ca1d665237cd725
DIFF:
https://github.com/llvm/llvm-project/commit/f57f086714bc7a1399acf05d5ca1d665237cd725.diff
LOG
Author: Tomas Matheson
Date: 2022-12-01T12:50:23Z
New Revision: 450de8008bb0ccb5dfc9dd69b6f5b434158772bd
URL:
https://github.com/llvm/llvm-project/commit/450de8008bb0ccb5dfc9dd69b6f5b434158772bd
DIFF:
https://github.com/llvm/llvm-project/commit/450de8008bb0ccb5dfc9dd69b6f5b434158772bd.diff
LOG
Author: Tomas Matheson
Date: 2022-12-01T13:06:54Z
New Revision: d1ef4b0a8da152fe4282f97c7c49f4930a3c66a2
URL:
https://github.com/llvm/llvm-project/commit/d1ef4b0a8da152fe4282f97c7c49f4930a3c66a2
DIFF:
https://github.com/llvm/llvm-project/commit/d1ef4b0a8da152fe4282f97c7c49f4930a3c66a2.diff
LOG
Author: Tomas Matheson
Date: 2022-12-01T15:30:07Z
New Revision: e83f1502f1be7a2a3b9a33f5a73867767e78ba6b
URL:
https://github.com/llvm/llvm-project/commit/e83f1502f1be7a2a3b9a33f5a73867767e78ba6b
DIFF:
https://github.com/llvm/llvm-project/commit/e83f1502f1be7a2a3b9a33f5a73867767e78ba6b.diff
LOG
Author: Tomas Matheson
Date: 2022-12-05T11:09:03Z
New Revision: 541a1371c05d77bb70a6173127d6544b9571dbab
URL:
https://github.com/llvm/llvm-project/commit/541a1371c05d77bb70a6173127d6544b9571dbab
DIFF:
https://github.com/llvm/llvm-project/commit/541a1371c05d77bb70a6173127d6544b9571dbab.diff
LOG
Author: Tomas Matheson
Date: 2024-02-19T12:19:16Z
New Revision: d022f32c73c57b59a9121eba909f5034e89c628e
URL:
https://github.com/llvm/llvm-project/commit/d022f32c73c57b59a9121eba909f5034e89c628e
DIFF:
https://github.com/llvm/llvm-project/commit/d022f32c73c57b59a9121eba909f5034e89c628e.diff
LOG
https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/96628
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tmatheson-arm wrote:
Thank you for the example, I understand what is happening how.
- Before #94279, we used to add CPU features in `AArch64::initFeatureMap`.
- In #94279, we decided that actually you should do that in the Driver, which
should put all `-target-features` it wants on the -cc1 com
@@ -445,4 +445,21 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
Features.push_back("+no-bti-at-return-twice");
+
+ // Parse AArch64 CPU Features
+ const Arg *CPUArg = Args.getLastArg(options::OPT_m
@@ -445,4 +445,21 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
Features.push_back("+no-bti-at-return-twice");
+
+ // Parse AArch64 CPU Features
+ const Arg *CPUArg = Args.getLastArg(options::OPT_m
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/97749
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https://github.com/llvm/llvm-project/pull/97824
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https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/97824
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@@ -15,22 +15,23 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/Host.h"
+#include
+
using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- StringMap featu
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https://github.com/llvm/llvm-project/pull/97824
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@@ -22,13 +22,13 @@ using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- if (std::optional> features =
+ if (const std::optional> features =
sys::getHostCPUFeatures(featu
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/97829
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https://github.com/tmatheson-arm approved this pull request.
LGTM, just based on what I can see from implementation of the existing bits in
the version field.
https://github.com/llvm/llvm-project/pull/96159
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tmatheson-arm wrote:
> Mind sticking it in a gist at least so folks can use it for downstream
> subtargets?
[Here you
go](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d)
https://github.com/llvm/llvm-project/pull/97829
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@@ -0,0 +1,24 @@
+// REQUIRES: aarch64-registered-target
tmatheson-arm wrote:
I've kept them as-is so that they still correspond to the [generating
script](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d).
https://github.com/llvm/llvm-pro
@@ -261,9 +261,9 @@ __attribute__((target_version("jscvt"))) int
default_def_with_version_decls(void
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+lse,-v9.5a" }
// CHECK: attribute
https://github.com/tmatheson-arm commented:
It's really hard to tell what is changing here because the existing tests are
so non-specific.
https://github.com/llvm/llvm-project/pull/97761
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@@ -4210,9 +4192,7 @@ void CodeGenModule::emitMultiVersionFunctions() {
return cast(Func);
};
-bool HasDefaultDecl = !FD->isTargetVersionMultiVersion();
-bool ShouldEmitResolver =
-!getContext().getTargetInfo().getTriple().isAArch64();
+bool Shoul
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/97761
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@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (on
@@ -4224,10 +4204,8 @@ void CodeGenModule::emitMultiVersionFunctions() {
llvm::Function *Func = createFunction(CurFD);
Options.emplace_back(Func, TA->getArchitecture(), Feats);
} else if (const auto *TVA = CurFD->getAttr()) {
-bool
@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (on
@@ -11,7 +11,7 @@ int __attribute__((target_version("fp+aes"))) fmv(void) {
return 6; }
int __attribute__((target_version("crc+ls64_v"))) fmv(void) { return 7; }
int __attribute__((target_version("bti"))) fmv(void) { return 8; }
int __attribute__((target_version("sme2"))) fmv(
tmatheson-arm wrote:
Are you planning to follow through with this?
https://github.com/llvm/llvm-project/pull/106304
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https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/104435
This adds a check that all ExtensionWithMArch which are marked as implied
features for an architecture are also present in the list of default features.
It doesn't make sense to have something mandatory b
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/104435
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tmatheson-arm wrote:
> > Cortex-A710 does not appear to have SSBS
> I believe this says it should be present:
You're right, I'll fix that.
I will also actually remove FeatureCCIDX from the 8.3 mandatory features.
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 1/9] [AArch64] Add a check for invalid default features
T
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/10] [AArch64] Add a check for invalid default features
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/11] [AArch64] Add a check for invalid default features
tmatheson-arm wrote:
Fixed SSBS and CCIDX.
> Does this also fix the "+nossbs" issue we saw earlier this week?
Yes, added a test
https://github.com/llvm/llvm-project/pull/104435/files#diff-e355e3951d191d3a32265d9bdeb101e4f49ddfa6049ef058cf9e1dfdf7c19ef3
https://github.com/llvm/llvm-project/pul
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/12] [AArch64] Add a check for invalid default features
@@ -283,9 +311,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
-// The apple-latest alias is backend only, do not expose it to -mcpu.
-
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/16] [AArch64] Add a check for invalid default features
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/17] [AArch64] Add a check for invalid default features
https://github.com/tmatheson-arm milestoned
https://github.com/llvm/llvm-project/pull/104435
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@@ -0,0 +1,382 @@
+// Use --implicit-check-not={{[a-zA-Z0-9]}} to ensure no additional CPUs are
in these lists
+
+// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix X86 --implicit-check-not={{[a-zA-Z0-9]}}
+// X86: er
https://github.com/tmatheson-arm approved this pull request.
Thanks. This will make downstream maintenance much easier after the initial
merge.
https://github.com/llvm/llvm-project/pull/104601
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@@ -718,12 +718,16 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
+ // Apple A14 a
@@ -286,7 +286,6 @@ void AArch64TargetInfo::getTargetDefinesARMV84A(const
LangOptions &Opts,
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEA
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92600
>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/4] [AArch64] set AppleA14 architecture version to 8.5
--
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92600
>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/5] [AArch64] set AppleA14 architecture version to 8.5
--
https://github.com/tmatheson-arm approved this pull request.
LGTM. The main change to point out is that the target attribute will no longer
accept internal feature names. I don't think it should ever have done so, but
we should get input from others. @davemgreen? There are references to existin
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/94279
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@@ -13665,9 +13665,9 @@ QualType
ASTContext::getCorrespondingSignedFixedPointType(QualType Ty) const {
}
// Given a list of FMV features, add each of their backend features to the
list.
tmatheson-arm wrote:
```suggestion
// Given a list of FMV features, ret
@@ -48,5 +48,5 @@ int test_versions() {
return code();
}
// CHECK: attributes #0 = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-// CHECK: attributes #1 = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-b
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92600
>From 518b83ab69c4852f7e7ea71c17df3f58e8ff50ef Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 17 May 2024 21:39:17 +0100
Subject: [PATCH 1/5] [AArch64] set AppleA14 architecture version to 8.5
--
Author: Tomas Matheson
Date: 2024-06-10T14:47:23+01:00
New Revision: 1b13bc05fe4a3b7b4916387543f0a64d41909e83
URL:
https://github.com/llvm/llvm-project/commit/1b13bc05fe4a3b7b4916387543f0a64d41909e83
DIFF:
https://github.com/llvm/llvm-project/commit/1b13bc05fe4a3b7b4916387543f0a64d41909e83.diff
https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/92600
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https://github.com/tmatheson-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/95231
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https://github.com/tmatheson-arm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/95214
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@@ -521,7 +521,14 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_SHA3, AArch64::AEK_FP16,
AArch64::AEK_FP16FML})},
-
+// Technically ap
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