https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/10] [AMDGPU] Use alias info to relax waitcounts for LDS
@@ -130,6 +130,8 @@
; GCN-O0-NEXT:MachineDominator Tree Construction
; GCN-O0-NEXT:Machine Natural Loop Construction
; GCN-O0-NEXT:MachinePostDominator Tree Construction
+; GCN-O0-NEXT:Basic Alias Analysis (stateless AA impl)
+; GCN-O0-NEXT:
@@ -1183,9 +1228,21 @@ bool
SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
// No need to wait before load from VMEM to LDS.
if (TII->mayWriteLDSThroughDMA(MI))
continue;
-unsigned RegNo = SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS;
+
@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/11] [AMDGPU] Use alias info to relax waitcounts for LDS
@@ -1183,9 +1228,21 @@ bool
SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
// No need to wait before load from VMEM to LDS.
if (TII->mayWriteLDSThroughDMA(MI))
continue;
-unsigned RegNo = SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS;
+
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/12] [AMDGPU] Use alias info to relax waitcounts for LDS
@@ -707,7 +723,40 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
(TII->isDS(Inst) || TII->mayWriteLDSThroughDMA(Inst))) {
// MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS
// written can be accessed. A load from LDS to VMEM
rampitec wrote:
> lgtm, but can still fix the -O0 thing
But where do I get TM in the getAnalysisUsage?
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/13] [AMDGPU] Use alias info to relax waitcounts for LDS
rampitec wrote:
> > lgtm, but can still fix the -O0 thing
>
> But where do I get TM in the getAnalysisUsage?
Found addUsedIfAvailable() which does the trick.
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/llvm/llvm-project/pull/78492
We currently force users to use a negative contant in the intrinsic call.
Changing it zext would break existing programs, so just sign extend an argument.
>From 01af6c9d8e80b810bbdec35dee38b1cf5d73cfe0 Mon Sep
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/78492
>From 01af6c9d8e80b810bbdec35dee38b1cf5d73cfe0 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri, 12 Jan 2024 15:07:53 -0800
Subject: [PATCH 1/3] [AMDGPU] Sign extend simm16 in setreg intrinsic
We
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/78492
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rampitec wrote:
> > > lgtm, but can still fix the -O0 thing
> >
> >
> > But where do I get TM in the getAnalysisUsage?
>
> MF.getTarget() (or maybe a pass parameter is necessary?)
There is no MF there of course.
https://github.com/llvm/llvm-project/pull/74537
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/llvm/llvm-project/pull/75974
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/69483
>From 27ab57359ea876c0ce78e42d8ab1ffc47348efb1 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 18 Oct 2023 09:50:44 -0700
Subject: [PATCH] [AMDGPU] Make S_MOV_B64_IMM_PSEUDO foldable
With the le
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/69483
>From 27ab57359ea876c0ce78e42d8ab1ffc47348efb1 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 18 Oct 2023 09:50:44 -0700
Subject: [PATCH] [AMDGPU] Make S_MOV_B64_IMM_PSEUDO foldable
With the le
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https://github.com/llvm/llvm-project/pull/69483
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Author: Stanislav Mekhanoshin
Date: 2020-09-23T11:39:50-07:00
New Revision: 59691dc8740c7eada7fcf5552e0d2377780c6fb7
URL:
https://github.com/llvm/llvm-project/commit/59691dc8740c7eada7fcf5552e0d2377780c6fb7
DIFF:
https://github.com/llvm/llvm-project/commit/59691dc8740c7eada7fcf5552e0d2377780c6f
Author: Stanislav Mekhanoshin
Date: 2020-11-05T16:29:16-08:00
New Revision: 4fcdfc4398bdf9295cd0259d6416a7dc1d2da47f
URL:
https://github.com/llvm/llvm-project/commit/4fcdfc4398bdf9295cd0259d6416a7dc1d2da47f
DIFF:
https://github.com/llvm/llvm-project/commit/4fcdfc4398bdf9295cd0259d6416a7dc1d2da4
Author: Stanislav Mekhanoshin
Date: 2020-10-15T12:41:18-07:00
New Revision: d1beb95d1241ec50bdf19db351d273374a146a4a
URL:
https://github.com/llvm/llvm-project/commit/d1beb95d1241ec50bdf19db351d273374a146a4a
DIFF:
https://github.com/llvm/llvm-project/commit/d1beb95d1241ec50bdf19db351d273374a146a
Author: Stanislav Mekhanoshin
Date: 2021-02-01T14:20:43-08:00
New Revision: 8e661d3d9c52ea9e5e68cbf699701d9cfa071a8f
URL:
https://github.com/llvm/llvm-project/commit/8e661d3d9c52ea9e5e68cbf699701d9cfa071a8f
DIFF:
https://github.com/llvm/llvm-project/commit/8e661d3d9c52ea9e5e68cbf699701d9cfa071a
Author: Stanislav Mekhanoshin
Date: 2021-02-25T08:31:59-08:00
New Revision: 502b3bfc6a713e5b6640faf48e72de08d7cb0aba
URL:
https://github.com/llvm/llvm-project/commit/502b3bfc6a713e5b6640faf48e72de08d7cb0aba
DIFF:
https://github.com/llvm/llvm-project/commit/502b3bfc6a713e5b6640faf48e72de08d7cb0a
Author: Stanislav Mekhanoshin
Date: 2021-03-01T09:00:30-08:00
New Revision: 21280d35d652788309176831bd88257b58f674f9
URL:
https://github.com/llvm/llvm-project/commit/21280d35d652788309176831bd88257b58f674f9
DIFF:
https://github.com/llvm/llvm-project/commit/21280d35d652788309176831bd88257b58f674
Author: Stanislav Mekhanoshin
Date: 2022-09-16T02:42:09-07:00
New Revision: e540965915a490f2f3cc51a09571ad5a573da05d
URL:
https://github.com/llvm/llvm-project/commit/e540965915a490f2f3cc51a09571ad5a573da05d
DIFF:
https://github.com/llvm/llvm-project/commit/e540965915a490f2f3cc51a09571ad5a573da0
Author: Stanislav Mekhanoshin
Date: 2023-01-24T10:52:42-08:00
New Revision: 4ab2246d486ba30c4b2d654323a0c0b97565c0f1
URL:
https://github.com/llvm/llvm-project/commit/4ab2246d486ba30c4b2d654323a0c0b97565c0f1
DIFF:
https://github.com/llvm/llvm-project/commit/4ab2246d486ba30c4b2d654323a0c0b97565c0
Author: Stanislav Mekhanoshin
Date: 2023-01-24T11:16:07-08:00
New Revision: 870b92977e89fe45d5fc39e26319b3b13670b699
URL:
https://github.com/llvm/llvm-project/commit/870b92977e89fe45d5fc39e26319b3b13670b699
DIFF:
https://github.com/llvm/llvm-project/commit/870b92977e89fe45d5fc39e26319b3b13670b6
Author: Stanislav Mekhanoshin
Date: 2023-01-26T10:34:36-08:00
New Revision: df0488369d32a8cb1604a85d008e602e4de24d05
URL:
https://github.com/llvm/llvm-project/commit/df0488369d32a8cb1604a85d008e602e4de24d05
DIFF:
https://github.com/llvm/llvm-project/commit/df0488369d32a8cb1604a85d008e602e4de24d
rampitec wrote:
> > I've just tested this on 1 graphics shaders and it seems to make no
> > difference at all. I tried gfx900 and gfx1100. Can anyone else from the
> > graphics team confirm this?
>
> I can confirm no difference on gfx1102
gfx11 is the same as gfx10, it just bails because
rampitec wrote:
> I've just tested this on 1 graphics shaders and it seems to make no
> difference at all. I tried gfx900 and gfx1100. Can anyone else from the
> graphics team confirm this?
It seems the most impact is on the pre-gfx9 targets, very similar to
https://github.com/llvm/llvm-p
rampitec wrote:
> I've just tested this on 1 graphics shaders and it seems to make no
> difference at all. I tried gfx900 and gfx1100. Can anyone else from the
> graphics team confirm this?
It seems the most impact is on the pre-gfx9 targets, very similar to
https://github.com/llvm/llvm-p
rampitec wrote:
I have measured compile time performance impact with timing
check-llvm-codegen-amdgpu on the release build:
```
before the patch: 11.06s
add folding:11.09s +0.2%
remove folding from shrink: 11.02s -0.4%
```
In general the impact smaller than run to run
rampitec wrote:
I have measured compile time performance impact with timing
check-llvm-codegen-amdgpu on the release build:
```
before the patch: 11.06s
add folding:11.09s +0.2%
remove folding from shrink: 11.02s -0.4%
```
In general the impact smaller than run to run
rampitec wrote:
> I've taken another look at this. The patch does not show any benefit from
> running another `SIFoldOperands` pass _after_ `SIShrinkInstructions` per se;
> you get exactly the same results (modulo a couple of add instructions that
> have their operands commuted differently) if
rampitec wrote:
> I've taken another look at this. The patch does not show any benefit from
> running another `SIFoldOperands` pass _after_ `SIShrinkInstructions` per se;
> you get exactly the same results (modulo a couple of add instructions that
> have their operands commuted differently) if
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/68740
>From cc9e065a9218eb36750a2c2a4a4d08fae3f329fa Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Oct 2023 13:36:25 -0700
Subject: [PATCH 1/3] [AMDGPU] Change the representation of double literals
@@ -2241,7 +2242,10 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst,
int64_t Val, bool ApplyMo
return;
}
-Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
+if (isInt<32>(Val) || isUInt<32>(Val))
+ Val = AMDGPU::isSISrcFPOperand(InstDesc, OpNu
rampitec wrote:
> LGTM modulo one remaining comment about validateVOPLiteral.
Done.
https://github.com/llvm/llvm-project/pull/68740
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/68740
>From cc9e065a9218eb36750a2c2a4a4d08fae3f329fa Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Oct 2023 13:36:25 -0700
Subject: [PATCH 1/6] [AMDGPU] Change the representation of double literals
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/68740
>From cc9e065a9218eb36750a2c2a4a4d08fae3f329fa Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Oct 2023 13:36:25 -0700
Subject: [PATCH 1/6] [AMDGPU] Change the representation of double literals
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/68740
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rampitec wrote:
> Hi @rampitec
>
> With UBSan built binaries the MC/AMDGPU/literals.s testcase fails and
> triggers UB like
>
> ```
> 07:33:04 ../lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:2246:59: runtime
> error: left shift of negative value -54321
> 07:33:04 SUMMARY: UndefinedBehavior
rampitec wrote:
> > Hi @rampitec
> > With UBSan built binaries the MC/AMDGPU/literals.s testcase fails and
> > triggers UB like
> > ```
> > 07:33:04 ../lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:2246:59:
> > runtime error: left shift of negative value -54321
> > 07:33:04 SUMMARY: Undefined
rampitec wrote:
I have a small little problem that I cannot build tip now:
```
FAILED: tools/llvm-remarkutil/CMakeFiles/llvm-remarkutil.dir/RemarkCounter.cpp.o
CCACHE_CPP2=yes CCACHE_HASHDIR=yes /usr/bin/ccache /usr/bin/clang++
-DGTEST_HAS_RTTI=0 -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GNU_SOURCE
-D_
rampitec wrote:
> I suppose left shift of negative values is undefined because if you shift out
> the sign bit you can overflow and get a positive value.
Sounds like BS. It is defined. Unexpected maybe.
https://github.com/llvm/llvm-project/pull/68740
___
rampitec wrote:
> I suppose left shift of negative values is undefined because if you shift out
> the sign bit you can overflow and get a positive value.
https://github.com/llvm/llvm-project/pull/68959
https://github.com/llvm/llvm-project/pull/68740
Author: rampitec
Date: Thu Apr 6 13:15:44 2017
New Revision: 299678
URL: http://llvm.org/viewvc/llvm-project?rev=299678&view=rev
Log:
[AMDGPU] Translate reqd_work_group_size into amdgpu_flat_work_group_size
These two attributes specify the same info in a different way.
AMGPU BE only checks the l
Author: rampitec
Date: Thu Jan 26 10:49:21 2017
New Revision: 293190
URL: http://llvm.org/viewvc/llvm-project?rev=293190&view=rev
Log:
Use TargetMachine adjustPassManager hook
Differential Revision: https://reviews.llvm.org/D28340
Modified:
cfe/trunk/lib/CodeGen/BackendUtil.cpp
Modified: cf
Author: rampitec
Date: Tue Nov 15 12:58:03 2016
New Revision: 287006
URL: http://llvm.org/viewvc/llvm-project?rev=287006&view=rev
Log:
[AMDGPU] Add wave barrier builtin
The wave barrier represents the discardable barrier. Its main purpose is to
carry convergent attribute, thus preventing illegal
@@ -0,0 +1,8 @@
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s |
FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s |
FileCheck %s
+
+# CHECK: v_dot2_bf16_bf16 v5, v1, v2, 0x42c8
rampitec wro
@@ -2652,6 +2652,23 @@ bool isInlinableLiteral32(int32_t Literal, bool
HasInv2Pi) {
(Val == 0x3e22f983 && HasInv2Pi);
}
+bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi) {
+ if (!HasInv2Pi)
+return false;
rampitec wrote:
It does not
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s
+
+v_dot2_bf16_bf16 v5, v1, v2, 100.0
+// CHECK: v_dot2_bf16_bf16 v5, v1, v2, 0x42c8 ; encoding:
[0x05,0x00,0x
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s
+
+v_dot2_bf16_bf16 v5, v1, v2, 100.0
+// CHECK: v_dot2_bf16_bf16 v5, v1, v2, 0x42c8 ; encoding:
[0x05,0x00,0x
https://github.com/rampitec approved this pull request.
Thanks. There are definitely at least 2 outstanding problems, but it seems
there are no regressions comparing to what we have now. LGTM.
https://github.com/llvm/llvm-project/pull/80908
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https://github.com/llvm/llvm-project/pull/82044
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https://github.com/llvm/llvm-project/pull/97633
None
>From dc9d1e2039981bb412e68975570d9911511bb880 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 3 Jul 2024 13:12:21 -0700
Subject: [PATCH] [AMDGPU] Report error in clang if wave32 is request
@@ -188,8 +188,12 @@ bool AMDGPUTargetInfo::initFeatureMap(
// TODO: Should move this logic into TargetParser
std::string ErrorMsg;
- if (!insertWaveSizeFeature(CPU, getTriple(), Features, ErrorMsg)) {
-Diags.Report(diag::err_invalid_feature_combination) << ErrorMsg;
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/97633
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@@ -188,8 +188,12 @@ bool AMDGPUTargetInfo::initFeatureMap(
// TODO: Should move this logic into TargetParser
std::string ErrorMsg;
- if (!insertWaveSizeFeature(CPU, getTriple(), Features, ErrorMsg)) {
-Diags.Report(diag::err_invalid_feature_combination) << ErrorMsg;
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107133
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH 1/4] [AMDGPU] Add target intrinsic for s_prefetch_data
-
@@ -2689,6 +2689,12 @@ def int_amdgcn_global_load_tr_b128 :
AMDGPULoadIntrinsic;
def int_amdgcn_wave_id :
DefaultAttrsIntrinsic<[llvm_i32_ty], [], [NoUndef, IntrNoMem,
IntrSpeculatable]>;
+def int_amdgcn_s_prefetch_data :
+ Intrinsic<[], [llvm_anyptr_ty, llvm_i32_ty],
---
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/107293
None
>From 8361742ca5fe20a3168b3274166909412e225184 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Sep 2024 12:00:27 -0700
Subject: [PATCH] [AMDGPU] Add target intrinsic for s_buffer_prefetc
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/107133
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@@ -9934,6 +9934,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops);
return SDValue(NewMI, 0);
}
+ case Intrinsic::amdgcn_s_prefetch_data: {
+// For non-global address space preserve the
@@ -9934,6 +9934,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops);
return SDValue(NewMI, 0);
}
+ case Intrinsic::amdgcn_s_prefetch_data: {
+// For non-global address space preserve the
@@ -9934,6 +9934,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops);
return SDValue(NewMI, 0);
}
+ case Intrinsic::amdgcn_s_prefetch_data: {
+// For non-global address space preserve the
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107293
>From 8361742ca5fe20a3168b3274166909412e225184 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Sep 2024 12:00:27 -0700
Subject: [PATCH 1/2] [AMDGPU] Add target intrinsic for s_buffer_prefetch_
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1200 < %s | FileCheck
--check-prefix=GCN %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 < %s | FileC
rampitec wrote:
> I think the parent needs some revision for global/flat/infer handling
Do you like this more? https://github.com/llvm/llvm-project/pull/107624
https://github.com/llvm/llvm-project/pull/107293
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@@ -61,6 +61,8 @@ BUILTIN(__builtin_amdgcn_s_waitcnt, "vIi", "n")
BUILTIN(__builtin_amdgcn_s_sendmsg, "vIiUi", "n")
BUILTIN(__builtin_amdgcn_s_sendmsghalt, "vIiUi", "n")
BUILTIN(__builtin_amdgcn_s_barrier, "v", "n")
+BUILTIN(__builtin_amdgcn_s_ttracedata, "vi", "n")
+BUILTIN(__
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/88076
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@@ -1534,6 +1534,12 @@ def FeatureISAVersion11_5_1 : FeatureSet<
FeatureVGPRSingleUseHintInsts,
Feature1_5xVGPRs])>;
+def FeatureISAVersion11_5_2 : FeatureSet<
rampitec wrote:
Looks the same as 1150?
https://github.com/llvm/llvm-project/pull/94534
@@ -1534,6 +1534,12 @@ def FeatureISAVersion11_5_1 : FeatureSet<
FeatureVGPRSingleUseHintInsts,
Feature1_5xVGPRs])>;
+def FeatureISAVersion11_5_2 : FeatureSet<
rampitec wrote:
I don't know, but if they are I have a question why a new target needed?
@@ -1534,6 +1534,12 @@ def FeatureISAVersion11_5_1 : FeatureSet<
FeatureVGPRSingleUseHintInsts,
Feature1_5xVGPRs])>;
+def FeatureISAVersion11_5_2 : FeatureSet<
rampitec wrote:
Then I defer review to Jay.
https://github.com/llvm/llvm-project/pull/94
https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/99540
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/99551
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https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/107133
None
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH] [AMDGPU] Add target intrinsic for s_prefetch_data
@@ -19489,6 +19489,12 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
F, {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1)),
EmitScalarExpr(E->getArg(2)), EmitScalarExpr(E->getArg(3))});
}
+ case AMDGPU::BI__builtin_amdgcn_s
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107133
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH 1/2] [AMDGPU] Add target intrinsic for s_prefetch_data
-
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107133
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH 1/3] [AMDGPU] Add target intrinsic for s_prefetch_data
-
@@ -19489,6 +19489,12 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
F, {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1)),
EmitScalarExpr(E->getArg(2)), EmitScalarExpr(E->getArg(3))});
}
+ case AMDGPU::BI__builtin_amdgcn_s
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1200 < %s | FileCheck
--check-prefixes=GCN,SDAG %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 < %s
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/97633
>From dc9d1e2039981bb412e68975570d9911511bb880 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 3 Jul 2024 13:12:21 -0700
Subject: [PATCH 1/2] [AMDGPU] Report error in clang if wave32 is requested
@@ -188,8 +188,12 @@ bool AMDGPUTargetInfo::initFeatureMap(
// TODO: Should move this logic into TargetParser
std::string ErrorMsg;
- if (!insertWaveSizeFeature(CPU, getTriple(), Features, ErrorMsg)) {
-Diags.Report(diag::err_invalid_feature_combination) << ErrorMsg;
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/97633
>From dc9d1e2039981bb412e68975570d9911511bb880 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 3 Jul 2024 13:12:21 -0700
Subject: [PATCH 1/3] [AMDGPU] Report error in clang if wave32 is requested
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/97633
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rampitec wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Fixed https://github.com/llvm/llvm-project/pull/98231
Sorry.
Stas
From: LLVM Continuous Integration ***@***.***>
Date: Tuesday, July 9, 2024 at 14:37
To: llvm/llvm-project ***@***.***>
Cc: Mekhanoshin, Stanislav ***@***.*
rampitec wrote:
> /build/buildbot/premerge-monolithic-linux/llvm-project/flang/lib/Frontend/CompilerInstance.cpp:226:44:
> error: too many arguments to function call, expected 3, have 4
Fixed.
https://github.com/llvm/llvm-project/pull/97633
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@@ -2466,23 +2466,24 @@ def int_amdgcn_perm :
// GFX9 Intrinsics
//===--===//
-class AMDGPUGlobalLoadLDS : Intrinsic <
- [],
- [LLVMQualPointerType<1>, // Base global pointer to load from
- LL
@@ -2466,23 +2466,20 @@ def int_amdgcn_perm :
// GFX9 Intrinsics
//===--===//
-class AMDGPUGlobalLoadLDS : Intrinsic <
- [],
- [LLVMQualPointerType<1>, // Base global pointer to load from
- LL
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/92962
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Author: Stanislav Mekhanoshin
Date: 2022-03-02T13:54:48-08:00
New Revision: 2e2e64df4a4f6580499fa09c3c16d5c39d9dd4cb
URL:
https://github.com/llvm/llvm-project/commit/2e2e64df4a4f6580499fa09c3c16d5c39d9dd4cb
DIFF:
https://github.com/llvm/llvm-project/commit/2e2e64df4a4f6580499fa09c3c16d5c39d9dd4
Author: Stanislav Mekhanoshin
Date: 2022-03-07T12:32:02-08:00
New Revision: 932f628121d85281ef1a2410dd158a735acdea5e
URL:
https://github.com/llvm/llvm-project/commit/932f628121d85281ef1a2410dd158a735acdea5e
DIFF:
https://github.com/llvm/llvm-project/commit/932f628121d85281ef1a2410dd158a735acdea
Author: Stanislav Mekhanoshin
Date: 2022-03-07T23:13:02-08:00
New Revision: 9eabea396814c5580978cd4766b524bef57844cf
URL:
https://github.com/llvm/llvm-project/commit/9eabea396814c5580978cd4766b524bef57844cf
DIFF:
https://github.com/llvm/llvm-project/commit/9eabea396814c5580978cd4766b524bef57844
Author: Stanislav Mekhanoshin
Date: 2021-05-06T16:17:33-07:00
New Revision: c714d037857f9c8e3bbe32e22ec22279121c378d
URL:
https://github.com/llvm/llvm-project/commit/c714d037857f9c8e3bbe32e22ec22279121c378d
DIFF:
https://github.com/llvm/llvm-project/commit/c714d037857f9c8e3bbe32e22ec22279121c37
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