Author: rampitec
Date: Fri Apr 5 11:25:00 2019
New Revision: 357792
URL: http://llvm.org/viewvc/llvm-project?rev=357792&view=rev
Log:
[AMDGPU] rename vi-insts into gfx8-insts
Differential Revision: https://reviews.llvm.org/D60293
Modified:
cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
Author: rampitec
Date: Fri Feb 8 16:34:41 2019
New Revision: 353588
URL: http://llvm.org/viewvc/llvm-project?rev=353588&view=rev
Log:
[AMDGPU] Split dot-insts feature
Differential Revision: https://reviews.llvm.org/D57972
Modified:
cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
cfe/tr
Author: rampitec
Date: Thu Jun 13 16:47:59 2019
New Revision: 363341
URL: http://llvm.org/viewvc/llvm-project?rev=363341&view=rev
Log:
[AMDGPU] gfx1010 wave32 clang support
Differential Revision: https://reviews.llvm.org/D63209
Modified:
cfe/trunk/docs/ClangCommandLineReference.rst
cfe/t
Author: rampitec
Date: Thu Jun 13 17:33:59 2019
New Revision: 363345
URL: http://llvm.org/viewvc/llvm-project?rev=363345&view=rev
Log:
[AMDGPU] gfx1011/gfx1012 clang support
Differential Revision: https://reviews.llvm.org/D63308
Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/
Author: rampitec
Date: Wed Aug 14 13:55:15 2019
New Revision: 368917
URL: http://llvm.org/viewvc/llvm-project?rev=368917&view=rev
Log:
[AMDGPU] Do not assume a default GCN target
Differential Revision: https://reviews.llvm.org/D66246
Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/t
Author: rampitec
Date: Tue Jul 9 11:19:00 2019
New Revision: 365528
URL: http://llvm.org/viewvc/llvm-project?rev=365528&view=rev
Log:
[AMDGPU] gfx908 clang target
Differential Revision: https://reviews.llvm.org/D64430
Modified:
cfe/trunk/include/clang/Basic/Cuda.h
cfe/trunk/lib/Basic/Cu
Author: rampitec
Date: Mon May 13 16:15:59 2019
New Revision: 360634
URL: http://llvm.org/viewvc/llvm-project?rev=360634&view=rev
Log:
[AMDGPU] gfx1010 clang target
Differential Revision: https://reviews.llvm.org/D61875
Modified:
cfe/trunk/docs/ClangCommandLineReference.rst
cfe/trunk/inc
Author: rampitec
Date: Wed Jan 9 19:25:47 2019
New Revision: 350794
URL: http://llvm.org/viewvc/llvm-project?rev=350794&view=rev
Log:
[AMDGPU] Separate feature dot-insts
Differential Revision: https://reviews.llvm.org/D56525
Modified:
cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
cfe
Author: Stanislav Mekhanoshin
Date: 2020-06-12T11:57:40-07:00
New Revision: 58de24ce6cb413afea1470ec183f3fc5d9ca6817
URL:
https://github.com/llvm/llvm-project/commit/58de24ce6cb413afea1470ec183f3fc5d9ca6817
DIFF:
https://github.com/llvm/llvm-project/commit/58de24ce6cb413afea1470ec183f3fc5d9ca68
Author: Stanislav Mekhanoshin
Date: 2020-08-05T12:36:26-07:00
New Revision: ea7d0e2996ec6b72a08dbef26dadf217458ab382
URL:
https://github.com/llvm/llvm-project/commit/ea7d0e2996ec6b72a08dbef26dadf217458ab382
DIFF:
https://github.com/llvm/llvm-project/commit/ea7d0e2996ec6b72a08dbef26dadf217458ab3
Author: Stanislav Mekhanoshin
Date: 2020-08-05T12:39:03-07:00
New Revision: 105608a4c2821ca8f8340104614c1176ed1ed82d
URL:
https://github.com/llvm/llvm-project/commit/105608a4c2821ca8f8340104614c1176ed1ed82d
DIFF:
https://github.com/llvm/llvm-project/commit/105608a4c2821ca8f8340104614c1176ed1ed8
@@ -292,13 +292,17 @@
TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_f16_w32, "V8fV16hV16hV8f", "nc
TARGET_BUILTIN(__builtin_amdgcn_wmma_f32_16x16x16_bf16_w32, "V8fV16sV16sV8f",
"nc", "gfx11-insts")
TARGET_BUILTIN(__builtin_amdgcn_wmma_f16_16x16x16_f16_w32,
"V16hV16hV16hV1
https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/70669
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rampitec wrote:
Any tests?
https://github.com/llvm/llvm-project/pull/71989
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@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
@@ -1209,6 +1209,15 @@ def G_FENCE : GenericInstruction {
let hasSideEffects = true;
}
+// Generic opcode equivalent to the llvm.prefetch intrinsic.
+def G_PREFETCH : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins ptype0:$address, i32imm:$rw
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/7] [AMDGPU] Use alias info to relax waitcounts for LDS D
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/71989
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/70484
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https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/70395
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https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/70395
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https://github.com/rampitec commented:
Also needed negative tests that gfx11-insts feature is required (using gfx1030
target for example) and for the immediate arguments. See for example
builtins-amdgcn-gfx11-err.cl and builtins-amdgcn-fp-atomics-gfx11-err.cl.
https://github.com/llvm/llvm-proj
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/7] [AMDGPU] Use alias info to relax waitcounts for LDS D
rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/7] [AMDGPU] Use alias info to relax waitcounts for LDS D
rampitec wrote:
To make it easier I am splitting the patch. I have pre-comitted the test, and
there is a part which fixes lack of wait on GFX10 :
https://github.com/llvm/llvm-project/pull/75245
https://github.com/llvm/llvm-project/pull/74537
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rampitec wrote:
Another part is improving memoperand info:
https://github.com/llvm/llvm-project/pull/75247. This is NFCI just by itself.
https://github.com/llvm/llvm-project/pull/74537
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rampitec wrote:
Yet another part to fix disjoint memory checks with LDS DMA:
https://github.com/llvm/llvm-project/pull/75249
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/7] [AMDGPU] Use alias info to relax waitcounts for LDS D
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/75249
>From 82606c4447e8aa8edde90ed420f1c48707967695 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 12 Dec 2023 13:45:47 -0800
Subject: [PATCH] [AMDGPU] Fix lack of LDS DMA check in the AA handling
S
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/75249
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@@ -3656,8 +3656,8 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const
MachineInstr &MIa,
// underlying address space, even if it was lowered to a different one,
// e.g. private accesses lowered to use MUBUF instructions on a scratch
// buffer.
- if (isDS(MIa)) {
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/75249
>From 82606c4447e8aa8edde90ed420f1c48707967695 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 12 Dec 2023 13:45:47 -0800
Subject: [PATCH 1/2] [AMDGPU] Fix lack of LDS DMA check in the AA handlin
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/8] [AMDGPU] Use alias info to relax waitcounts for LDS D
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/9] [AMDGPU] Use alias info to relax waitcounts for LDS D
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/75249
>From 82606c4447e8aa8edde90ed420f1c48707967695 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 12 Dec 2023 13:45:47 -0800
Subject: [PATCH 1/3] [AMDGPU] Fix lack of LDS DMA check in the AA handlin
@@ -3656,8 +3656,8 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const
MachineInstr &MIa,
// underlying address space, even if it was lowered to a different one,
// e.g. private accesses lowered to use MUBUF instructions on a scratch
// buffer.
- if (isDS(MIa)) {
rampitec wrote:
Ping. This one seems obvious to me.
https://github.com/llvm/llvm-project/pull/75249
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https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/75249
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https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/75247
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/9] [AMDGPU] Use alias info to relax waitcounts for LDS D
rampitec wrote:
All split off parts were merged and this patch is merged with main. Only
waitcount insertion pass changes remained here.
https://github.com/llvm/llvm-project/pull/74537
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rampitec wrote:
> How does this work in a case like this?
>
> ```
> call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3)
> @lds.3, i32 4, i32 0, i32 0, i32 0, i32 0)
> call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3)
> %ptr, i32 4, i32 0, i32
rampitec wrote:
> Test case:
>
> ```
> @lds.0 = internal addrspace(3) global [64 x float] poison, align 16
> @lds.1 = internal addrspace(3) global [64 x float] poison, align 16
>
> declare void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr
> addrspace(3) nocapture, i32 %size, i32 %voff
rampitec wrote:
> This is still correct, pointer argument cannot alias module global. A pointer
> argument to a kernel is an LDS external requested by the host side, and host
> cannot see module LDS.
I.e. that is really the point of the patch: if we are able to definitively
identify an LDS ob
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/10] [AMDGPU] Use alias info to relax waitcounts for LDS
rampitec wrote:
> > This is still correct, pointer argument cannot alias module global. A
> > pointer argument to a kernel is an LDS external requested by the host side,
> > and host cannot see module LDS.
>
> I.e. that is really the point of the patch: if we are able to definitively
> identi
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/75974
LDA DMA loads increase VMCNT and a load from the LDS stored must
wait on this counter to only read memory after it is written.
Wait count insertion pass does not track memory dependencies, it
tracks register depe
rampitec wrote:
Actually since I am only using alias scope I can avoid all alias analysis
altogether and only compare alias scope. This does not need an analysis pass,
calls to mayAlias, and in general simpler code. You can see an alternative PR
if you like it more: https://github.com/llvm/llv
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/75974
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/12] [AMDGPU] Use alias info to relax waitcounts for LDS
rampitec wrote:
One thing to note: this alias.scope I am creating myself in the module LDS
lowering, so I do exactly know what to expect. And then since there is this
module LDS lowering even if any alias scope would be created before (which
never happens, much less for an intrinsic call) it i
rampitec wrote:
This is the place I am creating it: https://reviews.llvm.org/D108315
https://github.com/llvm/llvm-project/pull/75974
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/72709
>From 423a0d1d4640680c5db3382ca0652fe85051ad8d Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri, 17 Nov 2023 10:52:13 -0800
Subject: [PATCH] [AMDGPU] Fix folding of v2i16/v2f16 splat imms
We can u
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/72709
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https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/72709
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rampitec wrote:
After some digging I believe with this bug fixed we are fine now. Since we are
passing all bf16 inputs as i16 we can only inline small integers, and inline
integer 1 shall be the same as using 1 in an input register I believe. Although
we are missing a potential optimization, s
rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/74537
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rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/75974
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@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/2
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Author: Stanislav Mekhanoshin
Date: 2022-03-24T12:12:52-07:00
New Revision: 27439a764230e5eb54568b2fc053a20c9005970f
URL:
https://github.com/llvm/llvm-project/commit/27439a764230e5eb54568b2fc053a20c9005970f
DIFF:
https://github.com/llvm/llvm-project/commit/27439a764230e5eb54568b2fc053a20c900597
Author: Stanislav Mekhanoshin
Date: 2022-03-24T12:40:42-07:00
New Revision: 6e3e14f600afa1fa64a699df97c8bbac6d0f8b5a
URL:
https://github.com/llvm/llvm-project/commit/6e3e14f600afa1fa64a699df97c8bbac6d0f8b5a
DIFF:
https://github.com/llvm/llvm-project/commit/6e3e14f600afa1fa64a699df97c8bbac6d0f8b
Author: Stanislav Mekhanoshin
Date: 2022-02-17T11:07:03-08:00
New Revision: b0aa1946dfe1d204e49b8238c4960f64a68f31d5
URL:
https://github.com/llvm/llvm-project/commit/b0aa1946dfe1d204e49b8238c4960f64a68f31d5
DIFF:
https://github.com/llvm/llvm-project/commit/b0aa1946dfe1d204e49b8238c4960f64a68f31
Author: Stanislav Mekhanoshin
Date: 2022-07-18T11:48:43-07:00
New Revision: 9fa5a6b7e8a292ec91b844a622836d2990ef5796
URL:
https://github.com/llvm/llvm-project/commit/9fa5a6b7e8a292ec91b844a622836d2990ef5796
DIFF:
https://github.com/llvm/llvm-project/commit/9fa5a6b7e8a292ec91b844a622836d2990ef57
Author: Stanislav Mekhanoshin
Date: 2022-07-18T11:49:56-07:00
New Revision: 2695f0a688e9d26fcb0f3a4b686a2783f2eb145c
URL:
https://github.com/llvm/llvm-project/commit/2695f0a688e9d26fcb0f3a4b686a2783f2eb145c
DIFF:
https://github.com/llvm/llvm-project/commit/2695f0a688e9d26fcb0f3a4b686a2783f2eb14
Author: Stanislav Mekhanoshin
Date: 2022-07-18T12:12:41-07:00
New Revision: 523a99c0eb0331680905e9ef6fbdd114f4ee7a47
URL:
https://github.com/llvm/llvm-project/commit/523a99c0eb0331680905e9ef6fbdd114f4ee7a47
DIFF:
https://github.com/llvm/llvm-project/commit/523a99c0eb0331680905e9ef6fbdd114f4ee7a
https://github.com/rampitec commented:
Do you want to rename intrinsics as well? Because now intrinsic names do not
match builtin names.
https://github.com/llvm/llvm-project/pull/86202
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@@ -432,13 +432,15 @@ TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi",
"n", "gfx12-insts")
TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts")
TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts")
-TARGET_BUILTIN(__builti
rampitec wrote:
> > Do you want to rename intrinsics as well? Because now intrinsic names do
> > not match builtin names.
>
> Do we have to match builtins with intrinsics? Renaming intrinsics here means
> we will have to duplicate the intrinsics.
Is that because of the mangling?
https://gith
rampitec wrote:
> I don't think intrinsics are meant for users. Builtins are the user-facing
> front. :-)
Depending on who you consider an user. Are folks writing MLIR generators users?
https://github.com/llvm/llvm-project/pull/86202
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rampitec wrote:
> global_load_re_b64
Type global_load_re_b64.
https://github.com/llvm/llvm-project/pull/86313
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@@ -0,0 +1,8 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s
+
+v_dot2_bf16_bf16 v5, v1, v2, 100.0
+// CHECK: v_dot2_bf16_bf16 v5, v1, v2, 0x42c8 ; encoding:
[0x05,0x00,0x
@@ -1562,8 +1562,9 @@ bool IRTranslator::translateBitCast(const User &U,
bool IRTranslator::translateCast(unsigned Opcode, const User &U,
MachineIRBuilder &MIRBuilder) {
- if (U.getType()->getScalarType()->isBFloatTy() ||
- U.getOperand(0
@@ -521,8 +521,11 @@ void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm,
uint8_t OpType,
if (printImmediateFloat32(Imm, STI, O))
return;
break;
+ case AMDGPU::OPERAND_REG_IMM_V2BF16:
case AMDGPU::OPERAND_REG_IMM_V2FP16:
+ case AMDGPU::OPERAND_REG_INLINE
@@ -79,17 +79,17 @@ define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT:v_mov_b32_e32 v2, s1
; GFX11-NEXT:s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:v_dot2_bf16_bf16 v2, s0, 0x10001, v2
+; GFX11-NEXT:v_do
@@ -4181,13 +4181,20 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand
&MO,
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
return AMDGPU::isInlinableLiteralV2I16(Imm);
+ case AMDGPU::OPERAND_REG_IMM_V2BF16:
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/80908
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@@ -79,17 +79,17 @@ define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT:v_mov_b32_e32 v2, s1
; GFX11-NEXT:s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:v_dot2_bf16_bf16 v2, s0, 0x10001, v2
+; GFX11-NEXT:v_do
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s
rampitec wrote:
You also need a disasm test for this.
https://github.com/llvm/llvm-project/pull/80908
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@@ -1,8 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s |
FileCheck %s --check-prefixes=GFX11,SDAG-GFX11
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-mach
@@ -488,6 +488,49 @@ static bool printImmediateFloat16(uint32_t Imm, const
MCSubtargetInfo &STI,
return true;
}
+static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ if (Imm == 0x3F80)
+O <
@@ -4185,9 +4185,17 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand
&MO,
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
return AMDGPU::isInlinableLiteralV2F16(Imm);
+ case AMDGPU::OPERAND_REG_IMM_V2BF16:
+ case AMDGPU:
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
rampitec wrote:
clang/test/CodeGenOp
@@ -4185,9 +4185,17 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand
&MO,
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
return AMDGPU::isInlinableLiteralV2F16(Imm);
+ case AMDGPU::OPERAND_REG_IMM_V2BF16:
+ case AMDGPU:
https://github.com/rampitec approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/84248
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@@ -1122,7 +1122,7 @@ class S_SETREG_B32_Pseudo pattern=[]> :
SOPK_Pseudo <
pattern>;
def S_SETREG_B32 : S_SETREG_B32_Pseudo <
- [(int_amdgcn_s_setreg (i32 SIMM16bit:$simm16), i32:$sdst)]> {
+ [(int_amdgcn_s_setreg (i32 timm:$simm16), i32:$sdst)]> {
ramp
@@ -1122,7 +1122,7 @@ class S_SETREG_B32_Pseudo pattern=[]> :
SOPK_Pseudo <
pattern>;
def S_SETREG_B32 : S_SETREG_B32_Pseudo <
- [(int_amdgcn_s_setreg (i32 SIMM16bit:$simm16), i32:$sdst)]> {
+ [(int_amdgcn_s_setreg (i32 timm:$simm16), i32:$sdst)]> {
ramp
@@ -1122,7 +1122,7 @@ class S_SETREG_B32_Pseudo pattern=[]> :
SOPK_Pseudo <
pattern>;
def S_SETREG_B32 : S_SETREG_B32_Pseudo <
- [(int_amdgcn_s_setreg (i32 SIMM16bit:$simm16), i32:$sdst)]> {
+ [(int_amdgcn_s_setreg (i32 timm:$simm16), i32:$sdst)]> {
ramp
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/80503
>From b07f5866aa8acf881fbdb15450ecda4dfc8a68e8 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri, 2 Feb 2024 14:28:00 -0800
Subject: [PATCH 1/2] [AMDGPU] Fixed byte_sel of v_cvt_f32_bf8/v_cvt_f32_fp
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/80503
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@@ -832,6 +832,13 @@ void test_atomic_inc_dec(local uint *lptr, global uint
*gptr, uint val) {
res = __builtin_amdgcn_atomic_dec32((volatile global uint*)gptr, val,
__ATOMIC_SEQ_CST, "");
}
+// CHECK-LABEL test_wavefrontsize(
+unsigned test_wavefrontsize() {
--
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/80741
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/80741
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@@ -832,6 +832,13 @@ void test_atomic_inc_dec(local uint *lptr, global uint
*gptr, uint val) {
res = __builtin_amdgcn_atomic_dec32((volatile global uint*)gptr, val,
__ATOMIC_SEQ_CST, "");
}
+// CHECK-LABEL test_wavefrontsize(
+unsigned test_wavefrontsize() {
--
https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/79218
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rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/74537
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