@@ -83,6 +83,84 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
@@ -83,6 +83,84 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/146302
Co-authored-by: Shilei Tian
>From ed3e22a2edc87f68c19ed8b27527ee09dda795cf Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Sun, 29 Jun 2025 22:58:17 -0400
Subject: [PATCH] [AMDGPU] Add support f
shiltian wrote:
* **#146302** https://app.graphite.dev/github/pr/llvm/llvm-project/146302?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146
shiltian wrote:
### Merge activity
* **Jun 30, 11:47 AM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/146302).
https://github.com/llvm/llvm-project/pull/146302
__
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/146302
>From 1be2863da610906403bf436d33a3114a13f40daa Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_fp8` on gfx1250
Co-authored-
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/146305
>From 51e5e4593f24771ee818e273f76092a05e2fb98a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:02 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250
Co-authored-
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/146305
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shiltian wrote:
> > Co-authored-by: Shilei Tian [i...@tianshilei.me](mailto:i...@tianshilei.me)
>
> Co authored by yourself?
Yes, because if you check the commit, the author is @rampitec.
https://github.com/llvm/llvm-project/pull/146302
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https://github.com/llvm/llvm-project/pull/146302
>From befea46e97c499f3b1ad0e3ac17ecadebc74acc1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_fp8` on gfx1250
Co-authored-
shiltian wrote:
Oh indeed! I didn't notice that…
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@@ -1214,6 +1214,12 @@ void __kmp_serialized_parallel(ident_t *loc, kmp_int32
global_tid) {
// Reset for next parallel region
this_thr->th.th_set_proc_bind = proc_bind_default;
+ // OpenMP 6.0 12.1.2 requires the num_threads 'strict' modifier to also have
+ // effect wh
shiltian wrote:
Please split the PR into three: front end, device runtime, and libomp for
faster and better review.
https://github.com/llvm/llvm-project/pull/146346
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@@ -1214,6 +1214,12 @@ void __kmp_serialized_parallel(ident_t *loc, kmp_int32
global_tid) {
// Reset for next parallel region
this_thr->th.th_set_proc_bind = proc_bind_default;
+ // OpenMP 6.0 12.1.2 requires the num_threads 'strict' modifier to also have
+ // effect wh
@@ -1214,6 +1214,12 @@ void __kmp_serialized_parallel(ident_t *loc, kmp_int32
global_tid) {
// Reset for next parallel region
this_thr->th.th_set_proc_bind = proc_bind_default;
+ // OpenMP 6.0 12.1.2 requires the num_threads 'strict' modifier to also have
+ // effect wh
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146382
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>From 8b078d8346b7c9e949700d7e5c2a4ec9e29a2138 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_fp8` on gfx1250
Co-authored-
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/147425
>From 2c36f0664993d54841245fe62d062af3b7332c97 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 14 Jul 2025 12:56:54 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250
Co-authored-by
@@ -704,12 +704,12 @@ void diagnoseUnknownMMRAASName(const MachineInstr &MI,
StringRef AS) {
DiagnosticInfoUnsupported(Fn, Str.str(), MI.getDebugLoc(), DS_Warning));
}
-/// Reads \p MI's MMRAs to parse the "amdgpu-as" MMRA.
+/// Reads \p MI's MMRAs to parse the "amdgpu-
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146220
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146289
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shiltian wrote:
### Merge activity
* **Jul 17, 12:41 PM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149229).
https://github.com/llvm/llvm-project/pull/149229
__
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149339
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@@ -610,7 +610,7 @@ void StmtPrinter::VisitObjCAtTryStmt(ObjCAtTryStmt *Node) {
}
}
- if (auto *FS = static_cast(Node->getFinallyStmt())) {
+ if (auto *FS = Node->getFinallyStmt()) {
shiltian wrote:
If there is no cast, then we'd want to use the type
https://github.com/shiltian approved this pull request.
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shiltian wrote:
but we do have `v_cos_bf16` in `llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s`?
https://github.com/llvm/llvm-project/pull/149355
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shiltian wrote:
* **#149355** https://app.graphite.dev/github/pr/llvm/llvm-project/149355?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/149
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149355
Co-authored-by: Mekhanoshin, Stanislav
>From a6b7ccf491c4d88b18bfdba0dbf839030df189ec Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149355
>From 29b54575b3e64372750466dfafab971697f402f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16_e64` on gfx1250
Co-authored
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149229
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https://github.com/llvm/llvm-project/pull/149241
>From 8012a2d62f910c81a38c1c8d1de1a5bbd797d22f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 23:48:48 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16` on gfx1250
Co-authored-by:
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149241
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@@ -2,51 +2,41 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileCheck
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146944
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146987
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@@ -85,7 +85,7 @@ __amdgpu_buffer_rsrc_t
test_amdgcn_make_buffer_p0_nullptr(short stride, int num,
// CHECK-LABEL: @test_amdgcn_make_buffer_p1_nullptr(
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call ptr addrspace(8)
@llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr
@@ -13658,6 +13658,7 @@ bool SITargetLowering::isCanonicalized(Register Reg,
const MachineFunction &MF,
case Intrinsic::amdgcn_frexp_mant:
case Intrinsic::amdgcn_fdot2:
case Intrinsic::amdgcn_trig_preop:
+case Intrinsic::amdgcn_tanh:
shiltian w
@@ -13658,6 +13658,7 @@ bool SITargetLowering::isCanonicalized(Register Reg,
const MachineFunction &MF,
case Intrinsic::amdgcn_frexp_mant:
case Intrinsic::amdgcn_fdot2:
case Intrinsic::amdgcn_trig_preop:
+case Intrinsic::amdgcn_tanh:
shiltian w
shiltian wrote:
For some reason there is a crash in
`llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll`.
```
LLVM ERROR: Cannot select: t28: ch = store<(store (s16) into %ir.out.load,
addrspace 1)> t0, t27, t30, undef:i64
t27: i16 = bitcast t21
t21: bf16 = llvm.amdgcn.tanh TargetConstant:i64<
@@ -2,51 +2,41 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileCheck
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/147558
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shiltian wrote:
This PR is messed up at this moment.
https://github.com/llvm/llvm-project/pull/147425
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@@ -266,7 +266,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple
&Triple,
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
CUMode = !(GPUFeatures & llvm::AMDGPU::FEATURE_WGP);
- for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"})
+ for (auto F : {
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/147425
>From f75f85e997f95bd29e244e199d16c89dffca1232 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 14 Jul 2025 12:56:54 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250
Co-authored-by
@@ -2,169 +2,69 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileChec
shiltian wrote:
FWIW, the crash still exists.
https://github.com/llvm/llvm-project/pull/147425
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https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/148916
Co-authored-by: Mekhanoshin, Stanislav
>From b0c51e4f67e0740d916d1596ced8f93228d93b1c Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 15 Jul 2025 14:10:18 -0400
Subject: [PATCH] [AMDGPU] Add support for
shiltian wrote:
* **#148916** https://app.graphite.dev/github/pr/llvm/llvm-project/148916?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/148
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/148871
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https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149194
Co-authored-by: Mekhanoshin, Stanislav
>From 296077854b4bcad36f9b924da1dbfe4376d8b4d5 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 17:31:42 -0400
Subject: [PATCH] [AMDGPU] Add support for
shiltian wrote:
* **#149194** https://app.graphite.dev/github/pr/llvm/llvm-project/149194?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/149
@@ -252,6 +252,15 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fmax_f64,
"dd*0d", "t", "gfx90a-inst
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_f64, "dd*3d", "t",
"gfx90a-insts")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_f32, "ff*3f", "t", "gfx8-insts")
+TARGET_BUI
@@ -25,4 +25,27 @@ define amdgpu_ps void @llvm_log2_bf16_s(ptr addrspace(1)
%out, bfloat inreg %src
ret void
}
+define amdgpu_ps void @llvm_exp2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
+; GCN-LABEL: llvm_exp2_bf16_v:
+; GCN: ; %bb.0:
+; GCN-NEXT:v_exp_bf16_e3
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shiltian wrote:
### Merge activity
* **Jul 17, 6:41 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149355).
https://github.com/llvm/llvm-project/pull/149355
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https://github.com/shiltian closed
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149360
>From 10b9379f759506e4e1e3c1cab1191ed386609ebe Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 13:03:14 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_f32` on gfx1250
Co-authored-by:
@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149450
>From e35cd5506ed733fcb62eab4c28ab4e9f5966216f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 00:26:15 -0400
Subject: [PATCH 1/2] [AMDGPU] Add support for `v_prng_b32` on gfx1250
Co-authored
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 345d4d9de11d21c1b087cdf88de22f0d90a7ba9f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149450
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shiltian wrote:
### Merge activity
* **Jul 18, 2:58 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149450).
https://github.com/llvm/llvm-project/pull/149450
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shiltian wrote:
Oh nice catch. Thanks.
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https://github.com/llvm/llvm-project/pull/149518
>From 33991acfd14b041071d112de032afe94c6bedf35 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
shiltian wrote:
### Merge activity
* **Jul 18, 4:46 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149518).
https://github.com/llvm/llvm-project/pull/149518
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 4d850d602b45130ae958776cd353512116bd5862 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 1d045407b88bc8efae91410223e8ba980cdec6d1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 8f89191a1714b2e891eda67d844d32be2ccfc27a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From e6d5fd17af108d454e43a6489eb7580bf007a170 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From f7c11e672cebd2488582ee89e66d9777182db1e1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From d58f9605434bfc4de1820f7c6beabd82586a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149528
>From 3fb65bcda47f66a47c8295e04102a3a1d675dbd7 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:36:56 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sat_pk4_i4_[i8,u8]` on gfx1250
Co-au
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149528
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149518
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149528
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@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
shiltian wrote:
### Merge activity
* **Jul 18, 12:42 PM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149447).
https://github.com/llvm/llvm-project/pull/149447
__
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149447
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https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149450
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149450
>From e35cd5506ed733fcb62eab4c28ab4e9f5966216f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 00:26:15 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_prng_b32` on gfx1250
Co-authored-by:
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149684
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