[clang] [llvm] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250 (PR #147425)

[Shilei Tian via cfe-commits]

https://github.com/shiltian updated 
https://github.com/llvm/llvm-project/pull/147425

>From f75f85e997f95bd29e244e199d16c89dffca1232 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i...@tianshilei.me>
Date: Mon, 14 Jul 2025 12:56:54 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250

Co-authored-by: Mekhanoshin, Stanislav <stanislav.mekhanos...@amd.com>
---
 clang/include/clang/Basic/BuiltinsAMDGPU.def  |  2 +
 clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp   |  3 +
 clang/test/CodeGenOpenCL/amdgpu-features.cl   |  2 +-
 .../CodeGenOpenCL/builtins-amdgcn-gfx1250.cl  | 19 ++++
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td      |  4 +
 llvm/lib/Target/AMDGPU/AMDGPU.td              | 10 ++
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp |  6 +-
 .../AMDGPU/AMDGPUInstCombineIntrinsic.cpp     |  3 +-
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |  1 +
 llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h      |  3 +
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     |  1 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.td         |  1 +
 llvm/lib/Target/AMDGPU/VOP1Instructions.td    |  5 +
 llvm/lib/TargetParser/TargetParser.cpp        |  1 +
 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll  | 94 +++++++++++++++++++
 llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s | 48 ++++++++++
 llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s        | 51 ++++++++++
 .../MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s | 56 +++++++++++
 llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s  | 60 ++++++++++++
 .../MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s  | 12 +++
 llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s   | 16 ++++
 .../gfx1250_asm_vop3_from_vop1-fake16.s       | 45 +++++++++
 .../MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s    | 48 ++++++++++
 .../gfx1250_asm_vop3_from_vop1_dpp16-fake16.s | 56 +++++++++++
 .../AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s | 60 ++++++++++++
 .../gfx1250_asm_vop3_from_vop1_dpp8-fake16.s  | 16 ++++
 .../AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s  | 20 ++++
 .../Disassembler/AMDGPU/gfx1250_dasm_vop1.txt | 63 +++++++++++++
 .../AMDGPU/gfx1250_dasm_vop1_dpp16.txt        | 59 ++++++++++++
 .../AMDGPU/gfx1250_dasm_vop1_dpp8.txt         | 16 ++++
 .../AMDGPU/gfx1250_dasm_vop3_from_vop1.txt    | 64 +++++++++++++
 .../gfx1250_dasm_vop3_from_vop1_dpp16.txt     | 60 ++++++++++++
 .../gfx1250_dasm_vop3_from_vop1_dpp8.txt      | 20 ++++
 33 files changed, 921 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll

diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 4d371a9f7d6db..ab432b7a8ad58 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -668,6 +668,8 @@ TARGET_BUILTIN(__builtin_amdgcn_s_monitor_sleep,  "vIs", 
"n", "gfx1250-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_wait_asynccnt, "vIUs", "n", "gfx1250-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_wait_tensorcnt, "vIUs", "n", "gfx1250-insts")
 
+TARGET_BUILTIN(__builtin_amdgcn_tanh_bf16, "yy", "nc", "bf16-trans-insts")
+
 TARGET_BUILTIN(__builtin_amdgcn_cvt_f16_fp8, "hiIi", "nc", "gfx1250-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_f16_bf8, "hiIi", "nc", "gfx1250-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_f16_fp8, "V2hs", "nc", "gfx1250-insts")
diff --git a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp 
b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
index f09b3b92c4ea0..bd44874eac470 100644
--- a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
@@ -497,6 +497,9 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned 
BuiltinID,
     Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_ballot, { ResultType });
     return Builder.CreateCall(F, { Src });
   }
+  case AMDGPU::BI__builtin_amdgcn_tanh_bf16:
+    return emitBuiltinWithOneOverloadedType<1>(*this, E,
+                                               Intrinsic::amdgcn_tanh);
   case AMDGPU::BI__builtin_amdgcn_uicmp:
   case AMDGPU::BI__builtin_amdgcn_uicmpl:
   case AMDGPU::BI__builtin_amdgcn_sicmp:
diff --git a/clang/test/CodeGenOpenCL/amdgpu-features.cl 
b/clang/test/CodeGenOpenCL/amdgpu-features.cl
index 77d2414230cf2..42768ac8def1f 100644
--- a/clang/test/CodeGenOpenCL/amdgpu-features.cl
+++ b/clang/test/CodeGenOpenCL/amdgpu-features.cl
@@ -108,7 +108,7 @@
 // GFX1153: 
"target-features"="+16-bit-insts,+atomic-fadd-rtn-insts,+ci-insts,+dl-insts,+dot10-insts,+dot12-insts,+dot5-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32"
 // GFX1200: 
"target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot10-insts,+dot11-insts,+dot12-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+fp8-conversion-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32"
 // GFX1201: 
"target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot10-insts,+dot11-insts,+dot12-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+fp8-conversion-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32"
-// GFX1250: 
"target-features"="+16-bit-insts,+ashr-pk-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+bitop3-insts,+ci-insts,+dl-insts,+dot7-insts,+dot8-insts,+dpp,+fp8-conversion-insts,+fp8e5m3-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx1250-insts,+gfx8-insts,+gfx9-insts,+permlane16-swap,+prng-inst,+setprio-inc-wg-inst,+transpose-load-f4f6-insts,+wavefrontsize32"
+// GFX1250: 
"target-features"="+16-bit-insts,+ashr-pk-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+bf16-trans-insts,+bitop3-insts,+ci-insts,+dl-insts,+dot7-insts,+dot8-insts,+dpp,+fp8-conversion-insts,+fp8e5m3-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx1250-insts,+gfx8-insts,+gfx9-insts,+permlane16-swap,+prng-inst,+setprio-inc-wg-inst,+transpose-load-f4f6-insts,+wavefrontsize32"
 
 // GFX1103-W64: 
"target-features"="+16-bit-insts,+atomic-fadd-rtn-insts,+ci-insts,+dl-insts,+dot10-insts,+dot12-insts,+dot5-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize64"
 
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
index a1b91d0cc38dc..830ceabb1cb29 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
@@ -42,6 +42,25 @@ void test_s_wait_tensorcnt() {
   __builtin_amdgcn_s_wait_tensorcnt(0);
 }
 
+// CHECK-LABEL: @test_tanh_bf16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[OUT_ADDR:%.*]] = alloca ptr addrspace(1), align 8, 
addrspace(5)
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca bfloat, align 2, addrspace(5)
+// CHECK-NEXT:    [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[OUT_ADDR]] to ptr
+// CHECK-NEXT:    [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[A_ADDR]] to ptr
+// CHECK-NEXT:    store ptr addrspace(1) [[OUT:%.*]], ptr [[OUT_ADDR_ASCAST]], 
align 8
+// CHECK-NEXT:    store bfloat [[A:%.*]], ptr [[A_ADDR_ASCAST]], align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = load bfloat, ptr [[A_ADDR_ASCAST]], align 2
+// CHECK-NEXT:    [[TMP1:%.*]] = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 
[[TMP0]])
+// CHECK-NEXT:    [[TMP2:%.*]] = load ptr addrspace(1), ptr 
[[OUT_ADDR_ASCAST]], align 8
+// CHECK-NEXT:    store bfloat [[TMP1]], ptr addrspace(1) [[TMP2]], align 2
+// CHECK-NEXT:    ret void
+//
+void test_tanh_bf16(global __bf16* out, __bf16 a)
+{
+  *out = __builtin_amdgcn_tanh_bf16(a);
+}
+
 // CHECK-LABEL: @test_cvt_f16_fp8(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[OUT_ADDR:%.*]] = alloca ptr addrspace(1), align 8, 
addrspace(5)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 8016757cf0f3c..962693003349e 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -588,6 +588,10 @@ def int_amdgcn_ds_ordered_swap : AMDGPUDSOrderedIntrinsic;
 def int_amdgcn_ds_append : AMDGPUDSAppendConsumedIntrinsic;
 def int_amdgcn_ds_consume : AMDGPUDSAppendConsumedIntrinsic;
 
+def int_amdgcn_tanh : DefaultAttrsIntrinsic<
+  [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
+>;
+
 def int_amdgcn_cvt_pk_f16_fp8 : DefaultAttrsIntrinsic<
   [llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrSpeculatable]
 >, ClangBuiltin<"__builtin_amdgcn_cvt_pk_f16_fp8">;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 31420caca0899..04ec1716478e4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -541,6 +541,12 @@ def FeatureRealTrue16Insts : 
SubtargetFeature<"real-true16",
   "Use true 16-bit registers"
 >;
 
+def FeatureBF16TransInsts : SubtargetFeature<"bf16-trans-insts",
+  "HasBF16TransInsts",
+  "true",
+  "Has bf16 transcendental instructions"
+>;
+
 def FeatureBF16ConversionInsts : SubtargetFeature<"bf16-cvt-insts",
   "HasBF16ConversionInsts",
   "true",
@@ -1967,6 +1973,7 @@ def FeatureISAVersion12_50 : FeatureSet<
    FeatureDPPSrc1SGPR,
    FeatureBitOp3Insts,
    FeatureTransposeLoadF4F6Insts,
+   FeatureBF16TransInsts,
    FeatureBF16ConversionInsts,
    FeatureCvtPkF16F32Inst,
    FeatureMinimum3Maximum3PKF16,
@@ -2442,6 +2449,9 @@ def UseFakeTrue16Insts : 
True16PredicateClass<"Subtarget->hasTrue16BitInsts() &&
   // FIXME When we default to RealTrue16 instead of Fake, change the line as 
follows.
   // AssemblerPredicate<(all_of FeatureTrue16BitInsts, (not 
FeatureRealTrue16Insts))>;
 
+def HasBF16TransInsts : Predicate<"Subtarget->hasBF16TransInsts()">,
+  AssemblerPredicate<(all_of FeatureBF16TransInsts)>;
+
 def HasBF16ConversionInsts : Predicate<"Subtarget->hasBF16ConversionInsts()">,
   AssemblerPredicate<(all_of FeatureBF16ConversionInsts)>;
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index e64d2162441ab..3414fe758eff8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4006,7 +4006,8 @@ SDValue 
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
   case Intrinsic::amdgcn_rsq:
   case Intrinsic::amdgcn_rcp_legacy:
   case Intrinsic::amdgcn_rsq_legacy:
-  case Intrinsic::amdgcn_rsq_clamp: {
+  case Intrinsic::amdgcn_rsq_clamp:
+  case Intrinsic::amdgcn_tanh: {
     // FIXME: This is probably wrong. If src is an sNaN, it won't be quieted
     SDValue Src = N->getOperand(1);
     return Src.isUndef() ? Src : SDValue();
@@ -6196,7 +6197,8 @@ bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(
     case Intrinsic::amdgcn_rsq:
     case Intrinsic::amdgcn_rcp_legacy:
     case Intrinsic::amdgcn_rsq_legacy:
-    case Intrinsic::amdgcn_rsq_clamp: {
+    case Intrinsic::amdgcn_rsq_clamp:
+    case Intrinsic::amdgcn_tanh: {
       if (SNaN)
         return true;
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index b8996fb97f1cb..e2c2e8912c715 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -700,7 +700,8 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, 
IntrinsicInst &II) const {
     break;
   }
   case Intrinsic::amdgcn_sqrt:
-  case Intrinsic::amdgcn_rsq: {
+  case Intrinsic::amdgcn_rsq:
+  case Intrinsic::amdgcn_tanh: {
     Value *Src = II.getArgOperand(0);
     if (isa<PoisonValue>(Src))
       return IC.replaceInstUsesWith(II, Src);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 1483d97d23fcc..965053ffe8624 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4546,6 +4546,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const 
MachineInstr &MI) const {
     case Intrinsic::amdgcn_rcp_legacy:
     case Intrinsic::amdgcn_rsq_legacy:
     case Intrinsic::amdgcn_rsq_clamp:
+    case Intrinsic::amdgcn_tanh:
     case Intrinsic::amdgcn_fmul_legacy:
     case Intrinsic::amdgcn_fma_legacy:
     case Intrinsic::amdgcn_frexp_mant:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h 
b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 7c24f428d78e4..1e44be8e47201 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -59,6 +59,7 @@ class AMDGPUSubtarget {
   bool HasCvtPkF16F32Inst = false;
   bool HasF32ToF16BF16ConversionSRInsts = false;
   bool EnableRealTrue16Insts = false;
+  bool HasBF16TransInsts = false;
   bool HasBF16ConversionInsts = false;
   bool HasMadMixInsts = false;
   bool HasMadMacF32Insts = false;
@@ -202,6 +203,8 @@ class AMDGPUSubtarget {
   // supported and the support for fake True16 instructions is removed.
   bool useRealTrue16Insts() const;
 
+  bool hasBF16TransInsts() const { return HasBF16TransInsts; }
+
   bool hasBF16ConversionInsts() const {
     return HasBF16ConversionInsts;
   }
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e90316cee12fe..93fd767943679 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -13660,6 +13660,7 @@ bool SITargetLowering::isCanonicalized(Register Reg, 
const MachineFunction &MF,
     case Intrinsic::amdgcn_frexp_mant:
     case Intrinsic::amdgcn_fdot2:
     case Intrinsic::amdgcn_trig_preop:
+    case Intrinsic::amdgcn_tanh:
       return true;
     default:
       break;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td 
b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 5e41f875d980a..e5ce0a9d0e971 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2837,6 +2837,7 @@ def VOP_F16_F16 : VOPProfile<[f16, f16, untyped, 
untyped]>;
 def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
 def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
 def VOP_I16_I16 : VOPProfile <[i16, i16, untyped, untyped]>;
+def VOP_BF16_BF16 : VOPProfile<[bf16, bf16, untyped, untyped]>;
 
 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td 
b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 211112e5262a3..57857c688283d 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -526,6 +526,10 @@ defm V_LOG_F16 : VOP1Inst_t16 <"v_log_f16", VOP_F16_F16, 
AMDGPUlogf16>;
 defm V_EXP_F16 : VOP1Inst_t16 <"v_exp_f16", VOP_F16_F16, AMDGPUexpf16>;
 defm V_SIN_F16 : VOP1Inst_t16 <"v_sin_f16", VOP_F16_F16, AMDGPUsin>;
 defm V_COS_F16 : VOP1Inst_t16 <"v_cos_f16", VOP_F16_F16, AMDGPUcos>;
+
+let SubtargetPredicate = HasBF16TransInsts in {
+defm V_TANH_BF16 : VOP1Inst_t16 <"v_tanh_bf16", VOP_BF16_BF16, 
int_amdgcn_tanh>;
+}
 } // End TRANS = 1, SchedRW = [WriteTrans32]
 defm V_FREXP_MANT_F16 : VOP1Inst_t16 <"v_frexp_mant_f16", VOP_F16_F16, 
int_amdgcn_frexp_mant>;
 defm V_FREXP_EXP_I16_F16 : VOP1Inst_t16_with_profiles <"v_frexp_exp_i16_f16",
@@ -1127,6 +1131,7 @@ defm V_CVT_F32_F16           : 
VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x00b>;
 
 defm V_MOV_B64 : VOP1_Real_FULL <GFX1250Gen, 0x1d>;
 
+defm V_TANH_BF16             : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x04a>;
 defm V_CVT_F32_BF16          : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x072, 
"v_cvt_f32_bf16", "V_CVT_F32_BF16_gfx1250">;
 defm V_CVT_PK_F16_FP8        : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x075>;
 defm V_CVT_PK_F16_BF8        : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x076>;
diff --git a/llvm/lib/TargetParser/TargetParser.cpp 
b/llvm/lib/TargetParser/TargetParser.cpp
index 31123c5eb7ab7..d7e206ef8cd4f 100644
--- a/llvm/lib/TargetParser/TargetParser.cpp
+++ b/llvm/lib/TargetParser/TargetParser.cpp
@@ -444,6 +444,7 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const 
Triple &T,
       Features["bitop3-insts"] = true;
       Features["prng-inst"] = true;
       Features["transpose-load-f4f6-insts"] = true;
+      Features["bf16-trans-insts"] = true;
       Features["fp8-conversion-insts"] = true;
       Features["fp8e5m3-insts"] = true;
       Features["permlane16-swap"] = true;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll 
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
new file mode 100644
index 0000000000000..5349b1dc31bd5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 
-mattr=+real-true16 %s -o - | FileCheck -check-prefix=SDAG-REAL16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 
-mattr=-real-true16 %s -o - | FileCheck -check-prefix=SDAG-FAKE16 %s
+; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 
-mattr=+real-true16 %s -o - | FileCheck -check-prefix=GISEL-REAL16 %s
+; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 
-mattr=-real-true16 %s -o - | FileCheck -check-prefix=GISEL-FAKE16 %s
+
+; FIXME: GlobalISel does not work with bf16
+
+declare bfloat @llvm.amdgcn.tanh.bf16(bfloat) #0
+
+define amdgpu_kernel void @tanh_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
+; SDAG-REAL16-LABEL: tanh_bf16:
+; SDAG-REAL16:       ; %bb.0:
+; SDAG-REAL16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, s2
+; SDAG-REAL16-NEXT:    flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT:    s_endpgm
+;
+; SDAG-FAKE16-LABEL: tanh_bf16:
+; SDAG-FAKE16:       ; %bb.0:
+; SDAG-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, s2
+; SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; SDAG-FAKE16-NEXT:    s_endpgm
+  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat %src) #0
+  store bfloat %tanh, ptr addrspace(1) %out, align 2
+  ret void
+}
+
+define amdgpu_kernel void @tanh_bf16_constant_4(ptr addrspace(1) %out) #1 {
+; SDAG-REAL16-LABEL: tanh_bf16_constant_4:
+; SDAG-REAL16:       ; %bb.0:
+; SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, 4.0
+; SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT:    flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT:    s_endpgm
+;
+; SDAG-FAKE16-LABEL: tanh_bf16_constant_4:
+; SDAG-FAKE16:       ; %bb.0:
+; SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, 4.0
+; SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; SDAG-FAKE16-NEXT:    s_endpgm
+  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 4.0) #0
+  store bfloat %tanh, ptr addrspace(1) %out, align 2
+  ret void
+}
+
+define amdgpu_kernel void @tanh_bf16_constant_100(ptr addrspace(1) %out) #1 {
+; SDAG-REAL16-LABEL: tanh_bf16_constant_100:
+; SDAG-REAL16:       ; %bb.0:
+; SDAG-REAL16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-REAL16-NEXT:    v_tanh_bf16_e32 v0.l, 0x42c8
+; SDAG-REAL16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-REAL16-NEXT:    s_wait_kmcnt 0x0
+; SDAG-REAL16-NEXT:    flat_store_b16 v1, v0, s[0:1]
+; SDAG-REAL16-NEXT:    s_endpgm
+;
+; SDAG-FAKE16-LABEL: tanh_bf16_constant_100:
+; SDAG-FAKE16:       ; %bb.0:
+; SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; SDAG-FAKE16-NEXT:    v_tanh_bf16_e32 v0, 0x42c8
+; SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; SDAG-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; SDAG-FAKE16-NEXT:    s_endpgm
+  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 100.0) #0
+  store bfloat %tanh, ptr addrspace(1) %out, align 2
+  ret void
+}
+
+define amdgpu_kernel void @tanh_undef_bf16(ptr addrspace(1) %out) #1 {
+; SDAG-REAL16-LABEL: tanh_undef_bf16:
+; SDAG-REAL16:       ; %bb.0:
+; SDAG-REAL16-NEXT:    s_endpgm
+;
+; SDAG-FAKE16-LABEL: tanh_undef_bf16:
+; SDAG-FAKE16:       ; %bb.0:
+; SDAG-FAKE16-NEXT:    s_endpgm
+  %tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat undef)
+  store bfloat %tanh, ptr addrspace(1) %out, align 2
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
index 63a13062069de..cf8ad0e8b7b65 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
@@ -25,6 +25,54 @@ v_mov_b64 v[4:5], -1
 v_mov_b64 v[4:5], 0.5
 // GFX1250: v_mov_b64_e32 v[4:5], 0.5               ; encoding: 
[0xf0,0x3a,0x08,0x7e]
 
+v_mov_b64 v[254:255], 0xaf123456
+// GFX1250: v_mov_b64_e32 v[254:255], lit64(0xaf123456) ; encoding: 
[0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00]
+
+v_tanh_bf16 v5, v1
+// GFX1250: v_tanh_bf16_e32 v5, v1                  ; encoding: 
[0x01,0x95,0x0a,0x7e]
+
+v_tanh_bf16 v5, v127
+// GFX1250: v_tanh_bf16_e32 v5, v127                ; encoding: 
[0x7f,0x95,0x0a,0x7e]
+
+v_tanh_bf16 v5, s1
+// GFX1250: v_tanh_bf16_e32 v5, s1                  ; encoding: 
[0x01,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, s105
+// GFX1250: v_tanh_bf16_e32 v5, s105                ; encoding: 
[0x69,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, vcc_lo
+// GFX1250: v_tanh_bf16_e32 v5, vcc_lo              ; encoding: 
[0x6a,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, vcc_hi
+// GFX1250: v_tanh_bf16_e32 v5, vcc_hi              ; encoding: 
[0x6b,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, ttmp15
+// GFX1250: v_tanh_bf16_e32 v5, ttmp15              ; encoding: 
[0x7b,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, m0
+// GFX1250: v_tanh_bf16_e32 v5, m0                  ; encoding: 
[0x7d,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, exec_lo
+// GFX1250: v_tanh_bf16_e32 v5, exec_lo             ; encoding: 
[0x7e,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, exec_hi
+// GFX1250: v_tanh_bf16_e32 v5, exec_hi             ; encoding: 
[0x7f,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, null
+// GFX1250: v_tanh_bf16_e32 v5, null                ; encoding: 
[0x7c,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, -1
+// GFX1250: v_tanh_bf16_e32 v5, -1                  ; encoding: 
[0xc1,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, 0.5
+// GFX1250: v_tanh_bf16_e32 v5, 0.5                 ; encoding: 
[0xf0,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, src_scc
+// GFX1250: v_tanh_bf16_e32 v5, src_scc             ; encoding: 
[0xfd,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v127, 0x8000
+// GFX1250: v_tanh_bf16_e32 v127, 0x8000            ; encoding: 
[0xff,0x94,0xfe,0x7e,0x00,0x80,0x00,0x00]
+
 v_cvt_f32_bf16 v5, v1
 // GFX1250: v_cvt_f32_bf16_e32 v5, v1               ; encoding: 
[0x01,0xe5,0x0a,0x7e]
 
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
index b0a879a6cd726..055f540fc2203 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
@@ -25,6 +25,57 @@ v_mov_b64 v[4:5], -1
 v_mov_b64 v[4:5], 0.5
 // GFX1250: v_mov_b64_e32 v[4:5], 0.5               ; encoding: 
[0xf0,0x3a,0x08,0x7e]
 
+v_mov_b64 v[254:255], 0xaf123456
+// GFX1250: v_mov_b64_e32 v[254:255], lit64(0xaf123456) ; encoding: 
[0xfe,0x3a,0xfc,0x7f,0x56,0x34,0x12,0xaf,0x00,0x00,0x00,0x00]
+
+v_tanh_bf16 v5, v1
+// GFX1250: v_tanh_bf16_e32 v5, v1                  ; encoding: 
[0x01,0x95,0x0a,0x7e]
+
+v_tanh_bf16 v5, v127
+// GFX1250: v_tanh_bf16_e32 v5, v127                ; encoding: 
[0x7f,0x95,0x0a,0x7e]
+
+v_tanh_bf16 v5, s1
+// GFX1250: v_tanh_bf16_e32 v5, s1                  ; encoding: 
[0x01,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, s105
+// GFX1250: v_tanh_bf16_e32 v5, s105                ; encoding: 
[0x69,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, vcc_lo
+// GFX1250: v_tanh_bf16_e32 v5, vcc_lo              ; encoding: 
[0x6a,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, vcc_hi
+// GFX1250: v_tanh_bf16_e32 v5, vcc_hi              ; encoding: 
[0x6b,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, ttmp15
+// GFX1250: v_tanh_bf16_e32 v5, ttmp15              ; encoding: 
[0x7b,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, m0
+// GFX1250: v_tanh_bf16_e32 v5, m0                  ; encoding: 
[0x7d,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, exec_lo
+// GFX1250: v_tanh_bf16_e32 v5, exec_lo             ; encoding: 
[0x7e,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, exec_hi
+// GFX1250: v_tanh_bf16_e32 v5, exec_hi             ; encoding: 
[0x7f,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, null
+// GFX1250: v_tanh_bf16_e32 v5, null                ; encoding: 
[0x7c,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, -1
+// GFX1250: v_tanh_bf16_e32 v5, -1                  ; encoding: 
[0xc1,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, 0.5
+// GFX1250: v_tanh_bf16_e32 v5, 0.5                 ; encoding: 
[0xf0,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v5, src_scc
+// GFX1250: v_tanh_bf16_e32 v5, src_scc             ; encoding: 
[0xfd,0x94,0x0a,0x7e]
+
+v_tanh_bf16 v127, 0x8000
+// GFX1250: v_tanh_bf16_e32 v127, 0x8000            ; encoding: 
[0xff,0x94,0xfe,0x7e,0x00,0x80,0x00,0x00]
+
+v_tanh_bf16 v5.h, v1.h
+// GFX1250: v_tanh_bf16_e32 v5.h, v1.h              ; encoding: 
[0x81,0x95,0x0a,0x7f]
+
 v_cvt_f32_bf16 v5, v1
 // GFX1250: v_cvt_f32_bf16_e32 v5, v1               ; encoding: 
[0x01,0xe5,0x0a,0x7e]
 
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
index e53812bb3fd04..4e5754f3961c1 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s
@@ -2,6 +2,62 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 
-show-encoding %s | FileCheck --check-prefixes=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16 v5, v1 quad_perm:[3,2,1,0]
+// GFX1250: v_tanh_bf16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 quad_perm:[0,1,2,3]
+// GFX1250: v_tanh_bf16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_mirror
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_half_mirror
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shl:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shl:15
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shr:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shr:15
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_ror:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_ror:15
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x50,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 
bound_ctrl:1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x60,0x09,0x13]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 
fi:1
+// GFX1250: v_tanh_bf16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 
bank_mask:0x0 fi:1 ; encoding: [0xfa,0x94,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16 v5, v1 quad_perm:[3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0xe4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
index bd767d14fab5f..a6787254ae60f 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s
@@ -2,6 +2,66 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 
-show-encoding %s | FileCheck --check-prefixes=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16 v5, v1 quad_perm:[3,2,1,0]
+// GFX1250: v_tanh_bf16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 quad_perm:[0,1,2,3]
+// GFX1250: v_tanh_bf16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_mirror
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_half_mirror
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shl:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shl:15
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shr:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_shr:15
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_ror:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_ror:15
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x50,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; 
encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX1250: v_tanh_bf16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 
bound_ctrl:1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x60,0x09,0x13]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 
fi:1
+// GFX1250: v_tanh_bf16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 
bank_mask:0x0 fi:1 ; encoding: [0xfa,0x94,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5.h, v1.h quad_perm:[3,2,1,0]
+// GFX1250: v_tanh_bf16_dpp v5.h, v1.h quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7f,0x81,0x1b,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16 v5, v1 quad_perm:[3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0xe4,0x0a,0x7e,0x01,0x1b,0x00,0xff]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
index cbc0ebd3edda0..e6c35d5e3b863 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8-fake16.s
@@ -2,6 +2,18 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 
-show-encoding %s | FileCheck --check-prefixes=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0xe9,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: 
[0xea,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX1250: v_tanh_bf16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: 
[0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0xe9,0xe4,0x0a,0x7e,0x01,0x77,0x39,0x05]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
index 8b9980a31daf3..98bd1fd41fa60 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp8.s
@@ -2,6 +2,22 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 
-show-encoding %s | FileCheck --check-prefixes=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0xe9,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX1250: v_tanh_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: 
[0xea,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX1250: v_tanh_bf16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: 
[0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0xe9,0xe4,0x0a,0x7e,0x01,0x77,0x39,0x05]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
index f23557df0d745..7196f407e9038 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
@@ -1,6 +1,51 @@
 // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py 
UTC_ARGS: --version 5
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 
-show-encoding %s | FileCheck --check-prefix=GFX1250 %s
 
+v_tanh_bf16_e64 v5, v1
+// GFX1250: v_tanh_bf16_e64 v5, v1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x01,0x00,0x00]
+
+v_tanh_bf16_e64 v5, v255
+// GFX1250: v_tanh_bf16_e64 v5, v255                ; encoding: 
[0x05,0x00,0xca,0xd5,0xff,0x01,0x00,0x00]
+
+v_tanh_bf16_e64 v5, s1
+// GFX1250: v_tanh_bf16_e64 v5, s1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, s105
+// GFX1250: v_tanh_bf16_e64 v5, s105                ; encoding: 
[0x05,0x00,0xca,0xd5,0x69,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, vcc_lo
+// GFX1250: v_tanh_bf16_e64 v5, vcc_lo              ; encoding: 
[0x05,0x00,0xca,0xd5,0x6a,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, vcc_hi
+// GFX1250: v_tanh_bf16_e64 v5, vcc_hi              ; encoding: 
[0x05,0x00,0xca,0xd5,0x6b,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, ttmp15
+// GFX1250: v_tanh_bf16_e64 v5, ttmp15              ; encoding: 
[0x05,0x00,0xca,0xd5,0x7b,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, m0
+// GFX1250: v_tanh_bf16_e64 v5, m0                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x7d,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, exec_lo
+// GFX1250: v_tanh_bf16_e64 v5, exec_lo             ; encoding: 
[0x05,0x00,0xca,0xd5,0x7e,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, exec_hi
+// GFX1250: v_tanh_bf16_e64 v5, exec_hi             ; encoding: 
[0x05,0x00,0xca,0xd5,0x7f,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, null
+// GFX1250: v_tanh_bf16_e64 v5, null                ; encoding: 
[0x05,0x00,0xca,0xd5,0x7c,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, -1
+// GFX1250: v_tanh_bf16_e64 v5, -1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0xc1,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, 0.5 mul:2
+// GFX1250: v_tanh_bf16_e64 v5, 0.5 mul:2           ; encoding: 
[0x05,0x00,0xca,0xd5,0xf0,0x00,0x00,0x08]
+
+v_tanh_bf16_e64 v5, src_scc mul:4
+// GFX1250: v_tanh_bf16_e64 v5, src_scc mul:4       ; encoding: 
[0x05,0x00,0xca,0xd5,0xfd,0x00,0x00,0x10]
+
+v_tanh_bf16_e64 v255, -|0x8000| clamp div:2
+// GFX1250: v_tanh_bf16_e64 v255, -|0x8000| clamp div:2 ; encoding: 
[0xff,0x81,0xca,0xd5,0xff,0x00,0x00,0x38,0x00,0x80,0x00,0x00]
+
 v_cvt_f32_bf8_e64 v1, s3
 // GFX1250: v_cvt_f32_bf8_e64 v1, s3                ; encoding: 
[0x01,0x00,0xed,0xd5,0x03,0x00,0x00,0x00]
 
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
index 5f2313227c4b2..3ea695f10c559 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
@@ -1,6 +1,54 @@
 // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py 
UTC_ARGS: --version 5
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 
-show-encoding %s | FileCheck --check-prefix=GFX1250 %s
 
+v_tanh_bf16_e64 v5, v1
+// GFX1250: v_tanh_bf16_e64 v5, v1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x01,0x00,0x00]
+
+v_tanh_bf16_e64 v5, v255
+// GFX1250: v_tanh_bf16_e64 v5, v255                ; encoding: 
[0x05,0x00,0xca,0xd5,0xff,0x01,0x00,0x00]
+
+v_tanh_bf16_e64 v5, s1
+// GFX1250: v_tanh_bf16_e64 v5, s1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, s105
+// GFX1250: v_tanh_bf16_e64 v5, s105                ; encoding: 
[0x05,0x00,0xca,0xd5,0x69,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, vcc_lo
+// GFX1250: v_tanh_bf16_e64 v5, vcc_lo              ; encoding: 
[0x05,0x00,0xca,0xd5,0x6a,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, vcc_hi
+// GFX1250: v_tanh_bf16_e64 v5, vcc_hi              ; encoding: 
[0x05,0x00,0xca,0xd5,0x6b,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, ttmp15
+// GFX1250: v_tanh_bf16_e64 v5, ttmp15              ; encoding: 
[0x05,0x00,0xca,0xd5,0x7b,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, m0
+// GFX1250: v_tanh_bf16_e64 v5, m0                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x7d,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, exec_lo
+// GFX1250: v_tanh_bf16_e64 v5, exec_lo             ; encoding: 
[0x05,0x00,0xca,0xd5,0x7e,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, exec_hi
+// GFX1250: v_tanh_bf16_e64 v5, exec_hi             ; encoding: 
[0x05,0x00,0xca,0xd5,0x7f,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, null
+// GFX1250: v_tanh_bf16_e64 v5, null                ; encoding: 
[0x05,0x00,0xca,0xd5,0x7c,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, -1
+// GFX1250: v_tanh_bf16_e64 v5, -1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0xc1,0x00,0x00,0x00]
+
+v_tanh_bf16_e64 v5, 0.5 mul:2
+// GFX1250: v_tanh_bf16_e64 v5, 0.5 mul:2           ; encoding: 
[0x05,0x00,0xca,0xd5,0xf0,0x00,0x00,0x08]
+
+v_tanh_bf16_e64 v5, src_scc mul:4
+// GFX1250: v_tanh_bf16_e64 v5, src_scc mul:4       ; encoding: 
[0x05,0x00,0xca,0xd5,0xfd,0x00,0x00,0x10]
+
+v_tanh_bf16_e64 v255, -|0x8000| clamp div:2
+// GFX1250: v_tanh_bf16_e64 v255, -|0x8000| clamp div:2 ; encoding: 
[0xff,0x81,0xca,0xd5,0xff,0x00,0x00,0x38,0x00,0x80,0x00,0x00]
+
+v_tanh_bf16 v5.l, v128.h
+// GFX1250: v_tanh_bf16_e64 v5.l, v128.h op_sel:[1,0] ; encoding: 
[0x05,0x08,0xca,0xd5,0x80,0x01,0x00,0x00]
+
 v_cvt_f32_bf8_e64 v1, s3
 // GFX1250: v_cvt_f32_bf8_e64 v1, s3                ; encoding: 
[0x01,0x00,0xed,0xd5,0x03,0x00,0x00,0x00]
 
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
index ea22a8cbdda03..f7cb2234fa059 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16-fake16.s
@@ -2,6 +2,62 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 
-show-encoding < %s | FileCheck --check-prefix=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_mirror
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_half_mirror
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_half_mirror row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shl:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shl:15
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shr:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shr:15
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_ror:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_ror:15
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf 
; encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 
bank_mask:0x1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 
bound_ctrl:1 fi:0
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 
bank_mask:0x3 bound_ctrl:1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 
bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX1250: v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 
row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: 
[0xff,0x81,0xca,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xf2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
index 868bbe7cdde3a..dfa9741c7cf30 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp16.s
@@ -2,6 +2,66 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 
-show-encoding < %s | FileCheck --check-prefix=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_mirror
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_half_mirror
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_half_mirror row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shl:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shl:15
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shr:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_shr:15
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_ror:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_ror:15
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; 
encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf 
; encoding: [0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 
bank_mask:0x1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 
bound_ctrl:1 fi:0
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 
bank_mask:0x3 bound_ctrl:1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 
bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX1250: v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 
row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: 
[0xff,0x81,0xca,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5.h, v128.h quad_perm:[3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5.h, v128.h op_sel:[1,1] quad_perm:[3,2,1,0] 
row_mask:0xf bank_mask:0xf ; encoding: 
[0x05,0x48,0xca,0xd5,0xfa,0x00,0x00,0x00,0x80,0x1b,0x00,0xff]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xf2,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
index e2c9bc4387138..686209d1f5189 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
@@ -2,6 +2,22 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 
-show-encoding < %s | FileCheck --check-prefix=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; 
encoding: [0x05,0x00,0xca,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX1250: v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 
dpp8:[0,0,0,0,0,0,0,0] ; encoding: 
[0xff,0x81,0xca,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0x05,0x00,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s 
b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
index 2ea30aeb38fc1..52cbe92dd5dca 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
@@ -2,6 +2,26 @@
 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 
-show-encoding < %s | FileCheck --check-prefix=GFX1250 %s
 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 
-show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR 
--implicit-check-not=error: --strict-whitespace %s
 
+v_tanh_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX1250: v_tanh_bf16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; 
encoding: [0x05,0x00,0xca,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX1250: v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 
dpp8:[0,0,0,0,0,0,0,0] ; encoding: 
[0xff,0x81,0xca,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16_e64_dpp v5.h, v128.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX1250: v_tanh_bf16_e64_dpp v5.h, v128.h op_sel:[1,1] 
dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0x05,0x48,0xca,0xd5,0xe9,0x00,0x00,0x00,0x80,0x77,0x39,0x05]
+// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+
 v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX1250: v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0x05,0x00,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 // GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt 
b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
index 1a87993fb8e0b..1b1f65b4398cd 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
@@ -26,6 +26,69 @@
 0x6a,0x3a,0x08,0x7e
 # GFX1250: v_mov_b64_e32 v[4:5], vcc               ; encoding: 
[0x6a,0x3a,0x08,0x7e]
 
+0xff,0x94,0xfe,0x7e,0x00,0x80,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e32 v127.l, 0x8000          ; encoding: 
[0xff,0x94,0xfe,0x7e,0x00,0x80,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v127, 0x8000            ; encoding: 
[0xff,0x94,0xfe,0x7e,0x00,0x80,0x00,0x00]
+
+0xc1,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, -1                ; encoding: 
[0xc1,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, -1                  ; encoding: 
[0xc1,0x94,0x0a,0x7e]
+
+0xf0,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, 0.5               ; encoding: 
[0xf0,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, 0.5                 ; encoding: 
[0xf0,0x94,0x0a,0x7e]
+
+0x7f,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, exec_hi           ; encoding: 
[0x7f,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, exec_hi             ; encoding: 
[0x7f,0x94,0x0a,0x7e]
+
+0x7e,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, exec_lo           ; encoding: 
[0x7e,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, exec_lo             ; encoding: 
[0x7e,0x94,0x0a,0x7e]
+
+0x7d,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, m0                ; encoding: 
[0x7d,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, m0                  ; encoding: 
[0x7d,0x94,0x0a,0x7e]
+
+0x7c,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, null              ; encoding: 
[0x7c,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, null                ; encoding: 
[0x7c,0x94,0x0a,0x7e]
+
+0x01,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, s1                ; encoding: 
[0x01,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, s1                  ; encoding: 
[0x01,0x94,0x0a,0x7e]
+
+0x69,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, s105              ; encoding: 
[0x69,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, s105                ; encoding: 
[0x69,0x94,0x0a,0x7e]
+
+0xfd,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, src_scc           ; encoding: 
[0xfd,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, src_scc             ; encoding: 
[0xfd,0x94,0x0a,0x7e]
+
+0x7b,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, ttmp15            ; encoding: 
[0x7b,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, ttmp15              ; encoding: 
[0x7b,0x94,0x0a,0x7e]
+
+0x01,0x95,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, v1.l              ; encoding: 
[0x01,0x95,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, v1                  ; encoding: 
[0x01,0x95,0x0a,0x7e]
+
+0x7f,0x95,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, v127.l            ; encoding: 
[0x7f,0x95,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, v127                ; encoding: 
[0x7f,0x95,0x0a,0x7e]
+
+0x6b,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, vcc_hi            ; encoding: 
[0x6b,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, vcc_hi              ; encoding: 
[0x6b,0x94,0x0a,0x7e]
+
+0x6a,0x94,0x0a,0x7e
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.l, vcc_lo            ; encoding: 
[0x6a,0x94,0x0a,0x7e]
+# GFX1250-FAKE16: v_tanh_bf16_e32 v5, vcc_lo              ; encoding: 
[0x6a,0x94,0x0a,0x7e]
+
+0x81,0x95,0x0a,0x7f
+# GFX1250-REAL16: v_tanh_bf16_e32 v5.h, v1.h              ; encoding: 
[0x81,0x95,0x0a,0x7f]
+
 0xff,0xe4,0xfe,0x7e,0x00,0x80,0x00,0x00
 # GFX1250: v_cvt_f32_bf16_e32 v127, 0x8000         ; encoding: 
[0xff,0xe4,0xfe,0x7e,0x00,0x80,0x00,0x00]
 
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt 
b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
index 1475be10201a5..db36451c61715 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp16.txt
@@ -2,6 +2,65 @@
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
 
+0xfa,0x94,0xfe,0x7e,0x7f,0x6f,0x35,0x30
+# GFX1250-REAL16: v_tanh_bf16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 
bank_mask:0x0 fi:1 ; encoding: [0xfa,0x94,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 
bank_mask:0x0 fi:1 ; encoding: [0xfa,0x94,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
+
+0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l quad_perm:[0,1,2,3] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_half_mirror row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_half_mirror row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_mirror row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_ror:1 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_ror:15 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x50,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_share:0 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x50,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_share:0 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x50,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x5f,0x01,0x01
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_share:15 row_mask:0x0 
bank_mask:0x1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_share:15 row_mask:0x0 
bank_mask:0x1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x5f,0x01,0x01]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_shl:1 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_shl:15 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_shr:1 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_shr:15 row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf 
; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0xff]
+
+0xfa,0x94,0x0a,0x7e,0x01,0x60,0x09,0x13
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l row_xmask:0 row_mask:0x1 
bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x60,0x09,0x13]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 row_xmask:0 row_mask:0x1 
bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0x60,0x09,0x13]
+
+0xfa,0x94,0x0a,0x7f,0x81,0x1b,0x00,0xff
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.h, v1.h quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7f,0x81,0x1b,0x00,0xff]
+
 0xfa,0xe4,0xfe,0x7e,0x7f,0x6f,0x35,0x30
 # GFX1250: v_cvt_f32_bf16_dpp v127, -|v127.l| row_xmask:15 row_mask:0x3 
bank_mask:0x0 fi:1 ; encoding: [0xfa,0xe4,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
 
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt 
b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
index 274b58769911a..4598efc07f489 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
@@ -2,6 +2,22 @@
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
 
+0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; 
encoding: [0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; 
encoding: [0xe9,0x94,0xfe,0x7e,0x7f,0x00,0x00,0x00]
+
+0xe9,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0xe9,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0xe9,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+0xea,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; 
encoding: [0xea,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_bf16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; 
encoding: [0xea,0x94,0x0a,0x7e,0x01,0x77,0x39,0x05]
+
+0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05
+# GFX1250-REAL16: v_tanh_bf16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0xe9,0x94,0x0a,0x7f,0x81,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: 
[0x81,0x77,0x39,0x05]
+
 0xe9,0xe4,0xfe,0x7e,0x7f,0x00,0x00,0x00
 # GFX1250: v_cvt_f32_bf16_dpp v127, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: 
[0xe9,0xe4,0xfe,0x7e,0x7f,0x00,0x00,0x00]
 
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt 
b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
index e0acec3c1e3e9..3e345d73cd996 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
@@ -2,6 +2,70 @@
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
 
+0xff,0x81,0xca,0xd5,0xff,0x00,0x00,0x38,0x00,0x80,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v255.l, -|0x8000| clamp div:2 ; encoding: 
[0xff,0x81,0xca,0xd5,0xff,0x00,0x00,0x38,0x00,0x80,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v255, -|0x8000| clamp div:2 ; encoding: 
[0xff,0x81,0xca,0xd5,0xff,0x00,0x00,0x38,0x00,0x80,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0xc1,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, -1                ; encoding: 
[0x05,0x00,0xca,0xd5,0xc1,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, -1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0xc1,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0xf0,0x00,0x00,0x08
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, 0.5 mul:2         ; encoding: 
[0x05,0x00,0xca,0xd5,0xf0,0x00,0x00,0x08]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, 0.5 mul:2           ; encoding: 
[0x05,0x00,0xca,0xd5,0xf0,0x00,0x00,0x08]
+
+0x05,0x00,0xca,0xd5,0x7f,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, exec_hi           ; encoding: 
[0x05,0x00,0xca,0xd5,0x7f,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, exec_hi             ; encoding: 
[0x05,0x00,0xca,0xd5,0x7f,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x7e,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, exec_lo           ; encoding: 
[0x05,0x00,0xca,0xd5,0x7e,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, exec_lo             ; encoding: 
[0x05,0x00,0xca,0xd5,0x7e,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x7d,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, m0                ; encoding: 
[0x05,0x00,0xca,0xd5,0x7d,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, m0                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x7d,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x7c,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, null              ; encoding: 
[0x05,0x00,0xca,0xd5,0x7c,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, null                ; encoding: 
[0x05,0x00,0xca,0xd5,0x7c,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x01,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, s1                ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, s1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x69,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, s105              ; encoding: 
[0x05,0x00,0xca,0xd5,0x69,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, s105                ; encoding: 
[0x05,0x00,0xca,0xd5,0x69,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0xfd,0x00,0x00,0x10
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, src_scc mul:4     ; encoding: 
[0x05,0x00,0xca,0xd5,0xfd,0x00,0x00,0x10]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, src_scc mul:4       ; encoding: 
[0x05,0x00,0xca,0xd5,0xfd,0x00,0x00,0x10]
+
+0x05,0x00,0xca,0xd5,0x7b,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, ttmp15            ; encoding: 
[0x05,0x00,0xca,0xd5,0x7b,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, ttmp15              ; encoding: 
[0x05,0x00,0xca,0xd5,0x7b,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x01,0x01,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, v1.l              ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x01,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, v1                  ; encoding: 
[0x05,0x00,0xca,0xd5,0x01,0x01,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0xff,0x01,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, v255.l            ; encoding: 
[0x05,0x00,0xca,0xd5,0xff,0x01,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, v255                ; encoding: 
[0x05,0x00,0xca,0xd5,0xff,0x01,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x6b,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, vcc_hi            ; encoding: 
[0x05,0x00,0xca,0xd5,0x6b,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, vcc_hi              ; encoding: 
[0x05,0x00,0xca,0xd5,0x6b,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0x6a,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, vcc_lo            ; encoding: 
[0x05,0x00,0xca,0xd5,0x6a,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, vcc_lo              ; encoding: 
[0x05,0x00,0xca,0xd5,0x6a,0x00,0x00,0x00]
+
+0x05,0x08,0xca,0xd5,0x80,0x01,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64 v5.l, v128.h op_sel:[1,0] ; encoding: 
[0x05,0x08,0xca,0xd5,0x80,0x01,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64 v5, v128                ; encoding: 
[0x05,0x00,0xca,0xd5,0x80,0x01,0x00,0x00]
+
 0x01,0x00,0xed,0xd5,0x83,0x00,0x00,0x00
 # GFX1250: v_cvt_f32_bf8_e64 v1, 3                 ; encoding: 
[0x01,0x00,0xed,0xd5,0x83,0x00,0x00,0x00]
 
diff --git 
a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt 
b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
index eadd315ea411b..bae8909bb550e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
@@ -2,6 +2,66 @@
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250-REAL16 %s
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250-FAKE16 %s
 
+0xff,0x81,0xca,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v255.l, -|v255.l| clamp div:2 
row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: 
[0xff,0x81,0xca,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 
row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: 
[0xff,0x81,0xca,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l mul:2 row_share:15 
row_mask:0x0 bank_mask:0x1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 
bank_mask:0x1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l mul:4 row_xmask:0 
row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 
bank_mask:0x3 bound_ctrl:1 ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l quad_perm:[0,1,2,3] 
row_mask:0xf bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l quad_perm:[3,2,1,0] 
row_mask:0xf bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_half_mirror row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_half_mirror row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_mirror row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_mirror row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_ror:1 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_ror:1 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_ror:15 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_ror:15 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_share:0 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_share:0 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_shl:1 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_shl:1 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_shl:15 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_shl:15 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_shr:1 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_shr:1 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
+
+0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l row_shr:15 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 row_shr:15 row_mask:0xf 
bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
+
+0x05,0x48,0xca,0xd5,0xfa,0x00,0x00,0x00,0x80,0x1b,0x00,0xff
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.h, v128.h op_sel:[1,1] 
quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: 
[0x05,0x48,0xca,0xd5,0xfa,0x00,0x00,0x00,0x80,0x1b,0x00,0xff]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v128 quad_perm:[3,2,1,0] 
row_mask:0xf bank_mask:0xf ; encoding: 
[0x05,0x00,0xca,0xd5,0xfa,0x00,0x00,0x00,0x80,0x1b,0x00,0xff]
+
 0x05,0x00,0xf2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
 # GFX1250-REAL16: v_cvt_f32_bf16_e64_dpp v5, v1.l quad_perm:[0,1,2,3] 
row_mask:0xf bank_mask:0xf ; encoding: 
[0x05,0x00,0xf2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
 # GFX1250-FAKE16: v_cvt_f32_bf16_e64_dpp v5, v1 quad_perm:[0,1,2,3] 
row_mask:0xf bank_mask:0xf ; encoding: 
[0x05,0x00,0xf2,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
diff --git 
a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt 
b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
index 3b2fbe10c61a5..52f7932205dad 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
@@ -2,6 +2,26 @@
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250-REAL16 %s
 # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble 
-show-encoding < %s | FileCheck -check-prefixes=GFX1250-FAKE16 %s
 
+0xff,0x81,0xca,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v255.l, -|v255.l| clamp div:2 
dpp8:[0,0,0,0,0,0,0,0] ; encoding: 
[0xff,0x81,0xca,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v255, -|v255| clamp div:2 
dpp8:[0,0,0,0,0,0,0,0] ; encoding: 
[0xff,0x81,0xca,0xd5,0xe9,0x00,0x00,0x38,0xff,0x00,0x00,0x00]
+
+0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
+0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l mul:2 dpp8:[7,6,5,4,3,2,1,0] 
; encoding: [0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
+
+0x05,0x00,0xca,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.l, v1.l mul:4 dpp8:[7,6,5,4,3,2,1,0] 
fi:1 ; encoding: [0x05,0x00,0xca,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 
; encoding: [0x05,0x00,0xca,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
+
+0x05,0x48,0xca,0xd5,0xe9,0x00,0x00,0x00,0x80,0x77,0x39,0x05
+# GFX1250-REAL16: v_tanh_bf16_e64_dpp v5.h, v128.h op_sel:[1,1] 
dpp8:[7,6,5,4,3,2,1,0] ; encoding: 
[0x05,0x48,0xca,0xd5,0xe9,0x00,0x00,0x00,0x80,0x77,0x39,0x05]
+# GFX1250-FAKE16: v_tanh_bf16_e64_dpp v5, v128 dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xca,0xd5,0xe9,0x00,0x00,0x00,0x80,0x77,0x39,0x05]
+
 0x05,0x00,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
 # GFX1250-REAL16: v_cvt_f32_bf16_e64_dpp v5, v1.l dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 # GFX1250-FAKE16: v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; 
encoding: [0x05,0x00,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]

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