@@ -313,6 +313,72 @@ let TargetGuard = "sme2" in {
def SVBMOPA : Inst<"svbmopa_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNo
@@ -313,6 +313,72 @@ let TargetGuard = "sme2" in {
def SVBMOPA : Inst<"svbmopa_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNo
@@ -10570,6 +10570,26 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Builder.CreateCall(F, llvm::ConstantInt::get(Int32Ty, HintID));
}
+ if (BuiltinID == clang::AArch64::BI__builtin_arm_get_sme_state) {
+// Create call to __arm_sme_sta
@@ -1600,6 +1600,25 @@ void SVEEmitter::createSMEHeader(raw_ostream &OS) {
OS << "extern \"C\" {\n";
OS << "#endif\n\n";
+ OS << "void __arm_za_disable(void) __arm_streaming_compatible;\n\n";
+
+ OS << "__ai bool __arm_has_sme(void) __arm_streaming_compatible {\n";
+ OS
@@ -10570,6 +10570,26 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Builder.CreateCall(F, llvm::ConstantInt::get(Int32Ty, HintID));
}
+ if (BuiltinID == clang::AArch64::BI__builtin_arm_get_sme_state) {
+// Create call to __arm_sme_sta
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
@@ -315,6 +315,219 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+// FMLA/FMLS
+let TargetGuard = "sme2" in {
+ def SVMLA_MULTI_VG
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/75958
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I also noticed that a number of tests are failing with your patch at the moment.
https://github.com/llvm/llvm-project/pull/75958
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@@ -679,6 +679,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const
{
.Case("f32mm", FPU & SveMode && HasMatmulFP32)
.Case("f64mm", FPU & SveMode && HasMatmulFP64)
.Case("sve2", FPU & SveMode && HasSVE2)
+ .Case("sve2p1", HasSVE2p1)
-
@@ -8,7 +8,7 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror
-Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim |
FileCheck %s
// RUN: %clang_cc1 -f
@@ -1,78 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
sdesmalen-arm wrote:
Why is this file removed? (same question for `acle_sve2p1_sclamp.c`)
https://github.com/llvm/llvm-project/pull/75958
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/75584
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@@ -227,6 +227,7 @@ def IsPreservesZA : FlagType<0x100>;
def IsReadZA : FlagType<0x200>;
def IsWriteZA : FlagType<0x400>;
def IsReductionQV : FlagType<0x800>;
+def IsStreamingOrSVE2p1
@@ -1280,6 +1280,7 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
OS << "typedef __SVBfloat16_t svbfloat16_t;\n";
OS << "#include \n";
+ OS << "#include \n";
sdesmalen-arm wrote:
I'm missing similar changes for NeonEmitter.cpp where this include wou
@@ -2546,6 +2548,44 @@ void NeonEmitter::runFP16(raw_ostream &OS) {
OS << "#endif /* __ARM_FP16_H */\n";
}
+void NeonEmitter::runVectorType(raw_ostream &OS) {
+ OS << "/*=== arm_vector_type - ARM vector type "
+"--===\n"
+" *\n"
+" *\n"
+
@@ -279,11 +282,14 @@ cl::opt Action(
"Generate riscv_vector_builtin_cg.inc for clang"),
clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
"Generate riscv_vector_builtin_sema.inc for clang"),
-clEnumValN
@@ -2546,6 +2548,44 @@ void NeonEmitter::runFP16(raw_ostream &OS) {
OS << "#endif /* __ARM_FP16_H */\n";
}
+void NeonEmitter::runVectorType(raw_ostream &OS) {
+ OS << "/*=== arm_vector_type - ARM vector type "
+"--===\n"
+" *\n"
+" *\n"
+
@@ -0,0 +1,13 @@
+//===--- arm_vector_type.td - ARM Fixed vector types compiler interface
---===//
sdesmalen-arm wrote:
What is the value of this file?
https://github.com/llvm/llvm-project/pull/73258
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@@ -2546,6 +2548,44 @@ void NeonEmitter::runFP16(raw_ostream &OS) {
OS << "#endif /* __ARM_FP16_H */\n";
}
+void NeonEmitter::runVectorType(raw_ostream &OS) {
+ OS << "/*=== arm_vector_type - ARM vector type "
sdesmalen-arm wrote:
For here and everywhe
@@ -2546,6 +2548,44 @@ void NeonEmitter::runFP16(raw_ostream &OS) {
OS << "#endif /* __ARM_FP16_H */\n";
}
+void NeonEmitter::runVectorType(raw_ostream &OS) {
+ OS << "/*=== arm_vector_type - ARM vector type "
+"--===\n"
+" *\n"
+" *\n"
+
@@ -0,0 +1,113 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
sdesmalen-arm wrote:
Given my previous comment, I think it's also worth having a test for:
```
#include
#include
```
and
```
#include
#i
@@ -5,6 +5,11 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s |
FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-li
@@ -15,7 +22,7 @@
// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call
@llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") [[C:%.*]], i32 0)
// CPP-CHECK-NEXT:ret [[TMP0]]
//
-svbool_t test_svpext_lane_c8_0(svcount_t c) {
+svbool_t test_svpext_lane_c8_0(svcount_t c) __arm
@@ -1,10 +1,17 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1
@@ -1859,19 +1859,28 @@ def SVBGRP : SInst<"svbgrp[_{d}]", "ddd",
"UcUsUiUl", MergeNone, "aarch64_sv
def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone,
"aarch64_sve_bgrp_x">;
}
+let TargetGuard = "sve2p1|sme" in {
sdesmalen-arm wrote:
https://github.com/sdesmalen-arm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/72272
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@@ -3136,6 +3192,31 @@ bool Sema::CheckSVEBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
bool Sema::CheckNeonBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr *TheCall)
{
+ if (const FunctionDecl *FD
@@ -2993,6 +2993,62 @@ static QualType getNeonEltType(NeonTypeFlags Flags,
ASTContext &Context,
llvm_unreachable("Invalid NeonTypeFlag!");
}
+enum ArmStreamingType {
+ ArmNonStreaming,
+ ArmStreaming,
+ ArmStreamingCompatible,
+ ArmLocallyStreaming,
+ ArmStreamingOrSVE
@@ -0,0 +1,24 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN: -target-feature +sme -target-feature +sve2 -target-feature +neon
-fsyntax-only -verify %s
+
+// RE
@@ -3136,6 +3192,31 @@ bool Sema::CheckSVEBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
bool Sema::CheckNeonBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr *TheCall)
{
+ if (const FunctionDecl *FD
@@ -2993,6 +2993,62 @@ static QualType getNeonEltType(NeonTypeFlags Flags,
ASTContext &Context,
llvm_unreachable("Invalid NeonTypeFlag!");
}
+enum ArmStreamingType {
+ ArmNonStreaming,
+ ArmStreaming,
+ ArmStreamingCompatible,
+ ArmLocallyStreaming,
+ ArmStreamingOrSVE
@@ -2993,6 +2993,62 @@ static QualType getNeonEltType(NeonTypeFlags Flags,
ASTContext &Context,
llvm_unreachable("Invalid NeonTypeFlag!");
}
+enum ArmStreamingType {
+ ArmNonStreaming,
+ ArmStreaming,
+ ArmStreamingCompatible,
+ ArmLocallyStreaming,
+ ArmStreamingOrSVE
https://github.com/sdesmalen-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/73188
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@@ -2993,6 +2993,47 @@ static QualType getNeonEltType(NeonTypeFlags Flags,
ASTContext &Context,
llvm_unreachable("Invalid NeonTypeFlag!");
}
+enum ArmStreamingType {
+ ArmNonStreaming,
+ ArmStreaming,
+ ArmStreamingCompatible,
+ ArmLocallyStreaming
+};
+
+static ArmStre
https://github.com/sdesmalen-arm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/73672
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@@ -326,9 +326,14 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
return false;
}
- template bool ImmToTile(SDValue N, SDValue &Imm) {
+ template
+ bool ImmToTile(SDValue N, SDValue &Imm) {
sdesmalen-arm wrote:
If `ImmToTile` is now used f
@@ -298,3 +298,11 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// lookup table expand two contiguous registers
+//
+let TargetGuard = "sme2" in {
+ def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.dmdm",
"cUcsUsiUibhf"
@@ -298,3 +298,11 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// lookup table expand two contiguous registers
+//
+let TargetGuard = "sme2" in {
+ def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.dmdm",
"cUcsUsiUibhf"
https://github.com/sdesmalen-arm requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/73304
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@@ -298,3 +298,11 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// lookup table expand one register
+//
+let TargetGuard = "sme2" in {
+ def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "didi", "cUcsUsiUibhf",
MergeNone, "aarch6
@@ -305,4 +305,9 @@ defm SVSUB : ZAAddSub<"sub">;
let TargetGuard = "sme2" in {
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
def SVSTR_ZT : Inst
@@ -2746,19 +2746,25 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
-MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
- MachineBasicBlock
*
@@ -2746,19 +2746,25 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
-MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
- MachineBasicBlock
*
https://github.com/sdesmalen-arm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/74066
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LGTM with comment addressed.
https://github.com/llvm/llvm-project/pull/72274
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@@ -0,0 +1,23 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
@@ -6,20 +6,20 @@
#include
__attribute__((target("sme")))
-void test_sme(svbool_t pg, void *ptr) {
+void test_sme(svbool_t pg, void *ptr) __arm_streaming {
svld1_hor_za8(0, 0, pg, ptr);
}
__attribute__((target("arch=armv8-a+sme")))
-void test_arch_sme(svbool_t pg, void
@@ -3023,6 +3151,66 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
<< TheCall->getSourceRange() << "streaming compatible";
return;
}
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
dia
@@ -289,7 +283,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_vnum_za64(uint32_t
slice_base, svbool_t p
// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.st1q.vert( [[TMP0]], ptr [[TMP2]], i32 15, i32 [[SLICE_BASE]])
// CHECK-CXX-NEXT:ret void
//
-ARM_STREAMING_ATTR void
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@@ -2119,6 +2119,21 @@ let TargetGuard = "sme2" in {
// 2-way and 4-way selects
def SVSEL_X2 : SInst<"svsel[_{d}_x2]", "2}22", "cUcsUsiUilUlbhfd",
MergeNone, "aarch64_sve_sel_x2", [IsStreaming], []>;
def SVSEL_X4 : SInst<"svsel[_{d}_x4]", "4}44", "cUcsUsiUilUlbhfd",
M
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@@ -298,3 +298,11 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// Spill and fill of ZT0
+//
+let TargetGuard = "sme2" in {
+ def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamin
@@ -319,7 +319,7 @@ let TargetGuard = "sme2" in {
// Spill and fill of ZT0
//
let TargetGuard = "sme2" in {
- def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck
@@ -1109,10 +1109,10 @@ def SVPFALSE : SInst<"svpfalse[_b]", "Pv", "",
MergeNone, "", [IsOverloadNone, I
def SVPTRUE_PAT : SInst<"svptrue_pat_{d}", "PI", "PcPsPiPl", MergeNone,
"aarch64_sve_ptrue", [IsStreamingCompatible]>;
def SVPTRUE : SInst<"svptrue_{d}", "Pv", "Pc
https://github.com/sdesmalen-arm closed
https://github.com/llvm/llvm-project/pull/75791
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https://github.com/sdesmalen-arm requested changes to this pull request.
Perhaps I'm missing something obvious here, but it looks like this patch is
implementing the opposite of #75958 ?
https://github.com/llvm/llvm-project/pull/76712
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https://github.com/llvm/llvm-project/pull/75958
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sdesmalen-arm wrote:
I'm aware the PR is quite large, but I didn't really know a sensible way to
split this up. I'm happy to split things out if there are any suggestions.
https://github.com/llvm/llvm-project/pull/76971
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cf
@@ -1952,10 +1952,6 @@ def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc",
MergeNone, "", [IsStreamin
def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "",
[IsStreamingCompatible], []>;
def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "",
[IsS
@@ -1979,6 +1975,11 @@ let TargetGuard = "sve2p1|sme2" in {
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingOrSVE2p1], [ImmCheck<1, ImmCheck0_3>]>;
def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
M
@@ -6787,6 +6787,9 @@ void Parser::ParseDirectDeclarator(Declarator &D) {
// For consistency with attribute parsing.
Diag(Tok, diag::err_keyword_not_allowed) << Tok.getIdentifierInfo();
ConsumeToken();
+ BalancedDelimiterTracker T(*this, tok::l_paren);
--
@@ -3175,11 +3175,16 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
}
static bool hasSMEZAState(const FunctionDecl *FD) {
- if (FD->hasAttr())
-return true;
- if (const auto *T = FD->getType()->getAs())
-if (T->getAArch64SMEAttributes() & Functi
@@ -1767,14 +1767,22 @@ static void
AddAttributesFromFunctionProtoType(ASTContext &Ctx,
FPT->isNothrow())
FuncAttrs.addAttribute(llvm::Attribute::NoUnwind);
- if (FPT->getAArch64SMEAttributes() & FunctionType::SME_PStateSMEnabledMask)
+ unsigned SMEBits = FPT->get
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@@ -3095,23 +3095,23 @@ let TargetPrefix = "aarch64" in {
[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
- class SME2_CVT_FtoI_VG2_Intrinsic
+ class SME2_CVT_ItoF_VG2_Intrinsic
https://github.com/sdesmalen-arm commented:
Looks good, thanks for fixing. Just left one little nit.
https://github.com/llvm/llvm-project/pull/77656
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@@ -34,118 +34,118 @@ define
@multi_vector_cvt_x2_bf16( %unu
;
; FCVTZS
;
-define {, }
@multi_vector_cvt_x2_f32_s32( %unused,
%zn0, %zn1) {
-; CHECK-LABEL: multi_vector_cvt_x2_f32_s32:
+define {, }
@multi_vector_cvt_x2_s32_f32( %unused,
%zn0, %zn1) {
+; CHECK-LABEL:
https://github.com/sdesmalen-arm created
https://github.com/llvm/llvm-project/pull/77792
See the specification for more details:
*
https://github.com/ARM-software/acle/blob/main/main/acle.md#udot-sdot-fdot-vectors
*
https://github.com/ARM-software/acle/blob/main/main/acle.md#udot-sdot-fdot-ind
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Author: Sander de Smalen
Date: 2022-02-11T09:00:29Z
New Revision: 0b41238ae7f91bcc907a577377caa70721ffc400
URL:
https://github.com/llvm/llvm-project/commit/0b41238ae7f91bcc907a577377caa70721ffc400
DIFF:
https://github.com/llvm/llvm-project/commit/0b41238ae7f91bcc907a577377caa70721ffc400.diff
L
@@ -3717,6 +3717,16 @@ def err_sme_definition_using_za_in_non_sme_target :
Error<
"function using ZA state requires 'sme'">;
def err_sme_definition_using_zt0_in_non_sme2_target : Error<
"function using ZT0 state requires 'sme2'">;
+def warn_sme_streaming_pass_return_vl_to_
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/79842
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https://github.com/sdesmalen-arm commented:
Thanks for the update. I just left a few more suggestions to clean up the code
a bit.
https://github.com/llvm/llvm-project/pull/79842
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@@ -7513,6 +7516,30 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+bool IsCalleeStreaming =
+(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
+bool IsC
@@ -7513,6 +7516,30 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+bool IsCalleeStreaming =
+(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
+bool IsC
@@ -7513,6 +7516,30 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
sdesmalen-arm wrote:
nit: move this closer to its use, preferably wrap the condition, e.g.
```
if (auto
@@ -7513,6 +7516,30 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+bool IsCalleeStreaming =
+(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
-
@@ -7513,6 +7516,30 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+bool IsCalleeStreaming =
+(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
+bool IsC
@@ -7513,6 +7516,30 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+bool IsCalleeStreaming =
+(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
+bool IsC
@@ -7513,6 +7516,30 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+bool IsCalleeStreaming =
+(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
+bool IsC
@@ -3723,8 +3723,8 @@ def warn_sme_streaming_pass_return_vl_to_non_streaming :
Warning<
" different">,
InGroup, DefaultIgnore;
def warn_sme_locally_streaming_has_vl_args_returns : Warning<
- "passing/returning a VL-dependent argument from a function"
- " arm_locally_stre
@@ -7516,28 +7516,23 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
-auto *CallerFD = dyn_cast(CurContext);
-bool IsCalleeStreaming =
-(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
-bool Is
@@ -7516,28 +7516,23 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
-auto *CallerFD = dyn_cast(CurContext);
-bool IsCalleeStreaming =
-(ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask);
-bool Is
@@ -1390,6 +1390,9 @@ def MultiGPU: DiagGroup<"multi-gpu">;
// libc and the CRT to be skipped.
def AVRRtlibLinkingQuirks : DiagGroup<"avr-rtlib-linking-quirks">;
+// A warning group AArch64 related to SME function attribues.
sdesmalen-arm wrote:
nit: Sorry, j
@@ -3717,6 +3717,16 @@ def err_sme_definition_using_za_in_non_sme_target :
Error<
"function using ZA state requires 'sme'">;
def err_sme_definition_using_zt0_in_non_sme2_target : Error<
"function using ZT0 state requires 'sme2'">;
+def warn_sme_streaming_pass_return_vl_to_
@@ -3717,6 +3717,30 @@ def err_sme_definition_using_za_in_non_sme_target :
Error<
"function using ZA state requires 'sme'">;
def err_sme_definition_using_zt0_in_non_sme2_target : Error<
"function using ZT0 state requires 'sme2'">;
+def warn_sme_streaming_caller_pass_args_t
@@ -3717,6 +3717,30 @@ def err_sme_definition_using_za_in_non_sme_target :
Error<
"function using ZA state requires 'sme'">;
def err_sme_definition_using_zt0_in_non_sme2_target : Error<
"function using ZT0 state requires 'sme2'">;
+def warn_sme_streaming_caller_pass_args_t
@@ -7513,6 +7516,38 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+if (FD && CallerFD && Context.getTargetInfo().hasFeature("sme") &&
+!FD->getBuiltinID()) {
+ // If the cal
@@ -3717,6 +3717,30 @@ def err_sme_definition_using_za_in_non_sme_target :
Error<
"function using ZA state requires 'sme'">;
def err_sme_definition_using_zt0_in_non_sme2_target : Error<
"function using ZT0 state requires 'sme2'">;
+def warn_sme_streaming_caller_pass_args_t
@@ -445,3 +448,54 @@ void conflicting_state_attrs_preserves_out_zt0(void)
__arm_preserves("zt0") __ar
// expected-cpp-error@+2 {{conflicting attributes for state 'zt0'}}
// expected-error@+1 {{conflicting attributes for state 'zt0'}}
void conflicting_state_attrs_preserves_inou
@@ -7513,6 +7516,38 @@ void Sema::checkCall(NamedDecl *FDecl, const
FunctionProtoType *Proto,
}
}
+auto *CallerFD = dyn_cast(CurContext);
+if (FD && CallerFD && Context.getTargetInfo().hasFeature("sme") &&
sdesmalen-arm wrote:
This code req
@@ -3501,9 +3501,18 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc,
StringRef AttrStr) {
return false;
}
+static bool isArmStreaming(const FunctionDecl *FD) {
+ if (FD->hasAttr())
+return true;
sdesmalen-arm wrote:
Is this check required? I t
@@ -454,3 +454,34 @@ void unimplemented_spill_fill_za(void
(*share_zt0_only)(void) __arm_inout("zt0")
// expected-note@+1 {{add '__arm_preserves("za")' to the callee if it
preserves ZA}}
share_zt0_only();
}
+
+// expected-cpp-error@+2 {{streaming function cannot be multi-
https://github.com/sdesmalen-arm approved this pull request.
LGTM with nit addressed
https://github.com/llvm/llvm-project/pull/81268
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