[clang] [llvm] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

https://github.com/rgwott approved this pull request. Looking good. Is there a document to reference in the commit message? https://github.com/llvm/llvm-project/pull/75055 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[clang] [llvm] [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (PR #73777)

https://github.com/rgwott approved this pull request. Approved. https://github.com/llvm/llvm-project/pull/73777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [AArch64] Assembly support for the Armv9.5-A Memory System Extensions (PR #76237)

https://github.com/rgwott approved this pull request. Great patch, looks good to me. https://github.com/llvm/llvm-project/pull/76237 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Remove Automatic Enablement of FEAT_F32MM (PR #85203)

@@ -2487,10 +2480,10 @@ AArch64ExtensionDependenciesBaseCPUTestParams {}}, {"cortex-a520", {}, - {"v9.2a","bf16", "crc", "dotprod", "f32mm", "flagm", - "fp-armv8", "fullfp16", "fp16fml", "i8mm","lse", "

[clang] [Clang][AArch64] Add ACLE macros for FEAT_PAuth_LR (PR #80163)

https://github.com/rgwott approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/80163 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -1462,6 +1462,10 @@ enum NodeType { // Outputs: [rv], output chain, glue PATCHPOINT, + // PTRADD represents pointer arithmetic semantics, for those targets which + // benefit from that information. rgwott wrote: Done. https://github.com/llvm/llvm-pr

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -401,7 +401,7 @@ def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; -def ptradd : SDNode<"ISD::ADD" , SDTPtrAddOp, []>; +def

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -0,0 +1,451 @@ +; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O0 -global-isel=0 -fast-isel=0 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK-CPA-O0 rgwott wrote: I have put codegen behind -mcpa-codegen. Let me know if you prefer some oth

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

https://github.com/rgwott updated https://github.com/llvm/llvm-project/pull/105669 >From b26f61578c033eb6be0484e7346970176caafce2 Mon Sep 17 00:00:00 2001 From: Rodolfo Wottrich Date: Thu, 22 Aug 2024 15:17:00 +0100 Subject: [PATCH 01/13] [AArch64] Add CodeGen support for FEAT_CPA CPA stands f

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -0,0 +1,451 @@ +; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O0 -global-isel=0 -fast-isel=0 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK-CPA-O0 +; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O3 -global-isel=0 -fast-isel=0 %s -o - 2>

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -0,0 +1,451 @@ +; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O0 -global-isel=0 -fast-isel=0 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK-CPA-O0 +; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O3 -global-isel=0 -fast-isel=0 %s -o - 2>

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -0,0 +1,451 @@ +; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O0 -global-isel=0 -fast-isel=0 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK-CPA-O0 +; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O3 -global-isel=0 -fast-isel=0 %s -o - 2>

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -10382,6 +10382,26 @@ let Predicates = [HasCPA] in { // Scalar multiply-add/subtract def MADDPT : MulAccumCPA<0, "maddpt">; def MSUBPT : MulAccumCPA<1, "msubpt">; + + // Rules to use CPA instructions in pointer arithmetic patterns which are not + // folded into loads

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

https://github.com/rgwott edited https://github.com/llvm/llvm-project/pull/105669 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

@@ -401,7 +401,7 @@ def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], def add: SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; -def ptradd : SDNode<"ISD::ADD" , SDTPtrAddOp, []>; +def

[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

rgwott wrote: @arichardson Yes, of course. It's just that this is low priority at work right now. I intend to come back to it in some days. https://github.com/llvm/llvm-project/pull/105669 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https: