================
@@ -401,7 +401,7 @@ def tblockaddress: SDNode<"ISD::TargetBlockAddress",
SDTPtrLeaf, [],
def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
[SDNPCommutative, SDNPAssociative]>;
-def ptradd : SDNode<"ISD::ADD" , SDTPtrAddOp, []>;
+def ptradd : SDNode<"ISD::PTRADD" , SDTPtrAddOp, []>;
----------------
rgwott wrote:
I investigated a bit about this AMDGPU occurrence. When building the compiler,
the tablegen will indeed compile to include a ptradd pattern to select a
certain instruction. However: (1) there are two consecutive entries, one for
add and one for ptradd, that do the same thing, so they are equivalent, and (2)
in compile time, the PTRADD node will never exist for that backend so the
tablegen entry will never be selected (the one for ADD will instead).
Thankfully this is not a problem.
https://github.com/llvm/llvm-project/pull/105669
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