rj-jesus wrote:
Chipping into the discussion, since this patch I can also no longer build
OpenBLAS or PETSc. OpenBLAS for example fails with
```
$ clang -v -O3 -mcpu=native -DHAVE_C11 -Wall -DF_INTERFACE_GFORT -fPIC
-DSMP_SERVER -DNO_WARMUP -DMAX_CPU_NUMBER=72 -DMAX_PARALLEL_NUMBER=1
-DMAX_ST
rj-jesus wrote:
> > Chipping into the discussion, since this patch I can also no longer build
> > OpenBLAS or PETSc. OpenBLAS for example fails with
> > ```
> > $ clang -v -O3 -mcpu=native -DHAVE_C11 -Wall -DF_INTERFACE_GFORT -fPIC
> > -DSMP_SERVER -DNO_WARMUP -DMAX_CPU_NUMBER=72 -DMAX_PARALLE
rj-jesus wrote:
> The solution is to add `-fno-fortran-main` to the linker options via
> `CMAKE_SHARED_LINKER_FLAGS`. This will need PR #74139 land first. But this
> option will be a good way to control if the flang compiler should attempt
> linking in the `main` stub from its library.
>
> It
rj-jesus wrote:
Sounds good, thanks! :)
https://github.com/llvm/llvm-project/pull/126945
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rj-jesus wrote:
Should this be given a more general name, now that it also includes Neon types?
There are also a few comments right at the start that could be extended for
Neon.
https://github.com/llvm/llvm-project/pull/126945
rj-jesus wrote:
I believe this fixes #113297, right?
https://github.com/llvm/llvm-project/pull/126945
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rj-jesus wrote:
Thank you very much for checking! If you have any other comments please let me
know.
https://github.com/llvm/llvm-project/pull/127837
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rj-jesus wrote:
Thanks for the pointer, @davemgreen. You're right, with `+strict-align` this
has to be 16B aligned.
This is also only valid for LE, but this should already be enforced.
https://github.com/llvm/llvm-project/pull/127837
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rj-jesus wrote:
Hi @paulwalker-arm, I think the alignment requirements of LD1 and LDR are
indeed different, but this only matters if `AlignmentEnforced()` is enabled,
right? I thought `AlignmentEnforced` wasn't generally a concern, otherwise even
the current lowering we have for `vld1q_u8(uint
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@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
+foreach Ty = [ nxv16i8
https://github.com/rj-jesus edited
https://github.com/llvm/llvm-project/pull/127837
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https://github.com/rj-jesus edited
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@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
+foreach Ty = [ nxv16i8
@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
rj-jesus w
rj-jesus wrote:
I'll commit this to get the bot back to green while I look into it offline.
https://github.com/llvm/llvm-project/pull/130263
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https://github.com/rj-jesus closed
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https://github.com/rj-jesus created
https://github.com/llvm/llvm-project/pull/130263
Reverts llvm/llvm-project#129732.
I'll look into what's causing the buildbot reported in
https://github.com/llvm/llvm-project/pull/129732#issuecomment-2705062636 to
fail offline.
>From 5a71fab0067bae0f532a62
https://github.com/rj-jesus closed
https://github.com/llvm/llvm-project/pull/129732
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https://github.com/rj-jesus edited
https://github.com/llvm/llvm-project/pull/130625
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https://github.com/rj-jesus created
https://github.com/llvm/llvm-project/pull/130625
This restores commit f01e760c08365426de95f02dc2c2dc670eb47352.
The original patch from #129732 exposed what seems to be a bug in
`SelectAddrModeIndexedSVE`.
Currently, the offset returned by `SelectAddrModeIn
https://github.com/rj-jesus updated
https://github.com/llvm/llvm-project/pull/130625
>From 03471cbf9270d1707191057de46dd38409c8a046 Mon Sep 17 00:00:00 2001
From: Ricardo Jesus
Date: Mon, 10 Mar 2025 01:57:20 -0700
Subject: [PATCH 1/4] Reapply "[AArch64][SVE] Improve fixed-length addressing
mo
rj-jesus wrote:
Hi @paulwalker-arm, thanks again for your suggestion. I think the only node
missing was `MemIntrinsicSDNode`, which seemingly was considered after
`isa(Root)` in the original code (although I'm not sure it was
reachable). I've moved it before the main `MemSDNode` path to avoid
https://github.com/rj-jesus updated
https://github.com/llvm/llvm-project/pull/129732
>From 624d1e924aa130eea2a8ddaefaeb587aab642f2f Mon Sep 17 00:00:00 2001
From: Ricardo Jesus
Date: Tue, 4 Mar 2025 02:36:06 -0800
Subject: [PATCH 1/5] Precommit tests
---
.../AArch64/sve-fixed-length-offsets.l
https://github.com/rj-jesus updated
https://github.com/llvm/llvm-project/pull/129732
>From 624d1e924aa130eea2a8ddaefaeb587aab642f2f Mon Sep 17 00:00:00 2001
From: Ricardo Jesus
Date: Tue, 4 Mar 2025 02:36:06 -0800
Subject: [PATCH 1/7] Precommit tests
---
.../AArch64/sve-fixed-length-offsets.l
https://github.com/rj-jesus updated
https://github.com/llvm/llvm-project/pull/129732
>From 624d1e924aa130eea2a8ddaefaeb587aab642f2f Mon Sep 17 00:00:00 2001
From: Ricardo Jesus
Date: Tue, 4 Mar 2025 02:36:06 -0800
Subject: [PATCH 1/4] Precommit tests
---
.../AArch64/sve-fixed-length-offsets.l
@@ -7380,17 +7380,31 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ std::optional MulImm;
+ if (VScale.getOpcode() == ISD::VSCALE) {
+MulImm
@@ -0,0 +1,362 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve
-aarch64-sve-vector-bits-min=128 -aarc
@@ -0,0 +1,362 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve
-aarch64-sve-vector-bits-min=128 -aarc
https://github.com/rj-jesus edited
https://github.com/llvm/llvm-project/pull/129732
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@@ -7380,17 +7380,31 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ std::optional MulImm;
+ if (VScale.getOpcode() == ISD::VSCALE) {
+MulImm
@@ -405,6 +405,17 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}
+ // Return the known bit length of SVE data registers. A value of 0 means the
+ // length is unkown beyond what's implied by the architecture.
+ uns
@@ -7380,12 +7380,26 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ int64_t MulImm = std::numeric_limits::max();
+ if (VScale.getOpcode() == ISD
https://github.com/rj-jesus edited
https://github.com/llvm/llvm-project/pull/129732
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@@ -405,6 +405,17 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}
+ // Return the known bit length of SVE data registers. A value of 0 means the
+ // length is unkown beyond what's implied by the architecture.
+ uns
https://github.com/rj-jesus edited
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@@ -7380,12 +7380,27 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ int64_t MulImm = std::numeric_limits::max();
+ if (VScale.getOpcode() == ISD
https://github.com/rj-jesus updated
https://github.com/llvm/llvm-project/pull/129732
>From 624d1e924aa130eea2a8ddaefaeb587aab642f2f Mon Sep 17 00:00:00 2001
From: Ricardo Jesus
Date: Tue, 4 Mar 2025 02:36:06 -0800
Subject: [PATCH 1/8] Precommit tests
---
.../AArch64/sve-fixed-length-offsets.l
rj-jesus wrote:
Thank you very much for the explanation, @paulwalker-arm - that makes a lot of
sense! I'll try your suggestion tomorrow. I'll let you know how it goes. :)
https://github.com/llvm/llvm-project/pull/130625
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rj-jesus wrote:
Hi, Olympus is the core in the NVIDIA Vera CPU announced at GTC.
https://github.com/llvm/llvm-project/pull/132368
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@@ -872,6 +883,16 @@ def ProcessorFeatures {
list Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2,
FeatureAES,
FeatureFullFP16, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM,
FeatureFPARMv8];
+ li
rj-jesus wrote:
Thanks very much :) Do you want me to wait for a review from @jthackray too
since you added him as a reviewer?
https://github.com/llvm/llvm-project/pull/132368
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rj-jesus wrote:
Thank you very much, and sorry, I didn't want to sound like I was rushing. I
just wasn't sure if I should wait or not, so I thought I'd check. I hope
everything goes well!
https://github.com/llvm/llvm-project/pull/132368
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https://github.com/rj-jesus created
https://github.com/llvm/llvm-project/pull/132368
This patch adds support for the NVIDIA Olympus core.
This does not add any special tuning decisions, and those may come later.
>From b9725e115876f26311edd408b9d4521ae8a03ebd Mon Sep 17 00:00:00 2001
From: Rica
https://github.com/rj-jesus closed
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@@ -288,6 +288,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef
ProcCpuinfoContent) {
if (Implementer == "0x4e") { // NVIDIA Corporation
return StringSwitch(Part)
.Case("0x004", "carmel")
+.Case("0x10", "olympus")
rj-jesus wrote
https://github.com/rj-jesus updated
https://github.com/llvm/llvm-project/pull/132368
>From b9725e115876f26311edd408b9d4521ae8a03ebd Mon Sep 17 00:00:00 2001
From: Ricardo Jesus
Date: Wed, 4 Dec 2024 05:42:38 -0800
Subject: [PATCH 1/2] [AArch64] Add initial support for -mcpu=olympus.
This patch
https://github.com/rj-jesus edited
https://github.com/llvm/llvm-project/pull/133054
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@@ -555,7 +555,8 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2",
"ARMProcFamily", "NeoverseV2
FeatureEnableSelectOptimize,
FeatureUseFixedOverScalableIfEqualCost,
@@ -19,6 +19,7 @@
// CHECK-NEXT: FEAT_ETE
Enable Embedded Trace Extension
// CHECK-NEXT: FEAT_FCMA
Enable Armv8.3-A Floating-point complex number support
// CHECK-NEXT: FEAT
https://github.com/rj-jesus approved this pull request.
Except for a seemingly out-of-order test, LGTM!
https://github.com/llvm/llvm-project/pull/133054
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@@ -1067,7 +1067,8 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8,
FeatureMatMulInt8,
FeatureSSBS, FeatureCCIDX,
FeatureJS, FeatureLSE, FeatureRAS,
Featur
@@ -19,6 +19,7 @@
// CHECK-NEXT: FEAT_ETE
Enable Embedded Trace Extension
// CHECK-NEXT: FEAT_FCMA
Enable Armv8.3-A Floating-point complex number support
// CHECK-NEXT: FEAT
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