https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/124511
>From 806ed62f5c856ad15e5290da3b3b84ddcf9083d3 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 27 Jan 2025 14:13:22 +0800
Subject: [PATCH 1/2] [X86][AVX10] Disable m[no-]avx10.1 and switch
m[no-]avx
phoebewang wrote:
> I've been playing around and found that `-mavx10.2 -mno-avx10.2-512` enables
> `avx10.1-512` but `-mavx10.2-512 -mno-avx10.2-512` obviously doesn't. Does it
> make sense? It happens because when options match, they are eliminated before
> processing. But this is a problem n
phoebewang wrote:
> > Let me know whether you are happy with this solution or not.
>
> Yes, thanks, I agree, this is better. Since we disable AVX10 version
> completely with any of options 256 or 512 (some kind of duplication), it
> means that we can't partially disable it, so these options do
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/124511
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/119238
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@@ -19,11 +19,45 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(128)))
+/// Constructs a 128-bit integer vector, setting the lower 32 bits to the
+///lower 32 bits of the parameter \a __A; the uppe
@@ -19,11 +19,45 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(128)))
+/// Constructs a 128-bit integer vector, setting the lower 32 bits to the
+///lower 32 bits of the parameter \a __A; the uppe
@@ -19,11 +19,45 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(128)))
+/// Constructs a 128-bit integer vector, setting the lower 32 bits to the
+///lower 32 bits of the parameter \a __A; the uppe
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/120061
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From d2bd70ca596987fc8ed0292e10c56fe1a98b1333 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 16 Dec 2024 17:48:41 +0800
Subject: [PATCH] [X86
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/120061
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https://github.com/phoebewang approved this pull request.
Well done!
https://github.com/llvm/llvm-project/pull/117091
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https://github.com/phoebewang approved this pull request.
LGTM.
Note, `prefer-256-bit` just prefers. If you want to 256-bit guaranteed, you
need `no-evex512`.
https://github.com/llvm/llvm-project/pull/117092
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phoebewang wrote:
> > > @phoebewang and @lvwr I also noticed that there is this code in LLVM:
> > > https://github.com/llvm/llvm-project/blob/9ba6672b9f0e82a1f6d4100dc832c84447ea545c/llvm/lib/Transforms/Utils/ModuleUtils.cpp#L202-L214
> > >
> > > . As far as I can tell, this code is not triggere
@@ -208,10 +209,34 @@ void llvm::setKCFIType(Module &M, Function &F, StringRef
MangledType) {
std::string Type = MangledType.str();
if (M.getModuleFlag("cfi-normalize-integers"))
Type += ".normalized";
+
+ uint32_t OutHash = static_cast(llvm::xxHash64(Type));
+ auto
@@ -208,10 +209,34 @@ void llvm::setKCFIType(Module &M, Function &F, StringRef
MangledType) {
std::string Type = MangledType.str();
if (M.getModuleFlag("cfi-normalize-integers"))
Type += ".normalized";
+
+ uint32_t OutHash = static_cast(llvm::xxHash64(Type));
+ auto
phoebewang wrote:
> > > Second, this scheme reduces the expected number of hash collisions within
> > > each arity, compared against the expected number of collisions
> > > (0.01383765) for the 32-bit hashing scheme that includes all arities. The
> > > table below shows the expected number of
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/120927
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/120927
>From 608ce20a7b3b8fdd7b65c7afc8f2de7ad271369c Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 23 Dec 2024 09:05:06 +0800
Subject: [PATCH] [X86][AVX10.2] Fix wrong mask bits in cvtpbf8_ph intrinsics
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/120927
>From 2b9cde28c2093556d006b5ff0103137f52a7a751 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 23 Dec 2024 09:05:06 +0800
Subject: [PATCH] [X86][AVX10.2] Fix wrong mask bits in cvtpbf8_ph intrinsics
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_P
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_P
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/120927
Found during review #120766
>From 13176bdf116f54aee7ffed4b22cace39776c6515 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 23 Dec 2024 09:05:06 +0800
Subject: [PATCH] [X86][AVX10.2] Fix wrong mask b
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
@@ -24,567 +24,3243 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements t
phoebewang wrote:
We cannot let clang-format to format it. Maybe use `clang-format off` to turn
it off.
https://github.com/llvm/llvm-project/pull/120766
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@@ -245,6 +245,7 @@ class LangOptionsBase {
/// construction vtable because it hasn't added 'type' as a substitution.
/// - Skip mangling enclosing class templates of member-like friend
/// function templates.
+/// - Incorrectly return C++ records in AVX
phoebewang wrote:
> A long way from an expert on OpenCL, but it seems to not even have the
> concept of `long long`, and `long` is defined as a 64-bit type (and just
> optional for embedded stuff)?
>
> https://registry.khronos.org/OpenCL/sdk/3.0/docs/man/html/scalarDataTypes.html
Thanks for t
https://github.com/phoebewang approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/122204
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@@ -203,180 +203,180 @@ __m128i test_mm256_maskz_cvtbiassph_phf8(__mmask16 __U,
__m256i __A, __m256h __B
return _mm256_maskz_cvtbiassph_phf8(__U, __A, __B);
}
-__m128i test_mm_cvtne2ph_pbf8(__m128h __A, __m128h __B) {
- // CHECK-LABEL: @test_mm_cvtne2ph_pbf8(
- // CHECK:
@@ -231,75 +231,71 @@ _mm512_maskz_cvtnehf8_ph(__mmask32 __U, __m256i __A) {
(__v32qi)__A, (__v32hf)(__m512h)_mm512_setzero_ph(), (__mmask32)__U);
}
-static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_cvtneph_pbf8(__m512h __A) {
- return (__m256i)__builtin_ia32_vcv
phoebewang wrote:
> > > @RKSimon do you know if there is a reason CodeGen AA is not enabled for
> > > x86?
> > > I'd otherwise be happy to approve this patch, lowering to the intrinsic
> > > seems like the right thing to do.
> >
> >
> > I don't remember any reason for alias analysis to not be
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/123272
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@@ -603,13 +603,13 @@ defm VCVTPS2IUBS : avx10_sat_cvt_base<0x6b,
"vcvtps2iubs", SchedWriteVecIMul,
X86vcvtp2iubsRnd>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
-defm VCVTTNEBF162IBS : avx10_sat_cvt_base<0x68, "vcvttn
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/123275
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@@ -5385,120 +5385,120 @@ let Features = "avx10.2-256", Attributes = [NoThrow,
Const, RequiredVectorWidth<
}
let Features = "avx10.2-512", Attributes = [NoThrow, Const,
RequiredVectorWidth<512>] in {
- def vcmppbf16512_mask : X86Builtin<"unsigned int(_Vector<32, __bf16>,
_
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/123656
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/123656
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/123307
>From e2ae76e265178880db7f1ea7c2c67b79ebbd1761 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 17 Jan 2025 17:07:26 +0800
Subject: [PATCH 1/2] [X86][AVX10.2-BF16] Update VCOMISBF16 intrinsics and
in
@@ -5376,12 +5376,12 @@ let Features = "avx10.2-512", Attributes = [NoThrow,
Const, RequiredVectorWidth<
}
let Features = "avx10.2-256", Attributes = [NoThrow, Const,
RequiredVectorWidth<128>] in {
- def vcomsbf16eq : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)"
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/123335
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/123307
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phoebewang wrote:
> > We also change -mno-avx10.[1,2]-512 to alias of 256 bit options to disable
> > both 256 and 512 instructions.
>
> Why this?
Because we expect m[no-]avx10.2 cover both 256 and 512 bit instructions.
https://github.com/llvm/llvm-project/pull/124511
_
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/124511
>From 7c56c51bb4d5982606ca9e2bcaac0651d59e5873 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 27 Jan 2025 14:13:22 +0800
Subject: [PATCH 1/2] [X86][AVX10] Disable m[no-]avx10.1 and switch
m[no-]avx
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/124511
>From 806ed62f5c856ad15e5290da3b3b84ddcf9083d3 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 27 Jan 2025 14:13:22 +0800
Subject: [PATCH] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/124511
Per the feedback we got, we’d like to switch m[no-]avx10.2 to alias of 512 bit
options and disable m[no-]avx10.1 due to they were alias of 256 bit options.
We also change -mno-avx10.[1,2]-512 to alias of 256
@@ -221,73 +221,73 @@ __m512h test_mm512_maskz_cvtnehf8_ph(__mmask32 __A,
__m256i __B) {
__m256i test_mm512_cvtneph_pbf8(__m512h __A) {
// CHECK-LABEL: @test_mm512_cvtneph_pbf8(
- // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2bf8512(
+ // CHECK: call <32 x i8> @l
@@ -115,87 +115,87 @@ __m256i test_mm512_maskz_cvtbiassph_phf8(__mmask32 __U,
__m512i __A, __m512h __B
__m512i test_mm512_cvtne2ph_pbf8(__m512h __A, __m512h __B) {
phoebewang wrote:
Why the test cases are still using `ne` and `p`. The same below.
https://git
@@ -420,143 +416,139 @@ _mm256_maskz_cvtnehf8_ph(__mmask16 __U, __m128i __A) {
(__v16qi)__A, (__v16hf)(__m256h)_mm256_setzero_ph(), (__mmask16)__U);
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_pbf8(__m128h __A) {
- return (__m128i)__builtin_ia32_vcvtn
@@ -205,175 +205,175 @@ __m128i test_mm256_maskz_cvtbiassph_phf8(__mmask16 __U,
__m256i __A, __m256h __B
__m128i test_mm_cvtne2ph_pbf8(__m128h __A, __m128h __B) {
phoebewang wrote:
Why the test cases are still using ne and p. The same below.
https://github.c
@@ -203,180 +203,180 @@ __m128i test_mm256_maskz_cvtbiassph_phf8(__mmask16 __U,
__m256i __A, __m256h __B
return _mm256_maskz_cvtbiassph_phf8(__U, __A, __B);
phoebewang wrote:
ditto.
https://github.com/llvm/llvm-project/pull/123656
___
@@ -113,92 +113,92 @@ __m256i test_mm512_maskz_cvtbiassph_phf8(__mmask32 __U,
__m512i __A, __m512h __B
return _mm512_maskz_cvtbiassph_phf8(__U, __A, __B);
}
phoebewang wrote:
The tests above are still using `p`.
https://github.com/llvm/llvm-project/pull/123
https://github.com/phoebewang approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/98426
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phoebewang wrote:
@DanShaders let me know if you need me to merge it for you.
https://github.com/llvm/llvm-project/pull/98426
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https://github.com/phoebewang closed
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@@ -0,0 +1,485 @@
+//===--- BuiltinsX86_64.td - X86-64 Builtin function database ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
phoebewang wrote:
I don't see any removal in BuiltinsX86_64.def. Is it intended?
https://github.com/llvm/llvm-project/pull/121043
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@@ -0,0 +1,485 @@
+//===--- BuiltinsX86_64.td - X86-64 Builtin function database ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,485 @@
+//===--- BuiltinsX86_64.td - X86-64 Builtin function database ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,485 @@
+//===--- BuiltinsX86_64.td - X86-64 Builtin function database ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/phoebewang approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/121043
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@@ -108,9 +109,15 @@ class PrototypeParser {
} else if (T.consume_back("&")) {
ParseType(T);
Type += "&";
+} else if (T.consume_front("long long")) {
phoebewang wrote:
Thanks for the information!
https://github.com/llvm/llvm-project/pull/1
phoebewang wrote:
> So, my preference is to keep this as is, and allow folks familiar with the
> specific builtins to merge groups together that make logical sense in
> follow-up PRs. Would that work for folks to at least get us out from using
> the X-macros?
Agreed! Can you share the script
@@ -108,9 +109,15 @@ class PrototypeParser {
} else if (T.consume_back("&")) {
ParseType(T);
Type += "&";
+} else if (T.consume_front("long long")) {
phoebewang wrote:
How did you get this diff? I think it's useful for us to verify the corr
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/120831
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=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?=
Message-ID:
In-Reply-To:
@@ -24,573 +24,3369 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"),
\
__min_vector_width_
@@ -181,8 +181,26 @@ void X86AsmPrinter::emitKCFITypeId(const MachineFunction
&MF) {
// Embed the type hash in the X86::MOV32ri instruction to avoid special
// casing object file parsers.
EmitKCFITypePadding(MF);
+
+ Register MovReg = X86::EAX;
+ const auto &Triple = M
phoebewang wrote:
And you cannot use ESI when it's used to pass arguments. Suggested registers:
| Arity Indicator | Description | Encoding in reg field |
| --- | --- | --- |
| 0 | 0 parameters | EDI |
| 1 | 1 parameter in RDI | ESI |
| 2 | 2 parameters in RDI a
@@ -181,8 +181,26 @@ void X86AsmPrinter::emitKCFITypeId(const MachineFunction
&MF) {
// Embed the type hash in the X86::MOV32ri instruction to avoid special
// casing object file parsers.
EmitKCFITypePadding(MF);
+
+ Register MovReg = X86::EAX;
+ const auto &Triple = M
phoebewang wrote:
> * Systematically using `Oi` instead of `LLi` for the type `long long int`.
> The `.def` file uses a mixture of `Oi` and `LLi`. I chose the shorter
> encoding.
The mixture use of `Oi` and `LLi` is a mess, but `Oi` has different meaning for
OpenCL targets. I think we should
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_P
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_P
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_Piróg?= ,
=?utf-8?q?Mikołaj_P
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/122238
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/123270
>From ebab1ea66e400f84eb0dca846187ea5a365d1c14 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 17 Jan 2025 10:06:13 +0800
Subject: [PATCH] [X86][AMX-AVX512][NFC] Remove P from intrinsic and
instruct
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/123270
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/123272
>From 97cb1e826ab9f454b07406a0373ca2ebd6532cb0 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 17 Jan 2025 10:20:59 +0800
Subject: [PATCH] [X86][AVX10.2-MINMAX][NFC] Remove NE[P] from intrinsic and
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/123307
- Add `I` to intrinsics and instructions
- Add `_` before sbf16 in intrinsics
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
>From e2ae76e265178880db7f1ea7c2c67b79ebbd1761 Mon Sep 17 00:00:00 2001
Fr
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/122238
According to MSVC, __readcr4/__writecr4 return/use `unsigned __int64`, and are
supported on both x86 and x64. While __readcr8/__writecr8 are only supported on
x64. So we use __INTPTR_TYPE__ and __int64 respe
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/123270
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
>From 6e6058e71a13de67e4c5b78258448629b3f8b0ba Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 17 Jan 2025 10:06:13 +0800
Subject: [PATCH] [X86
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/123272
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
>From 6a17e1af6ca33ebe97cc6c66dd2dee6d3619ae72 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 17 Jan 2025 10:20:59 +0800
Subject: [PATCH] [X86
phoebewang wrote:
> ⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️
>
> You can test this locally with the following command:
> View the diff from clang-format here.
> ```diff
> diff --git a/clang/lib/Headers/avx10_2convertintrin.h
> b/clang/lib/Headers/avx10_2convertintrin.
https://github.com/phoebewang approved this pull request.
Good catch!
https://github.com/llvm/llvm-project/pull/126390
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phoebewang wrote:
Please update test in clang\test\Headers\cpuid.c
https://github.com/llvm/llvm-project/pull/127331
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/127331
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/127385
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/127385
Address the X86 part of #126491
>From 80e85d3a44657df64fd9136156d36b096003b58e Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sun, 16 Feb 2025 18:17:39 +0800
Subject: [PATCH] [X86] Add missing explicit
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/128284
Similar to D14748, we can relax lzcnt intrinsics too, especially with improved
BSR lowering by #123623
>From eef9ec3ca38a2ba1dd12c8a8f8bfcacf38ab7926 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat,
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