[PATCH] D22221: Decide whether to enable plugin tests based on cmake variables

reames resigned from this revision. reames removed a reviewer: reames. reames added a comment. I know very little about our cmake infrastructure. Repository: rL LLVM https://reviews.llvm.org/D1 ___ cfe-commits mailing list cfe-commits@lists.l

[clang] a4a2943 - [RISCV][MC] Add minimal support for Ztso extension

Author: Philip Reames Date: 2022-09-07T09:30:57-07:00 New Revision: a4a29438f451370ed241dde30bfcaab0fdf2ab71 URL: https://github.com/llvm/llvm-project/commit/a4a29438f451370ed241dde30bfcaab0fdf2ab71 DIFF: https://github.com/llvm/llvm-project/commit/a4a29438f451370ed241dde30bfcaab0fdf2ab71.diff

[clang] a93cacf - [clang driver] Remove a bit of redundant flang specific code [nfc]

Author: Philip Reames Date: 2023-12-06T14:20:36-08:00 New Revision: a93cacf9b08f0780f2ae2832da10a9a841ae7d03 URL: https://github.com/llvm/llvm-project/commit/a93cacf9b08f0780f2ae2832da10a9a841ae7d03 DIFF: https://github.com/llvm/llvm-project/commit/a93cacf9b08f0780f2ae2832da10a9a841ae7d03.diff

[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)

https://github.com/preames created https://github.com/llvm/llvm-project/pull/74770 The previous code was always auto-completing options for the clang mode. We'd special cases flang to allow both clang and flang options, but this doesn't match either the help output or the actual argument pars

[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)

https://github.com/preames created https://github.com/llvm/llvm-project/pull/74889 d80e46d added support for the target function attribute. However, it turns out that commit has a nasty bug/oversight. As the tests in that revision show, everything works if clang -cc1 is directly invoked. I

[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)

preames wrote: > Related question. If there is an -mcpu on the command line and target > attribute changes the march, do we keep the original CPU in the -target-cpu > attribute or drop it. The reason for all those negative features from the > driver was to make the backend not infer any featur

[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)

https://github.com/preames closed https://github.com/llvm/llvm-project/pull/74889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Reduce the size of the index used for RVV intrinsics. NFC (PR #74906)

https://github.com/preames approved this pull request. LGTM - though maybe use uint32_t? Looking at this code, the whole Intrinsics map vs OverloadIntrinsic map structure loops to have heavy redundancy and could be greatly simplified. Maybe a follow up? https://github.com/llvm/llvm-project/p

[clang] [RISCV] Reduce the size of the index used for RVV intrinsics. NFC (PR #74906)

preames wrote: > > LGTM - though maybe use uint32_t? > > Looking at this code, the whole Intrinsics map vs OverloadIntrinsic map > > structure loops to have heavy redundancy and could be greatly simplified. > > Maybe a follow up? > > Did you have a specific idea in mind? Maybe we could use a s

[clang] [clang-tools-extra] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

@@ -31259,14 +31274,23 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG, if (!IsSeqCst && IsTypeLegal) return Op; - if (VT == MVT::i64 && !IsTypeLegal) { + if (!IsTypeLegal && !Subtarget.useSoftFloat() && + !DAG.getMachineFunction().getFunction()

[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

@@ -31259,14 +31274,23 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG, if (!IsSeqCst && IsTypeLegal) return Op; - if (VT == MVT::i64 && !IsTypeLegal) { + if (!IsTypeLegal && !Subtarget.useSoftFloat() && + !DAG.getMachineFunction().getFunction()

[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

@@ -30115,12 +30126,16 @@ X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { // If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we // can use movq to do the load. If we have X87 we can load into an 80-bit // X87 register and store it

[llvm] [clang-tools-extra] [clang] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

@@ -30095,12 +30102,16 @@ TargetLoweringBase::AtomicExpansionKind X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { Type *MemType = SI->getValueOperand()->getType(); - bool NoImplicitFloatOps = - SI->getFunction()->hasFnAttribute(Attribute::NoImplic

[llvm] [clang] [clang-tools-extra] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)

@@ -228,87 +228,86 @@ define void @widen_broadcast_unaligned(ptr %p0, i32 %v) { } define i128 @load_i128(ptr %ptr) { -; CHECK-O0-LABEL: load_i128: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT:pushq %rbx -; CHECK-O0-NEXT:.cfi_def_cfa_offset 16 -; CHECK-O0-NEXT:.cfi_

[clang] 0b7dda3 - Revert "[flang][nfc] Refactor linker invocation logic (#75534)"

Author: Philip Reames Date: 2023-12-15T11:08:09-08:00 New Revision: 0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896 URL: https://github.com/llvm/llvm-project/commit/0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896 DIFF: https://github.com/llvm/llvm-project/commit/0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896.diff

[llvm] [clang] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)

https://github.com/preames created https://github.com/llvm/llvm-project/pull/73971 When we'd originally added unaligned-scalar-mem and unaligned-vector-mem, they were separated into two parts under the theory that some processor might implement one, but not the other. At the moment, we don't

[clang] [llvm] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)

@@ -174,15 +174,10 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, bool HasV = llvm::is_contained(Features, "+zve32x"); preames wrote: Yep, change pending. https://github.com/llvm/llvm-project/pull/73971 ___

[clang] [llvm] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)

https://github.com/preames updated https://github.com/llvm/llvm-project/pull/73971 >From 2f746ba1857d0d9f3dc20bbde499f2340735b05e Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Thu, 30 Nov 2023 10:34:22 -0800 Subject: [PATCH 1/2] [RISCV] Collapse fast unaligned access into a single feature

[llvm] [clang] [RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (PR #73971)

https://github.com/preames closed https://github.com/llvm/llvm-project/pull/73971 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[flang] [clang] [Flang] Support -mrvv-vector-bits flag (PR #77588)

https://github.com/preames approved this pull request. LGTM We should explore options for merging the option processing code for options supported by both clang and flang, but that's explicitly future work. https://github.com/llvm/llvm-project/pull/77588 _

[clang] [llvm] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)

https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77645 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

@@ -96,6 +96,8 @@ on support follow. ``Svnapot`` Assembly Support ``Svpbmt`` Supported ``V``Supported + ``Za128rs`` Supported preames wrote: I think these may warrant an explanatory note after the table. See what

[clang] [Clang][doc] Add blank line before lists (PR #77573)

https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77573 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 13ccaf9 - Revert "Reapply "[analyzer] Accept C library functions from the `std` namespace""

Author: Philip Reames Date: 2024-03-13T10:19:42-07:00 New Revision: 13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c URL: https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c DIFF: https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c.diff

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -36,6 +36,11 @@ struct RISCVSupportedExtension { } }; +struct RISCVProfile { preames wrote: Very minor, but I believe you can use std::pair here instead. https://github.com/llvm/llvm-project/pull/76357 ___ c

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/preames commented: After this was discussed at the sync-up call today, I believe we're in agreement on direction here. This is close to being ready and is just pending some code cleanup. https://github.com/llvm/llvm-project/pull/76357 _

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || preames wrote: You do

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, "string must be lowercase"); } + bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") || + Arch.starts_with("r

[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)

preames wrote: I agree with @asb's framing above. Assuming this doesn't commit us to something which is hard to forward version for some reason, I support addressing this in a target specific manner for the moment. https://github.com/llvm/llvm-project/pull/80760 _

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

https://github.com/preames updated https://github.com/llvm/llvm-project/pull/79911 >From 3344e42d05875269b680b9626cd6cd093e88d81e Mon Sep 17 00:00:00 2001 From: brs Date: Thu, 19 Oct 2023 17:16:45 -0500 Subject: [PATCH 1/2] [RISCV][MC] MC layer support for the experimental zalasr extension --

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

preames wrote: I think we need some kind of official documentation to merge this. I went looking to see if I could find mention of this extension in e.g. ARC notes, and didn't find it. @mehnadnerd can you provide some kind of link or reference to some RVI source indicating the status of this

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

https://github.com/preames approved this pull request. LGTM w/comments addressed. https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", +

[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", +

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

preames wrote: > It has been approved to be pursued as a fast track extension > (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698). > It has not yet been approved by the chairs. Works for me. I've edited the PR description to include this information so tha

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

https://github.com/preames closed https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", +

[lldb] [compiler-rt] [clang-tools-extra] [llvm] [flang] [clang] [libcxx] [libc] [lld] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp)) { +unsigned TpRegs = getRegUsageForType(Tp); +unsigned NumElems = +

[clang-tools-extra] [clang] [libcxx] [compiler-rt] [lldb] [llvm] [flang] [lld] [libc] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp)) { +unsigned TpRegs = getRegUsageForType(Tp); +unsigned NumElems = +

[compiler-rt] [llvm] [clang-tools-extra] [lld] [clang] [libc] [libcxx] [lldb] [flang] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp)) { +unsigned TpRegs = getRegUsageForType(Tp); +unsigned NumElems = +

[libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)

preames wrote: FYI - https://github.com/llvm/llvm-project/pull/80360 adds testing infrastructure to exercise the TTI hooks. https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)

@@ -7,7 +7,7 @@ define i32 @test(ptr noalias %p, ptr noalias %addr) { ; CHECK-NEXT: entry: ; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[ADDR:%.*]], i32 0 ; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr> poison, <8 x i32> ze

[mlir] [clang] [libc] [lldb] [lld] [openmp] [flang] [libcxx] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[flang] [clang] [openmp] [mlir] [libc] [lldb] [lld] [clang-tools-extra] [llvm] [libcxx] [SLP]Add support for strided loads. (PR #80310)

@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef VL, const Value *VL0, std::optional Diff = getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE); // Check that the sorted loads are consecutive. - if (static_cast(*Diff) == VL.si

[flang] [libc] [mlir] [libcxx] [lldb] [lld] [clang] [openmp] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)

@@ -397,27 +241,12 @@ define void @test3([48 x float]* %p, float* noalias %s) { ; CHECK-NEXT: entry: ; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [48 x float], ptr [[P:%.*]], i64 0, i64 0 ; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[

[clang] [libc] [lld] [llvm] [lldb] [libcxx] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -17,7 +17,7 @@ define i16 @test() { ; CHECK-NEXT:[[TMP4:%.*]] = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> [[TMP3]], i32 2, <2 x i1> , <2 x i16> poison) ; CHECK-NEXT:[[TMP5:%.*]] = extractelement <2 x i16> [[TMP4]], i32 0 ; CHECK-NEXT:[[TMP6:%.*]] =

[flang] [libcxx] [lldb] [lld] [mlir] [clang-tools-extra] [libc] [openmp] [llvm] [clang] [SLP]Add support for strided loads. (PR #80310)

@@ -30,7 +30,7 @@ define void @test() { ; CHECK-SLP-THRESHOLD: bb: ; CHECK-SLP-THRESHOLD-NEXT:[[TMP0:%.*]] = insertelement <4 x ptr> poison, ptr [[COND_IN_V]], i32 0 ; CHECK-SLP-THRESHOLD-NEXT:[[TMP1:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <4

[libcxx] [flang] [mlir] [openmp] [llvm] [clang] [clang-tools-extra] [lldb] [lld] [libc] [SLP]Add support for strided loads. (PR #80310)

https://github.com/preames commented: These comments are trying to be helpful in pointing out bits which might be simplified or split off, but my track record with SLP reviews is not great. Feel free to ignore any or all of these. https://github.com/llvm/llvm-project/pull/80310

[openmp] [clang-tools-extra] [libcxx] [lld] [flang] [clang] [llvm] [lldb] [mlir] [libc] [SLP]Add support for strided loads. (PR #80310)

@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef VL, const Value *VL0, std::optional Diff = getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE); // Check that the sorted loads are consecutive. - if (static_cast(*Diff) == VL.si

[libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -3878,6 +3883,130 @@ static Align computeCommonAlignment(ArrayRef VL) { return CommonAlignment; } +/// Check if \p Order represents reverse order. +static bool isReverseOrder(ArrayRef Order) { + unsigned Sz = Order.size(); + return !Order.empty() && all_of(enumerate(Or

[clang] [llvm] [RISCV] Graduate Zicond to non-experimental (PR #79811)

https://github.com/preames approved this pull request. LGTM as well. https://github.com/llvm/llvm-project/pull/79811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)

https://github.com/preames closed https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)

preames wrote: Not actively working on this. Anyone interested is welcome to pick up the patch. https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/

[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

preames wrote: Can you separate out the basic processor definition (using NoSchedModel), and a patch which adds the scheduling model? We can at least get the processor definition landed while we iterate on the scheduling related pieces. https://github.com/llvm/llvm-project/pull/70232 __

[clang] 3b3eb7f - Speculative fix for build bot failures

Author: Philip Reames Date: 2020-12-14T13:44:40-08:00 New Revision: 3b3eb7f07ff97feb64a1975587bb473f1f3efa6b URL: https://github.com/llvm/llvm-project/commit/3b3eb7f07ff97feb64a1975587bb473f1f3efa6b DIFF: https://github.com/llvm/llvm-project/commit/3b3eb7f07ff97feb64a1975587bb473f1f3efa6b.diff

[clang] 740057d - [funcattrs] Infer writeonly argument attribute

Author: Philip Reames Date: 2021-12-02T13:04:09-08:00 New Revision: 740057d185ea0e8b5a4f8b7c78fdf38ae7a66f76 URL: https://github.com/llvm/llvm-project/commit/740057d185ea0e8b5a4f8b7c78fdf38ae7a66f76 DIFF: https://github.com/llvm/llvm-project/commit/740057d185ea0e8b5a4f8b7c78fdf38ae7a66f76.diff

[clang] 7b54de5 - [funcattrs] Fix a bug in recently introduced writeonly argument inference

Author: Philip Reames Date: 2021-12-03T08:57:15-08:00 New Revision: 7b54de5feffedfc08e5a02d6c9e27c54e3b7f119 URL: https://github.com/llvm/llvm-project/commit/7b54de5feffedfc08e5a02d6c9e27c54e3b7f119 DIFF: https://github.com/llvm/llvm-project/commit/7b54de5feffedfc08e5a02d6c9e27c54e3b7f119.diff

[clang] 9a8f3b1 - [clang][RISCV] Set vscale_range attribute based on VLEN

Author: Philip Reames Date: 2022-10-19T16:14:33-07:00 New Revision: 9a8f3b113d05d94d9aaacdf511365dde4e35ce4f URL: https://github.com/llvm/llvm-project/commit/9a8f3b113d05d94d9aaacdf511365dde4e35ce4f DIFF: https://github.com/llvm/llvm-project/commit/9a8f3b113d05d94d9aaacdf511365dde4e35ce4f.diff

[clang] eda2af5 - [RISCV][MC] Add support for experimental Zawrs extension

Author: Philip Reames Date: 2022-09-20T10:15:11-07:00 New Revision: eda2af575fdf038f3508112b42845516e7cb6192 URL: https://github.com/llvm/llvm-project/commit/eda2af575fdf038f3508112b42845516e7cb6192 DIFF: https://github.com/llvm/llvm-project/commit/eda2af575fdf038f3508112b42845516e7cb6192.diff

[clang] 4467c78 - [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

Author: Philip Reames Date: 2022-10-17T11:33:03-07:00 New Revision: 4467c781d7bbf25a3b89a25ccbc0382731f51322 URL: https://github.com/llvm/llvm-project/commit/4467c781d7bbf25a3b89a25ccbc0382731f51322 DIFF: https://github.com/llvm/llvm-project/commit/4467c781d7bbf25a3b89a25ccbc0382731f51322.diff

[clang] 780c539 - [RISCV] Implement assembler support for XVentanaCondOps

Author: Philip Reames Date: 2022-11-14T09:01:54-08:00 New Revision: 780c53984449e14f50e2418de993bbf560f54bfc URL: https://github.com/llvm/llvm-project/commit/780c53984449e14f50e2418de993bbf560f54bfc DIFF: https://github.com/llvm/llvm-project/commit/780c53984449e14f50e2418de993bbf560f54bfc.diff

[clang] 22e199e - [RISCV] Accept zicsr and zifencei command line options

Author: Philip Reames Date: 2023-02-16T10:41:41-08:00 New Revision: 22e199e6afb1263c943c0c0d4498694e15bf8a16 URL: https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16 DIFF: https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16.diff

[clang] 495b653 - [RISCV] Add missing plumbing and tests for zfa

Author: Philip Reames Date: 2023-02-17T17:56:30-08:00 New Revision: 495b653480238d692d814dde50469441b83adb4b URL: https://github.com/llvm/llvm-project/commit/495b653480238d692d814dde50469441b83adb4b DIFF: https://github.com/llvm/llvm-project/commit/495b653480238d692d814dde50469441b83adb4b.diff

Re: [PATCH] D21385: Adjust Registry interface to not require plugins to export a registry

reames added a comment. This seems to have landed a couple of days ago without problem, but if anyone sees any weird effects in shared builds for Linux, this change is probably the culprit. The last time I tried to do something like this, I had to back out my change due to linker errors I neve

Re: [PATCH] D16963: Copy LibASTMatchersReference.html to gen'd docs

reames added a comment. This looks entirely reasonable to me, but I don't really know cmake. Can someone with cmake knowledge take a quick look? http://reviews.llvm.org/D16963 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.ll

Re: [PATCH] D15998: Implement __attribute__((gc_leaf_function)).

reames added a comment. Neither Sanjoy or I are qualified to review a clang patch. You'll need to find clang reviewers. Also, before this gets exposed through Clang, we really should formalize/document the attribute. In practice, it implies the lack of a safepoint poll site inside the calle

[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

@@ -290,8 +290,24 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args, // 2. Get march (isa string) based on `-mcpu=` if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) { StringRef CPU = A->getValue(); -if (CPU == "native") +if (CPU == "nativ

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

https://github.com/preames requested changes to this pull request. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

preames wrote: > Will this core have active support on the LLVM side? I can't speak for the vendor, but I'll say that I'm interested in having this supported upstream. This looks to be a reasonable rva22 dev board w/V1.0, and having in tree support seems worthwhile. I've ordered one of these

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", FeatureStdExtC], [TuneNoDefaultUnroll]>; +def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacor

[clang] [lld] [llvm] [RISCV] Make M imply Zmmul (PR #95070)

preames wrote: Given the concern about breaking configurations w/no-integrated-as and older binutils, can someone summarize here which versions of binutils are known to work/not work after this change? This will likely become the key search result for such breakage, and having it well documen

[clang] [llvm] [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #88954)

https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88954 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Don't enable -mrelax-all for -O0 on RISC-V (PR #88538)

https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88538 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)

https://github.com/preames closed https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)

preames wrote: I've gone ahead and merged this into main. We have missed the branch creation, so without further action this will not be included in 19.x. We need to ensure the constructor change for compiler-rt lands, and then backport them together if we choose to. https://github.com/ll

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

preames wrote: @BeMg Can you rebase over commit [d1e28e2](https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59)? https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org ht

[clang] [llvm] [RISCV] Add capital letters to T-Head extension names in descriptions. (PR #99070)

https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/99070 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -14266,6 +14277,71 @@ CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) { return Result; } +Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs, + unsigned &MaxGroupIDUsed) { + + const unsigned Feat

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -14266,6 +14277,71 @@ CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) { return Result; } +Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs, + unsigned &MaxGroupIDUsed) { + + const unsigned Feat

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

https://github.com/preames edited https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -119,6 +119,51 @@ void getFeaturesForCPU(StringRef CPU, else EnabledFeatures.push_back(F.substr(1)); } + +namespace RISCVExtensionBitmaskTable { +#define GET_RISCVExtensionBitmaskTable_IMPL +#include "llvm/TargetParser/RISCVTargetParserDef.inc" + +} // namespace RI

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -14266,6 +14277,71 @@ CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) { return Result; } +Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs, + unsigned &MaxGroupIDUsed) { + + const unsigned Feat

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver( case llvm::Triple::aarch64: EmitAArch64MultiVersionResolver(Resolver, Options); return; + case llvm::Triple::riscv32: + case llvm::Triple::riscv64: +EmitRISCVMultiVersionResolver(Resolver,

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver( case llvm::Triple::aarch64: EmitAArch64MultiVersionResolver(Resolver, Options); return; + case llvm::Triple::riscv32: + case llvm::Triple::riscv64: +EmitRISCVMultiVersionResolver(Resolver,

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo { CharUnits Field2Off) const; ABIArgInfo coerceVLSVector(QualType Ty) const; + + using ABIInfo::appendAttributeMangling; + void appendAttributeMangling(TargetClones

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver( case llvm::Triple::aarch64: EmitAArch64MultiVersionResolver(Resolver, Options); return; + case llvm::Triple::riscv32: + case llvm::Triple::riscv64: +EmitRISCVMultiVersionResolver(Resolver,

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver( case llvm::Triple::aarch64: EmitAArch64MultiVersionResolver(Resolver, Options); return; + case llvm::Triple::riscv32: + case llvm::Triple::riscv64: +EmitRISCVMultiVersionResolver(Resolver,

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

https://github.com/preames requested changes to this pull request. At a high level, I think this is a quite a ways from being ready to land. There's both code style issues (mostly false generality), and missing bits of the user interface on the clang side. I do not think this has any real ser

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