olista01 added inline comments.
Comment at: test/Driver/aarch64-cpus.c:10
+// GENERIC: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-cpu" "generic"
+// GENERIC-LE: "-cc1"{{.*}} "-triple" "aarch64--"{{.*}} "-target-cpu" "generic"
Why do these need new check pr
olista01 added inline comments.
Comment at: test/Driver/aarch64-cpus.c:10
+// GENERIC: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-cpu" "generic"
+// GENERIC-LE: "-cc1"{{.*}} "-triple" "aarch64--"{{.*}} "-target-cpu" "generic"
SjoerdMeijer wrote:
> olista01
olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM, thanks!
https://reviews.llvm.org/D50175
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olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM, thanks!
https://reviews.llvm.org/D49793
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olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM.
https://reviews.llvm.org/D38452
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This revision was automatically updated to reflect the committed changes.
Closed by commit rC342126: [AArch64] Enable return address signing for static
ctors (authored by olista01, committed by ).
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Repository:
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https://reviews.llvm.org/D51418
Fil
olista01 added a comment.
This looks like it has the same problem as https://reviews.llvm.org/D51418
(doesn't get applied to C++ static constructor functions).
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olista01 added inline comments.
Comment at: src/DwarfInstructions.hpp:210
+register unsigned long long x16 __asm("x16") = cfa;
+asm("autia1716": "+r"(x17): "r"(x16));
+returnAddress = x17;
I don't think this will work for cross-unwinding b
olista01 added inline comments.
Comment at: lib/Frontend/CompilerInvocation.cpp:1133
+ if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
+const auto SignScopeKey = StringRef(A->getValue()).split('+');
+StringRef SignScope = SignScopeKey.first;
olista01 added inline comments.
Comment at: lib/CodeGen/CGDeclCXX.cpp:364
if (RASignKind != CodeGenOptions::SignReturnAddressScope::None)
+ {
Fn->addFnAttr("sign-return-address",
LLVM style has the opening brace on the same line as the if. There's a
git
olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM, thanks!
https://reviews.llvm.org/D51429
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olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM
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olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM
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olista01 added a reviewer: olista01.
olista01 added a comment.
Is there an existing compiler which this option is trying to be compatible
with? GCC for AArch64 doesn't currently have an option for this, so we don't
have to worry about compatibility with that. If possible, I'd prefer for the
opt
olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
I can't see any other uses of the option groups, or any way to put an option
into two groups, so this LGTM.
I'll commit it for you as before.
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Closed by commit rC357250: [AArch64] Support selecting TPIDR_EL[1-3] as the
thread base (authored by olista01, committed by ).
Changed prior to commit:
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Repository:
olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM, thanks!
https://reviews.llvm.org/D51432
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olista01 created this revision.
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This patch allows targetting Armv8.5-A from Clang. Most of the
implementation is in TargetParser, so this is mostly just adding tests.
Patch by Pablo Barrio!
Reposi
olista01 created this revision.
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The implementation of this is in TargetParser, so we only need to add a
test for it in clang.
Patch by Pablo Barrio!
Repository:
rC Clang
https://reviews.llvm.org/D5249
olista01 created this revision.
Herald added a reviewer: javed.absar.
Herald added subscribers: cfe-commits, chrib, kristof.beyls.
The implementation of this is in TargetParser, so we only need to add a
test for it in clang.
Patch by Pablo Barrio!
Repository:
rC Clang
https://reviews.llvm.or
This revision was automatically updated to reflect the committed changes.
Closed by commit rC343111: [ARM/AArch64][v8.5A] Add Armv8.5-A target (authored
by olista01, committed by ).
Changed prior to commit:
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Repository:
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This revision was automatically updated to reflect the committed changes.
Closed by commit rC343220: [AArch64][v8.5A] Test optional Armv8.5-A random
number extension (authored by olista01, committed by ).
Changed prior to commit:
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Reposito
This revision was automatically updated to reflect the committed changes.
Closed by commit rC343566: [AArch64][v8.5A] Test clang option for the Memory
Tagging Extension (authored by olista01, committed by ).
Changed prior to commit:
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Repos
olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM, but please remember to upload with more context.
Repository:
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olista01 requested changes to this revision.
olista01 added inline comments.
This revision now requires changes to proceed.
Comment at: test/Driver/arm-cortex-cpus.c:826
// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CPUV8MMAIN %s
+/
olista01 added a comment.
These macros have been in the published ACLE for a while now:
https://developer.arm.com/products/software-development-tools/compilers/arm-compiler-5/docs/101028/latest/5-feature-test-macros#position-independent-code
Repository:
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olista01 added a comment.
Yes, the back-end work was all done years ago, I just also forgot about these
while waiting for the ACLE to be published.
Repository:
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Closed by commit rL354265: [ARM] Add pre-defined macros for ROPI and RWPI
(authored by olista01, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D23610?vs=91990&id=187220#toc
Repository:
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CHAN
olista01 created this revision.
olista01 added reviewers: rengolin, SjoerdMeijer, flyingforyou.
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This adds a pre-defined macro to test if the compiler has support for the
v8.2-A dot rpoduct intrinsi
olista01 created this revision.
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The ACLE spec which describes these intrinsics hasn't been published yet, but
this is based on the fi
This revision was automatically updated to reflect the committed changes.
Closed by commit rC331038: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro
(authored by olista01, committed by ).
Changed prior to commit:
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Repository:
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olista01 marked an inline comment as done.
olista01 added inline comments.
Comment at: test/CodeGen/arm-neon-dot-product.c:1
+// RUN: %clang_cc1 -triple armv8-linux-gnueabihf -target-cpu cortex-a57
-target-feature +dotprod \
+// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt
This revision was automatically updated to reflect the committed changes.
Closed by commit rC331039: [ARM,AArch64] Add intrinsics for dot product
instructions (authored by olista01, committed by ).
Changed prior to commit:
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olista01 created this revision.
Herald added a subscriber: javed.absar.
The comment markers accepted by the assembler vary between different targets,
but '//' is always accepted, so we should use that for consistency.
Repository:
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https://reviews.llvm.org/D3
Files:
lib/CodeGen/
olista01 added reviewers: rnk, niravd, SjoerdMeijer.
olista01 added a comment.
Ping.
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Closed by commit rL311325: [ObjC] Use consistent comment style in inline asm
(authored by olista01).
Changed prior to commit:
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olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM
Repository:
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olista01 added a comment.
There is existing documentation of the diagnostics system here, which you could
extend if something is still unclear or incomplete:
- clang/docs/InternalsManual.rst
- https://clang.llvm.org/docs/InternalsManual.html#the-diagnostics-subsystem
Repository:
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olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM
Repository:
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olista01 added a comment.
My patch to the ACLE has now been accepted, so it will be in the next release.
This is the wording:
__ARM_ROPI is defined to 1 if the translation unit is being compiled in
read-only position independent mode. In this mode, all read-only data and
functions are at a l
olista01 updated this revision to Diff 91990.
olista01 retitled this revision from "[ARM] Add pre-defined macros for ROPI,
RWPI and FPIC" to "[ARM] Add pre-defined macros for ROPI and RWPI".
olista01 edited the summary of this revision.
Repository:
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File
olista01 added a comment.
What advantages does this have over the current way of printing diagnostics? If
this is just to get -w and -Werror working, would it not be easier to pass
those through to the assembler, than to send all diagnostics back through
clang? We already have some flags in MCT
olista01 added a comment.
That all sounds sensible from an assembler perspective, especially the ability
to gradually move diagnostics into categories rather than having one big change
that touches every assembler diag. However, I've not done much work in clang,
so it would be good to get someo
olista01 added a comment.
The change itself looks fine, but I have a few comments on the test.
Tests of clang shouldn't actually run the assembler, as I think this one will
fail if clang is built without the ARM backend. A better way to write the test
would be to just run the preprocessor, and
olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.
LGTM
https://reviews.llvm.org/D31765
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olista01 added a comment.
Ping.
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olista01 added a comment.
I've proposed a patch to the ACLE to add these macros, but it's stalled in
review. I've just given it a ping, I'll try to get an answer soon.
Repository:
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