[PATCH] D107138: [PowerPC] Implement cmplxl builtins

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:146 BUILTIN(__builtin_ppc_stfiw, "viC*d", "") +BUILTIN(__builtin_ppc_cmplxl, "XLdLdLd", "") ---

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Requesting changes until my comment is answered/addressed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107002/new/ https://revie

[PATCH] D106410: [PowerPC] Emit error for Altivec vector initializations when -faltivec-src-compat=gcc is specified

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Other than the naming nit, this LGTM. Comment at: clang/include/clang/Sema/Sema.h:6103 + // these vectors on gcc (an error is emitted). + bool IsAltivecCompatGCC(Source

[PATCH] D106550: [PowerPC] Allow MMA builtins to accpet restrict qualified pointers

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: clang/lib/Sema/SemaChecking.cpp:7306 (!ExpectedType->isVoidPointerType() && - ArgType.getCanonicalType() != ExpectedType)) +

[PATCH] D104854: Introduce intrinsic llvm.isnan

nemanjai added a comment. This appears to have caused some failures on PPC buildbots. For example: https://lab.llvm.org/buildbot/#/builders/105/builds/13446 We are investigating this. Can you please pull this to bring the bots back to green until we track down the reason for the problem and can

[PATCH] D104854: Introduce intrinsic llvm.isnan

nemanjai added a comment. In D104854#2932186 , @nemanjai wrote: > This appears to have caused some failures on PPC buildbots. For example: > https://lab.llvm.org/buildbot/#/builders/105/builds/13446 > We are investigating this. Can you please pull this t

[PATCH] D104854: Introduce intrinsic llvm.isnan

nemanjai added a comment. Rather than reverting this commit again, I pushed 62fe3dcf98d1 to use the same expansion as before (using unordered comparison) for `ppc_fp128`. I am not sure if there are other types that suffer fro

[PATCH] D107242: [AIX] Define __HOS_AIX__ macro

nemanjai added a comment. In D107242#2932289 , @joerg wrote: > I'm puzzled by this change. I don't think we have any case so far where the > compiler behavior changes with the host OS and I don't think it should. > What's the point / use case of this ma

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

nemanjai added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1 +// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \ +// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s Conanap wrote: > NeHuang wrote: > > NeHuang

[PATCH] D104854: Introduce intrinsic llvm.isnan

nemanjai added inline comments. Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6964 +return DAG.getSetCC(DL, ResultVT, Op, DAG.getConstantFP(0.0, DL, OperandVT), +ISD::SETUO); + sepavloff wrote: > nemanjai wrote: > > sep

[PATCH] D107647: [PowerPC] MMA - Remove deprecated built-ins and add new built-ins

nemanjai added a comment. In D107647#2937706 , @lei wrote: > Actually we should not be removing the deprecated bultins. Just need to add > the new ones. Yes, and also the semantics are different. Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107138/new/ https://reviews.llvm.org/D107138 __

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107002/new/ https://reviews.llvm.org/D107002 __

[PATCH] D106550: [PowerPC] Allow MMA built-ins to accept restrict qualified pointers

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: clang/lib/Sema/SemaChecking.cpp:7329 +// and false if it is not valid. +auto IsValidType = [ArgType, ExpectedType]() { + if (Expect

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15962 if (Depth > 0) { +SDValue FrameAddr = Please add a comment: ``` // The link register (return address) is saved in the caller's frame // not the callee's stack f

[PATCH] D107899: [PowerPC] Implement builtin for vbpermd

nemanjai created this revision. nemanjai added a reviewer: PowerPC. Herald added subscribers: shchenz, kbarton, hiraditya. nemanjai requested review of this revision. Herald added projects: clang, LLVM. The instruction has similar semantics to vbpermq but for doublewords. It was added in P9

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for fixing this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107646/new/ https://reviews.llvm.org/D107646 __

[PATCH] D105236: [PowerPC] Implament Atomic Load and Stores Builtins

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1724 + +let Predicates = [HasP8Altivec] in { + def : Pat<(int_ppc_stdcx xoaddr:$dst, g8rc:$A), lkail wrote: > IIRC, `l(w|d)arx`, `st(w|d)cx` are supported very early and don't n

[PATCH] D105236: [PowerPC] Implament Load and Reserve and Store Conditional Builtins

nemanjai accepted this revision. nemanjai added a comment. LGTM aside from a small nit. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll:2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai added a comment. Can you please add a test for this similar to `clang/test/Driver/ppc-pcrel.cpp` and other similar tests? Also, I imagine this will produce some warnings from the back end since the back end doesn't know what these target features mean. Can you please see what happens w

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. It appears that Victor's comments have not been addressed yet and this is not ready for the next round of review. Requesting changes again to take it out of the queue until Victo

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll:135 +; CHECK: # %bb.0: +; CHECK-NEXT:twnei 3, 0 +; CHECK-NEXT:blr Where are the aliases `twnei` and `tdnei` coming from? You don't seem to add them.

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1733 +// as XL produces a tweq , . +def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31), + (TD 4, $A,

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

nemanjai accepted this revision. nemanjai added a comment. LGTM. @NeHuang please have a look to see if your comments are adequately addressed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103668/new/ https://reviews.llvm.org/D103668

[PATCH] D105236: [PowerPC] Implement Load and Reserve and Store Conditional Builtins

nemanjai added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1533 + def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; + def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

nemanjai added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1535 - def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">, - Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>; } lkail wrote: > Just curious, compi

[PATCH] D105666: [PowerPC] [Altivec] Use signed comparison for vec_all_* and vec_any_* interfaces that compare vector bool types with vector signed types

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105666/new/ https://reviews.llvm.org/D105666 __

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3275 -static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall, - StringRef FeatureToCheck, unsigned DiagID) { +static bool SemaArchFeatureCheck(Sema &S, CallExpr *TheCall, +

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. I believe that your failing test case is because you are attempting to emit code for these builtins in the target independent code and the values just happen to match up.

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai added a comment. The testing is a bit overkill. A single test case with run lines for `-mcpu=pwr7-10` and a single prefix for each should suffice. For each prefix, just check for `+/-` for all the features you expect. The triples can be randomly distributed across the 4 run lines. And

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105501/new/ https://reviews.llvm.org/D105501 __

[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105834/new/ https://reviews.llvm.org/D105834 __

[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

nemanjai added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c:1 +// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \ +// RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8 Oh, I believe you're missi

[PATCH] D105360: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105360/new/ https://reviews.llvm.org/D105360 __

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

nemanjai added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:9754 "this builtin is only valid on POWER7 or later CPUs">; +def err_ppc_builtin_only_on_pwr9 : Error< + "this builtin is only valid on POWER9 or later CPUs">; No lon

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

nemanjai added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll:18 entry: - %0 = bitcast i64* %a to i8* - %1 = tail call i64 @llvm.ppc.ldarx(i8* %0) - ret i64 %1 + %0 = call i64 asm sideeffect "ldarx $0, $1", "

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105754/new/ https://reviews.llvm.org/D105754 __

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

nemanjai added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-fp.c:5 +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \ +// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-unknown-aix \

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Requesting changes to keep the queue accurate. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102875/new/ https://reviews.llvm.org/

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Requesting changes to remove it from the queue until comments are addressed or answered. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Also if we are going to be emitting this complex sequence, in the description of the patch, point out the test case that shows the back end handles this and emits a single instru

[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: clang/include/clang/Sema/Sema.h:12559 bool SemaBuiltinOSLogFormat(CallExpr *TheCall); + bool CheckPPCisRunOfOnes(CallExpr *TheCall, unsigned

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM aside from a formatting nit. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1574 + : GCCBuiltin<"__builtin_ppc_cmprb">, +Intrinsic<[llvm_i32_ty],

[PATCH] D105957: [PowerPC] Implement intrinsics for mtfsf[i]

nemanjai created this revision. nemanjai added reviewers: PowerPC, ZhangKang. Herald added subscribers: shchenz, kbarton, hiraditya. nemanjai requested review of this revision. Herald added projects: clang, LLVM. Herald added a subscriber: cfe-commits. This provides intrinsics for emitting instruc

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

nemanjai added a subscriber: ZhangKang. nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3087 // RM should be set. +let hasSideEffects = 1 in { def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), I think we should conservat

[PATCH] D105957: [PowerPC] Implement intrinsics for mtfsf[i]

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:4484 +// as an implicit def for all of them. +let Predicates = [HasFPU] in { +let Defs = [RM] in { @ZhangKang You modified this code most recently. Please provide your opinion he

[PATCH] D105926: [PowerPC] Extra test case for LDARX

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll:1 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +;

[PATCH] D105926: [PowerPC] Extra test case for LDARX

nemanjai added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll:149 + +attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tar

[PATCH] D105360: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:831 +// 64bit version of popcntb for 64bit sized unsigned long. +let isCodeGenOnly = 1 in +def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), efriedma wrote: > I'

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Please change `compact` in the title to `compat`. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:76-79 +BUILTIN(__builtin_ppc_mtfsb0, "vUi", "") +BUILTIN

[PATCH] D105360: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:831 +// 64bit version of popcntb for 64bit sized unsigned long. +let isCodeGenOnly = 1 in +def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), efriedma wrote: > ne

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5003 +N->getConstantOperandVal(1) == Intrinsic::ppc_tw) { + int16_t SImm; + if (isIntS16Immediate(N->getOperand(3), SImm)) { I think a couple of improvements

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1011 + case PPC::TDI: + case PPC::TWI: { +MachineInstr *LiMIA = getVRegDefOrNull(&MI.getOperand(1), MRI); Seems that we should be able to handle all 4 in the s

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5001 + case ISD::INTRINSIC_VOID: { +if (N->getConstantOperandVal(1) == Intrinsic::ppc_tdw || +

[PATCH] D106409: [PowerPC] Truncate exponent parameter for vec_cts,vec_ctf

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. I believe you are planning an update for this patch. Requesting changes to take it off the queue until you have uploaded the updated version. Repository: rG LLVM Github Monore

[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM other than a number of stylistic changes. Feel free to address those on the commit. You also might want to give @amyk a bit of time to ensure her comments were adequately addressed.

[PATCH] D113642: [PowerPC] Provide XL-compatible vec_round implementation

nemanjai created this revision. nemanjai added reviewers: PowerPC, rzurob, qiongsiwu. Herald added subscribers: shchenz, kbarton, hiraditya. nemanjai requested review of this revision. Herald added projects: clang, LLVM. The XL implementation of `vec_round` for `vector double` uses "round-to-near

[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. There are some very minor nits that can be addressed on the commit. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1018 +unsigned Opcode2 = LiMI2->ge

[PATCH] D98546: [PowerPC] Add __PCREL__ when PC Relative is enabled.

nemanjai added a comment. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98546/new/ https://reviews.llvm.org/D98546 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm

[PATCH] D109751: [Clang] Support conversion between PPC double-double and IEEE float128

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Please provide a description for this patch which includes justification for why we want to allow conversion between the two types. I am of the impression that allowing the two ty

[PATCH] D113306: [PowerPC] Allow MMA built-ins to accept non-void pointers and arrays

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thank you. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D113306/new/ https://reviews.llvm.org/D113306 ___

[PATCH] D114088: [PowerPC] Add BCD add/sub/cmp builtins

nemanjai created this revision. nemanjai added reviewers: bmahjour, PowerPC. Herald added subscribers: shchenz, kbarton, hiraditya. nemanjai requested review of this revision. Herald added projects: clang, LLVM. Support for builtins that use `bcdadd./bcdsub.` to add/subtract Binary Coded Decimal

[PATCH] D114088: [PowerPC] Add BCD add/sub/cmp builtins

nemanjai added inline comments. Comment at: clang/lib/Headers/altivec.h:19050 +} + +static __inline__ long __bcdcmpeq(vector unsigned char __a, NeHuang wrote: > Do we need to add a case for "__CR6_SO_REV"? It is defined in line 25 but not > used. I added it for

[PATCH] D114088: [PowerPC] Add BCD add/sub/cmp builtins

This revision was automatically updated to reflect the committed changes. Closed by commit rGc933c2eb3346: [PowerPC] Add BCD add/sub/cmp builtins (authored by nemanjai). Changed prior to commit: https://reviews.llvm.org/D114088?vs=387933&id=389238#toc Repository: rG LLVM Github Monorepo CHA

[PATCH] D113642: [PowerPC] Provide XL-compatible vec_round implementation

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb7bf937bbee3: [PowerPC] Provide XL-compatible vec_round implementation (authored by nemanjai). Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D114540: Big-endian version of vpermxor

nemanjai added a comment. Please also add a test for this builtin to the front end test `clang/test/CodeGen/builtins-ppc-crypto.c` Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2499 (COPY_TO_REGCLASS $c, VSRC>; + def : Pa

[PATCH] D114540: Big-endian version of vpermxor

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2506 + def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor_be v16i8:$a, +

[PATCH] D114497: [PowerPC] Drop stdlib paths in freestanding tests

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Seems fine to me but maybe give @MaskRay a couple of days to see if this adequately addresses his comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revie

[PATCH] D85599: [PowerPC] Remove isTerminator for TRAP instruction

nemanjai added a comment. Herald added a project: All. I think we should handle this similarly to `SITargetLowering::splitKillBlock()`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D85599/new/ https://reviews.llvm.org/D85599 __

[PATCH] D134371: [clang-doc] Add typedef/using information.

nemanjai added a comment. This causes failures with `-Werror` such as: https://lab.llvm.org/buildbot/#/builders/57/builds/22322 Please fix or revert. Comment at: clang-tools-extra/clang-doc/Representation.h:45 + IT_enum, + IT_typedef }; There are at least a

[PATCH] D137511: [PPC] Undefine __ppc64__ to match GCC

nemanjai added a comment. As mentioned by @q66 above, this can't go in until usage of this macro in the Clang/LLVM codebase is fixed. Looks like the uses in `clang/lib/Headers/ppc_wrappers` and some of the uses in `libcxx` and `libunwind` must be fixed while others should probably also be fixed

[PATCH] D137511: [PPC] Undefine __ppc64__ to match GCC

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. I am going to block this since the uses of the macros in `clang/lib/Headers/ppc_wrappers` will likely cause build bot failures. Repository: rG LLVM Github Monorepo CHANGES SI

[PATCH] D142222: [PowerPC] Remove the lax warning for explicit casts

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM other than the missing template test. Comment at: clang/test/Parser/lax-conv.cpp:4 +// RUN: %clang_cc1 -triple=powerpc64-ibm-aix -target-feature +altivec -target-fe

[PATCH] D124093: [PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions

nemanjai added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15587 + +bool isUnaligned = (BuiltinID == PPC::BI__builtin_altivec_vinsw || +BuiltinID == PPC::BI__builtin_altivec_vinsd) This is strange. You don't need the t

[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

nemanjai added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:7571-7573 + "Current bitcast for incompatible vector types (%0 and %1) are deprecated. " + "The default behaviour will change to what is implied by the " + "-fno-lax-vector-conversions

[PATCH] D124093: [PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c:8 // RUN: -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck %s -// RUN: %clang_cc1 -no-

[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

nemanjai added inline comments. Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:2152 ChosenToolsetVersion = ToolsetVersion; -ChosenToolsetDir = "/opt/rh/" + ToolsetDir.str(); +ChosenToolsetDir = "/opt/rh/" + ToolsetDir.str() + "/root/usr"; } --

[PATCH] D125862: [clang][driver] Add gcc-toolset/devtoolset 12 to prefixes

nemanjai added subscribers: quinnp, nemanjai. nemanjai added a comment. The original toolchain detection added `root/usr` to the paths which was certainly necessary on PowerPC. Since that suffix is removed in this patch, our Redhat buildbot is now broken (https://lab.llvm.org/buildbot/#/builder

[PATCH] D127310: [clang][driver] fix to correctly set devtoolset on RHEL

nemanjai added a comment. In D127310#3567472 , @MaskRay wrote: > Do you have more authoritative answer when /root/usr is used and when it > isn't? These suffixes were always part of the code and the mentioned changeset removed it without any justificat

[PATCH] D116016: [Clang] [PowerPC] Emit module flag for current float abi

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for reviving this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116016/new/ https://reviews.llvm.org/D116016 __

[PATCH] D152914: [Draft] Make __builtin_cpu builtins target-independent

nemanjai added inline comments. Comment at: llvm/include/llvm/IR/Intrinsics.td:903-907 +// Load of a value provided by the system library at a fixed address. Used for +// accessing things like HWCAP word provided by GLIBC. +def int_fixed_addr_ld +: DefaultAttrsIntrinsic<[llvm

[PATCH] D156076: [PowerPC][Clang] Remove constraint for initial-exec TLS mode on AIX

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Please provide a description justifying this change. There is no context here for the viewer to determine whether this change makes sense. Repository: rG LLVM Github Monorepo

[PATCH] D156076: [PowerPC][Clang] Remove constraint for initial-exec TLS mode on AIX

nemanjai added a comment. So we don't have code generation for this, but we are enabling it in the front end? What happens if we try to produce code for the IR this produces? It would make more sense to me to implement what is needed in the back end prior to allowing the front end to produce th

[PATCH] D156351: clang driver throws error for -mabi=elfv2 or elfv2

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Ah, ok. This makes sense. When we don't know anything about the ABI, it makes sense to rely on `-mabi`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.

[PATCH] D158066: [PowerPC] Fix use of FPSCR builtins in smmintrin.h

nemanjai added a comment. In D158066#4593961 , @qiucf wrote: > CC @amyk @quinnp Any comments about the naming? > > I see some `__builtin_ppc_xxx` are aliased into `__builtin_xxx` by > `defineXLCompatMacros`. But these are not XL-compatible builtins, and

[PATCH] D158065: [PowerPC] Implement builtin for mffsl

nemanjai accepted this revision. nemanjai added a comment. Thanks for implementing this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158065/new/ https://reviews.llvm.org/D158065 ___ cfe-commits mailing

[PATCH] D152914: [Draft] Make __builtin_cpu builtins target-independent

nemanjai added a comment. In D152914#4653669 , @lei wrote: > HI @nemanjai, Did you get a chance to post this as a github PR? Long overdue, but I finally have it up at https://github.com/llvm/llvm-project/pull/68919 Repository: rG LLVM Github Monorep

[PATCH] D152914: [Draft] Make __builtin_cpu builtins target-independent

nemanjai added a comment. In D152914#4602914 , @ilinpv wrote: > Friendly ping, are there any questions remained to proceed with > target-independent __builtin_cpu_supports ? Sorry, I have not gotten back to this review in quite some time as I have been

[PATCH] D154357: [Driver] Recognize powerpc-unknown-eabi as a bare-metal toolchain

nemanjai accepted this revision. nemanjai added a comment. No concerns from the perspective of PowerPC here. Of course, my focus is primarily on the server side of things but I am not aware of any other group that could be adversely affected. CHANGES SINCE LAST ACTION https://reviews.llvm.or

[PATCH] D155111: [clangd] Fix build failures observed on build bots for missing libs

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Lets get this committed to unblock the bots and if it is not the correct/desired fix, the author can subsequently provide the more appropriate fix. Repository: rG LLVM Github Monorepo

[PATCH] D152914: [Draft] Make __builtin_cpu builtins target-independent

nemanjai added a comment. In D152914#4428692 , @ilinpv wrote: > Thank you for the patch, it comes in the right time - we are also working on > AArch64 __builtin_cpu_supports, and I was thinking how to make it more > general. > I uploaded our RFC version

[PATCH] D152914: [Draft] Make __builtin_cpu builtins target-independent

nemanjai added a comment. @arsenm Has my description adequately addressed your question? Do you think we should move forward with [some version of] this patch or do you have any fundamental objections? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/

[PATCH] D152914: [Draft] Make __builtin_cpu builtins target-independent

nemanjai added inline comments. Comment at: llvm/include/llvm/IR/Intrinsics.td:903-907 +// Load of a value provided by the system library at a fixed address. Used for +// accessing things like HWCAP word provided by GLIBC. +def int_fixed_addr_ld +: DefaultAttrsIntrinsic<[llvm

[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. This is a good idea and we should go ahead with this for anyone that uses `vec_promote`, but it might be a good idea to improve codegen for the insert which might be more common.

[PATCH] D137511: [PPC] Undefine __ppc64__ to match GCC

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks so much for fixing up the existing code. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137511/new/ https://reviews.llvm.org/D13

[PATCH] D77249: [MSan] Pass command line options to MSan with new pass manager

nemanjai created this revision. nemanjai added reviewers: eugenis, vitalybuka, philip.pfaffe, leonardchan, PowerPC. Herald added projects: clang, Sanitizers. Herald added subscribers: Sanitizers, cfe-commits. There are a number of test cases that fail when clang is built to use NPM by default. T

[PATCH] D77249: [MSan] Pass command line options to MSan with new pass manager

nemanjai marked an inline comment as done. nemanjai added inline comments. Comment at: compiler-rt/test/msan/chained_origin_empty_stack_npm.cpp:4 +// this test. +// RUN: %clangxx_msan -fsanitize-memory-track-origins=2 \ +// RUN: -fexperimental-new-pass-manager -O3 %s -o %t &&

[PATCH] D77249: [MSan] Pass command line options to MSan with new pass manager

nemanjai marked an inline comment as done. nemanjai added inline comments. Comment at: compiler-rt/test/msan/chained_origin_empty_stack_npm.cpp:4 +// this test. +// RUN: %clangxx_msan -fsanitize-memory-track-origins=2 \ +// RUN: -fexperimental-new-pass-manager -O3 %s -o %t &&

[PATCH] D64024: [PowerPC][Altivec] Emit correct builtin for single precision vec_all_ne

nemanjai added a comment. Herald added subscribers: shchenz, wuzish. In D64024#1565190 , @jsji wrote: > LGTM. > BTW, looks like we are missing test cases all `vector float` `vec_all*` and > `vec_any*` and also non-vsx path? The non-VSX path is tested

[PATCH] D64024: [PowerPC][Altivec] Emit correct builtin for single precision vec_all_ne

This revision was automatically updated to reflect the committed changes. Closed by commit rG070e4027b024: [PowerPC][Altivec] Emit correct builtin for single precision vec_all_ne (authored by nemanjai). Changed prior to commit: https://reviews.llvm.org/D64024?vs=207374&id=228354#toc Repository

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