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This provides intrinsics for emitting instructions that set the FPSCR
(`mtfsf/mtfsfi`).
The patch also conservatively marks the rounding mode as an implicit def for
both since they both may set the rounding mode depending on the operands.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D105957
Files:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN: FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-AIX64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-AIX32
+
+define dso_local void @mtfsb0() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: mtfsb0 10
+; CHECK-PWR8-NEXT: blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7: # %bb.0: # %entry
+; CHECK-PWR7-NEXT: mtfsb0 10
+; CHECK-PWR7-NEXT: blr
+; CHECK-LABEL: mtfsb0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtfsb0 10
+; CHECK-NEXT: blr
+;
+; CHECK-AIX64-LABEL: mtfsb0:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: mtfsb0 10
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: mtfsb0:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: mtfsb0 10
+; CHECK-AIX32-NEXT: blr
+entry:
+ tail call void @llvm.ppc.mtfsb0(i32 10)
+ ret void
+}
+
+define dso_local void @mtfsb1() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb1:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT: mtfsb1 0
+; CHECK-PWR8-NEXT: blr
+;
+; CHECK-PWR7-LABEL: mtfsb1:
+; CHECK-PWR7: # %bb.0: # %entry
+; CHECK-PWR7-NEXT: mtfsb1 0
+; CHECK-PWR7-NEXT: blr
+; CHECK-LABEL: mtfsb1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtfsb1 0
+; CHECK-NEXT: blr
+;
+; CHECK-AIX64-LABEL: mtfsb1:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: mtfsb1 0
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: mtfsb1:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: mtfsb1 0
+; CHECK-AIX32-NEXT: blr
+entry:
+ tail call void @llvm.ppc.mtfsb1(i32 0)
+ ret void
+}
+
+define dso_local void @callmtfsf(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsf:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtfprwz 0, 3
+; CHECK-NEXT: xscvuxddp 0, 0
+; CHECK-NEXT: mtfsf 7, 0
+; CHECK-NEXT: blr
+;
+; CHECK-AIX64-LABEL: callmtfsf:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: addi 4, 1, -4
+; CHECK-AIX64-NEXT: stw 3, -4(1)
+; CHECK-AIX64-NEXT: lfiwzx 0, 0, 4
+; CHECK-AIX64-NEXT: xscvuxddp 0, 0
+; CHECK-AIX64-NEXT: mtfsf 7, 0
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: callmtfsf:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: addi 4, 1, -4
+; CHECK-AIX32-NEXT: stw 3, -4(1)
+; CHECK-AIX32-NEXT: lfiwzx 0, 0, 4
+; CHECK-AIX32-NEXT: xscvuxddp 0, 0
+; CHECK-AIX32-NEXT: mtfsf 7, 0
+; CHECK-AIX32-NEXT: blr
+entry:
+ %0 = uitofp i32 %a to double
+ tail call void @llvm.ppc.mtfsf(i32 7, double %0)
+ ret void
+}
+
+define dso_local void @callmtfsfi(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsfi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtfsfi 1, 3
+; CHECK-NEXT: blr
+;
+; CHECK-AIX64-LABEL: callmtfsfi:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT: mtfsfi 1, 3
+; CHECK-AIX64-NEXT: blr
+;
+; CHECK-AIX32-LABEL: callmtfsfi:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT: mtfsfi 1, 3
+; CHECK-AIX32-NEXT: blr
+entry:
+ tail call void @llvm.ppc.mtfsfi(i32 1, i32 3)
+ ret void
+}
+
+declare void @llvm.ppc.mtfsb0(i32)
+declare void @llvm.ppc.mtfsb1(i32)
+declare void @llvm.ppc.mtfsfi(i32, i32)
+declare void @llvm.ppc.mtfsf(i32, double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -8,44 +8,6 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
; RUN: FileCheck %s --check-prefix=CHECK-PWR8
-; Function Attrs: nounwind uwtable
-define dso_local void @mtfsb0() local_unnamed_addr #0 {
-; CHECK-PWR8-LABEL: mtfsb0:
-; CHECK-PWR8: # %bb.0: # %entry
-; CHECK-PWR8-NEXT: mtfsb0 10
-; CHECK-PWR8-NEXT: blr
-;
-; CHECK-PWR7-LABEL: mtfsb0:
-; CHECK-PWR7: # %bb.0: # %entry
-; CHECK-PWR7-NEXT: mtfsb0 10
-; CHECK-PWR7-NEXT: blr
-entry:
- tail call void @llvm.ppc.mtfsb0(i32 10)
- ret void
-}
-
-; Function Attrs: nounwind
-declare void @llvm.ppc.mtfsb0(i32)
-
-; Function Attrs: nounwind uwtable
-define dso_local void @mtfsb1() local_unnamed_addr #0 {
-; CHECK-PWR8-LABEL: mtfsb1:
-; CHECK-PWR8: # %bb.0: # %entry
-; CHECK-PWR8-NEXT: mtfsb1 0
-; CHECK-PWR8-NEXT: blr
-;
-; CHECK-PWR7-LABEL: mtfsb1:
-; CHECK-PWR7: # %bb.0: # %entry
-; CHECK-PWR7-NEXT: mtfsb1 0
-; CHECK-PWR7-NEXT: blr
-entry:
- tail call void @llvm.ppc.mtfsb1(i32 0)
- ret void
-}
-
-; Function Attrs: nounwind
-declare void @llvm.ppc.mtfsb1(i32)
-
; Function Attrs: mustprogress nofree nosync nounwind readnone uwtable willreturn
define dso_local double @fmsub_t0(double %d, double %d2, double %d3) local_unnamed_addr {
; CHECK-PWR8-LABEL: fmsub_t0:
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3098,7 +3098,8 @@
let Defs = [RM] in {
let isCodeGenOnly = 1 in
def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
- "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
+ "mtfsf $FM, $rT", IIC_IntMTFSB0,
+ [(int_ppc_mtfsf imm:$FM, f64:$rT)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
}
let Uses = [RM] in {
@@ -4478,19 +4479,20 @@
def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
"mcrfs $BF, $BFA", IIC_BrMCR>;
-// If W is 0 and BF is 7, the 60:63 bits will be set, we should set the
-// implicit-def RM.
-def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
+// All MTFSF variants may change the rounding mode so conservatively set it
+// as an implicit def for all of them.
+let Predicates = [HasFPU] in {
+let Defs = [RM] in {
+let isCodeGenOnly = 1,
+ Pattern = [(int_ppc_mtfsfi imm:$BF, imm:$U)], W = 0 in
+def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U),
+ "mtfsfi $BF, $U", IIC_IntMFFS>;
+def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W),
"mtfsfi $BF, $U, $W", IIC_IntMFFS>;
let Defs = [CR1] in
-def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
+def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W),
"mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm;
-def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
-def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>;
-
-let Predicates = [HasFPU] in {
-let Defs = [RM] in {
def MTFSF : XFLForm_1<63, 711, (outs),
(ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),
"mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
@@ -4500,6 +4502,8 @@
"mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;
}
+def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>;
+def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>;
def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;
}
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===================================================================
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1078,7 +1078,8 @@
DISP_3SLOTS_1C, DISP_3SLOTS_1C],
(instrs
(instregex "MTFSF(b|_rec)?$"),
- (instregex "MTFSFI(_rec)?$")
+ (instregex "MTFSFI(_rec)?$"),
+ MTFSFIb
)>;
// Cracked instruction made of two ALU ops.
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1583,9 +1583,8 @@
: GCCBuiltin<"__builtin_ppc_mtfsb1">,
Intrinsic <[], [llvm_i32_ty],
[IntrNoMem, IntrHasSideEffects]>;
- def int_ppc_mtfsf
- : GCCBuiltin<"__builtin_ppc_mtfsf">,
- Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
+ def int_ppc_mtfsf :
+ Intrinsic <[], [llvm_i32_ty, llvm_double_ty],
[IntrNoMem, IntrHasSideEffects]>;
def int_ppc_mtfsfi
: GCCBuiltin<"__builtin_ppc_mtfsfi">,
Index: clang/test/CodeGen/builtins-ppc-xlcompat-math.c
===================================================================
--- clang/test/CodeGen/builtins-ppc-xlcompat-math.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-math.c
@@ -24,10 +24,8 @@
}
// CHECK-LABEL: @mtfsf(
-// CHECK: [[UI_ADDR:%.*]] = alloca i32, align 4
-// CHECK-NEXT: store i32 [[UI:%.*]], i32* [[UI_ADDR]], align 4
-// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[UI_ADDR]], align 4
-// CHECK-NEXT: call void @llvm.ppc.mtfsf(i32 8, i32 [[TMP0]])
+// CHECK: [[TMP0:%.*]] = uitofp i32 %{{.*}} to double
+// CHECK-NEXT: call void @llvm.ppc.mtfsf(i32 8, double [[TMP0]])
// CHECK-NEXT: ret void
//
void mtfsf (unsigned int ui) {
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15575,6 +15575,13 @@
case PPC::BI__builtin_ppc_ldarx:
case PPC::BI__builtin_ppc_lwarx:
return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+ case PPC::BI__builtin_ppc_mtfsf: {
+ // The builtin takes a uint32 that needs to be cast to an
+ // f64 to be passed to the intrinsic.
+ Value *Cast = Builder.CreateUIToFP(Ops[1], DoubleTy);
+ llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_mtfsf);
+ return Builder.CreateCall(F, {Ops[0], Cast}, "");
+ }
}
}
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