[PATCH] D106150: [PowerPC] swdiv_nochk Builtins for XL Compat

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM other than a couple of nits. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15627 +Builder.getFastMathFlags().setFast(); +Value *fdiv = Builder.CreateFDiv(Ops[0

[PATCH] D105957: [PowerPC] Implement intrinsics for mtfsf[i]

nemanjai added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1589 [IntrNoMem, IntrHasSideEffects]>; def int_ppc_mtfsfi : GCCBuiltin<"__builtin_ppc_mtfsfi">, qiucf wrote: > If `mtfsf` was changed, `mtfsfi` `mt

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:4072 + +def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), + (STXSIWX f64:$XT, ForceXForm:$dst)>; I just realized this is in the wrong place. STXSIWX was added in Power8

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

nemanjai added a comment. Could you please add a check for constant arguments to `clang/test/CodeGen/builtins-ppc-xlcompat-error.c`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106130/new/ https://reviews.llvm.org/D106130 __

[PATCH] D106120: [PowerPC] Implement vector bool/pixel initialization under -faltivec-src-compat=xl

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM other than a minor nit about a comment. Comment at: clang/include/clang/Sema/Sema.h:6112-6115 + // Checks if we have a valid AltiVec vector type, and splats the +

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM aside from a very minor nit. Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4990 case ISD::INTRINSIC_WO_CHAIN: { +// We emit the ppc_fsels intrinsic

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 __

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106130/new/ https://reviews.llvm.org/D106130 __

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Mostly minor comments, but it'll be good to have another look to make sure they're all addressed. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15101 +// ret

[PATCH] D106282: [PowerPC] Update builtins-ppc-altivec.c to be run under `-faltivec-src-compat=mixed`

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Please don't forget to mark this as NFC in the title. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106282/new/ https://reviews.llvm.o

[PATCH] D105926: [PowerPC] Extra test case for LDARX

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105926/new/ https://reviews.llvm.org/D105926 __

[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104386/new/ https://reviews.llvm.org/D104386 __

[PATCH] D105194: [PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thank you. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105194/new/ https://reviews.llvm.org/D105194 ___

[PATCH] D106409: [PowerPC] Add diagnostic for out of range values for vec_cts,vec_ctf

nemanjai added a comment. My preference would be to just truncate the value with `& 0x1F`. It won't produce any code in the binary and will work as expected. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106409/new/ https://reviews.llvm.org/D10640

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM aside from a small nit. Comment at: clang/lib/Basic/Targets/PPC.cpp:124 Builder.defineMacro("__stfiw", "__builtin_ppc_stfiw"); + Builder.defineMacro("__stbcx", "

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

nemanjai added a comment. In D106757#2902849 , @Conanap wrote: > do we need an IR -> ASM test case as well? I didn't add this as the builtins do not produce any new IR - there are no new intrinsics or any other modifications to the back end. Since the c

[PATCH] D106530: [PowerPC] Change altivec indexed load/store builtins argument type

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for fixing this. I am just curious, was this revealed from a real world test that used an offset that is so large that it doesn't fit into 32 bits? Repository: rG LLVM Gith

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

nemanjai updated this revision to Diff 361658. nemanjai added a comment. Cleaned up some of the control flow. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106757/new/ https://reviews.llvm.org/D106757 Files: clang/include/clang/Basic/BuiltinsPPC

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

nemanjai added inline comments. Comment at: llvm/lib/Target/PowerPC/P9InstrResources.td:1434 + ADDEX, + ADDEX8 )> { let Unsupported = 1; } You have added the 64-bit version of this, but it seems this is only available for 64-bit operands in 64-bit mode. Under

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

nemanjai accepted this revision. nemanjai added a comment. Please add a test case that would cause a failure prior to this patch due to the argument being emitted more than once (i.e. the test case that prompted this patch). If that is already added and I just missed it, please add a note to th

[PATCH] D67678: PR17164: Change clang's default behavior from -flax-vector-conversions=all to -flax-vector-conversions=integer.

nemanjai added a comment. In D67678#3446526 , @rsmith wrote: > @dexonsmith @arphaman What do we need to do to get this re-landed? FWIW, on the PPC side, we are working on cleaning up `altivec.h` and plan to eventually make `-fno-lax-vector-conversions` t

[PATCH] D122983: [C11/C2x] Change the behavior of the implicit function declaration warning

nemanjai added a comment. This is still causing failures when building `test-suite`: https://lab.llvm.org/buildbot/#/builders/105/builds/24292 Why don't we just turn off this warning for the entire `test-suite` since I don't expect we want to modify the tests (as some of them have licenses that

[PATCH] D122983: [C11/C2x] Change the behavior of the implicit function declaration warning

nemanjai added a comment. In D122983#3463569 , @xbolva00 wrote: > But your link shows failures in compiler-rt/, not in llvm test-suite It shows both. But the `compiler-rt` ones have subsequently been fixed while the `test-suite` ones are still failing a

[PATCH] D124093: [PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Also, please run `clang-format` on the changes. Comment at: clang/lib/Headers/altivec.h:19051 #ifdef __LITTLE_ENDIAN__ - return __builtin_altivec_vstribl_p(__

[PATCH] D122983: [C11/C2x] Change the behavior of the implicit function declaration warning

nemanjai added a comment. @daltenty Can you please run this with the same config as the bot on one of our AIX machines but be sure to pass `-i` if it's `make` or `-k 0` if it's `ninja`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122983/new/ htt

[PATCH] D122983: [C11/C2x] Change the behavior of the implicit function declaration warning

nemanjai added a comment. In D122983#3465122 , @aaron.ballman wrote: > In D122983#3465099 , @nemanjai > wrote: > >> @daltenty Can you please run this with the same config as the bot on one of >> our AIX machine

[PATCH] D118753: [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 only.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D118753/new/ https://reviews.llvm.org/D118753 __

[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.

nemanjai added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:519 .Default(false); + Features["crbits"] = llvm::StringSwitch(CPU) +.Case("ppc64le", true) shchenz wrote: > amyk wrote:

[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.

nemanjai added inline comments. Comment at: clang/docs/ClangCommandLineReference.rst:3566 +Control the CR-bit tracking feature on PowerPC. ``-mcrbits`` (the enablement of CR-bit tracking support) is the default for POWER8 and above. + ``` ... is the default fo

[PATCH] D125203: [PowerPC] Fix PPCISD::STBRX selection issue on A2

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. In D125203#3502651 , @tingwang wrote: > In D125203#3502433 , @nemanjai > wrote: > >> Why not also fix th

[PATCH] D126302: [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float

nemanjai created this revision. nemanjai added reviewers: Laurentiu, PowerPC. Herald added subscribers: shchenz, kbarton. Herald added a project: All. nemanjai requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. The current behaviour with these

[PATCH] D58497: Clear the KnownModules cache if the preprocessor is going away

nemanjai added a comment. I have not seen this problem resurface to be honest. When we initially hit it, changing the path for the build worked around the problem for us so we weren't really hitting in any longer. I posted this because I realized the possibility exists of having these dangling

[PATCH] D36431: Add powerpc64 to compiler-rt build infrastructure.

nemanjai added a comment. This patch appears to be perfectly fine. However, it triggers a large number of warnings. Namely, there's a large number of `warning: ISO C forbids an empty translation unit [-Wpedantic]` warnings produced. The reason is that all the code in the file is wrapped with an

[PATCH] D36555: Move x86-specific sources to x86-specific source lists.

nemanjai added a comment. Thank you for doing this. These were causing warnings with some compilers when built on PowerPC because the sources were just empty (macro-guarded). Not compiling them at all is a much cleaner solution. LGTM but I am far from an authority on this part of the code so I'l

[PATCH] D36431: Add powerpc64 to compiler-rt build infrastructure.

nemanjai added a comment. Some buildbots use the distro gcc (looks like 5.4) and at least one uses gcc 7.1. I use gcc 6.2. I think that with the addition of https://reviews.llvm.org/D36555, the empty source file warnings should go away. However, I imagine that the warnings about atomics will st

[PATCH] D36764: The following functions and tests work fine for powerpc64, so enable them.

nemanjai added a comment. In https://reviews.llvm.org/D36764#843778, @saugustine wrote: > Anyone have any opinions on this? I don't see an issue with providing these functions on PowerPC as there doesn't seem to be anything in the implementation that PowerPC would have an issue with. However,

[PATCH] D36764: The following functions and tests work fine for powerpc64, so enable them.

nemanjai added a comment. In https://reviews.llvm.org/D36764#844486, @joerg wrote: > Because PPC uses the TC variant. Sorry, I don't understand this comment. What is the "TC variant"? https://reviews.llvm.org/D36764 ___ cfe-commits mailing list c

[PATCH] D36764: The following functions and tests work fine for powerpc64, so enable them.

nemanjai added a comment. In https://reviews.llvm.org/D36764#844692, @joerg wrote: > divtc3 and friends. Ah, OK. I see what you mean now. These builtins are for `XCmode` calculations (complex values as two `XFmode` components). Since PPC has no support for `XFmode` (i.e. 80-bit long double) i

[PATCH] D71600: PowerPC 32-bit - forces 8 byte lock/lock_free decisions at compiled time

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Comment at: clang/lib/AST/ExprConstant.cpp:11028 +// The lock free possibilities on this platform are covered by the lines +// above and we know in advance

[PATCH] D72579: Evaluate __{c11_,}atomic_is_lock_free to 0 (avoid libcall) if larger than MaxAtomicPromoteWidth

nemanjai added a comment. If I understand this correctly, this just evaluates the query for lock free atomics at compile time if the size is larger than the maximum possible size for an atomic on the target. If that's the case, this looks fine to me. But of course, some of the other target main

[PATCH] D87321: Fix -gz=zlib options for linker

nemanjai added a comment. This broke the PPC LLD bot and the failure has been ignored for 4 days. I believe it should be fixed with 3bc3983f229 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revi

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai added a comment. Yes, this definitely needs a test case. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84962/new/ https://reviews.llvm.org/D84962 ___ cfe-commits mailing list cfe-commits@lists.l

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14267 +assert((ArgWidth == 32 || ArgWidth == 64) && "Invalid argument width"); +if (BuiltinID == PPC::BI__builtin_altivec_vec_replace_elt) + ConstArg *= ArgWidth / 8; `// The

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Just marking this not ready to keep my queue clean until the comments are addressed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

nemanjai accepted this revision. nemanjai added a comment. The nits can be addressed when committing the code. LGTM otherwise. Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1452 // Vector Extend Sign -def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>; -def VEXTS

[PATCH] D87921: Fix -funique-internal-linkage-names to work with -O2 and new pass manager

nemanjai added a comment. In D87921#2288686 , @morehouse wrote: > The revert did not fix the PPC bots. I suspect there is some kind of > resource issue from the logs: > > msgget:: No space left on device > sysmsg.c.tmp: > /home/buildbots/ppc64le-cla

[PATCH] D87921: Fix -funique-internal-linkage-names to work with -O2 and new pass manager

nemanjai added a comment. It turns out that the culprit for the PPC bot failures is actually https://reviews.llvm.org/rG144e57fc9535 But this just took a while to manifest. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87921/new/ https://reviews.l

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3165 +static bool isEltOfVectorTy(ASTContext &Context, CallExpr *Call, Sema &S, +QualType VectorEltTy, QualType EltTy) { I think this should actually take a

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for your patience and for addressing all the comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews

[PATCH] D88105: [NFC] [PPC] Add PowerPC expected IR tests for C99 complex

nemanjai added a comment. This clearly changes behaviour and should thereby not have the `[NFC]` tag. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D88105/new/ https://reviews.llvm.org/D88105 ___ cfe-commits mailing list cfe-commits@lists.llvm

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. This is not what we want. The builtin behaves correctly. It is equivalent to the generic `__builtin_copysign` and it would be very surprising to a user if it reverses the operand

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. The remaining requests can be fulfilled when committing. I don't think this requires another review. Thanks. Comment at: clang/lib/Headers/altivec.h:7865 +#endif + retu

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

nemanjai accepted this revision. nemanjai added a comment. LGTM aside from a couple of minor nits. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13405 + // This combine is only eligible for a BUILD_VECTOR of v1i128. + // Other return types are not valid for the LXVR

[PATCH] D82485: Add tests for sequences of callbacks that RecursiveASTVisitor produces

nemanjai added a comment. Is there a way this test case can somehow be broken up into multiple files? The test case takes a very long time to compile which causes intermittent but frequent failures on one of our bots that runs on a fairly small VM. Most of the failures listed here: http://lab.

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

nemanjai added inline comments. Comment at: clang/lib/Headers/altivec.h:7743 + return __builtin_altivec_vrlqnm(__a, ((__c << ShiftMask) | +(__b << ShiftRotation))); +} While correct, this implementation will require two co

[PATCH] D90173: [PowerPC] Exploit splat instruction xxsplti32dx in Power10

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. This is not functionally correct. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9345 + return DAG.getBitcast(Op.getValueType(), SplatNode); +

[PATCH] D90329: [PowerPC] Fix va_arg in C++, Objective-C on 32-bit ELF targets

nemanjai accepted this revision. nemanjai added a comment. LGTM aside from a minor nit. Comment at: clang/lib/CodeGen/TargetInfo.cpp:4722 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64; - bool isInt = - Ty->isIntegerType() || Ty->isPointerType()

[PATCH] D92054: [Driver] Default Generic_GCC ppc/ppc64/ppc64le to -fasynchronous-unwind-tables

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Comment at: clang/test/Driver/ppc-features.cpp:45 +// PPC64: "-munwind-tables" +// PPC64-SAME: "-mfloat-abi" "hard" Curious - how come no ch

[PATCH] D93377: [Clang] Add __ibm128 type to represent ppc_fp128

nemanjai added a comment. Seems that conversion diagnostic test cases are completely missing. Comment at: clang/include/clang/Basic/TargetInfo.h:680 + /// Return the mangled code of __ibm128. + virtual const char *getIbm128Mangling() const { return "g"; } + T

[PATCH] D82485: Add tests for sequences of callbacks that RecursiveASTVisitor produces

nemanjai added a comment. Hi @gribozavr do you think we can do something about this test? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82485/new/ https://reviews.llvm.org/D82485 ___ cfe-commits mailing

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-vsx.c:1 -// REQUIRES: powerpc-registered-target +// requires: powerpc-registered-target // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -

[PATCH] D88154: Initial support for vectorization using Libmvec (GLIBC vector math library).

nemanjai added inline comments. Comment at: llvm/include/llvm/Analysis/TargetLibraryInfo.h:91 Accelerate, // Use Accelerate framework. +LIBMVEC,// GLIBC Vector Math library. MASSV, // IBM MASS vector library. fpetrogalli wrote: > Can we cal

[PATCH] D92445: [PowerPC] Add powerpcle target.

nemanjai added a comment. This seems problematic to me for a few reasons: 1. There is no 32-bit toolchains or libraries for little endian Linux systems 2. There is no support in the ELFv2 ABI for 32-bit object mode and there may be a number of places we assume that little endian systems use ELFv

[PATCH] D89986: [AIX]ignore the option -fvisibility-inlines-hidden when there is no option -fvisibility=*

nemanjai added inline comments. Comment at: clang/test/CodeGen/aix-visibility-inlines-hidden.cpp:30-34 +// COMMON-ASM: mflr 0 +// COMMON-ASM-NEXT:stw 0, 8(1) +// COMMON-ASM-NEXT:stwu 1, -64(1) +// COMMON-ASM-NEXT:bl ._Z1fv +// NOP-ASM-NEXT: nop -

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84962/new/ https://reviews.llvm.org/D84962 ___ cfe-commits mailing list cfe-commit

[PATCH] D92815: [PowerPC] [Clang] Enable float128 feature on VSX targets

nemanjai added a comment. Looks like this is causing failures at https://lab.llvm.org/buildbot/#/builders/76/builds/2422 Please revert. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92815/new/ https://reviews.llvm.org/D92815 _

[PATCH] D102191: [PowerPC] Add clang option -m[no-]prefixed

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102191/new/ https://reviews.llvm.org/D102191 __

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

nemanjai added subscribers: rjmccall, rsmith. nemanjai added a comment. In terms of the motivation for this, the description of the patch should include something along the lines of: "This is the first in a series of patches to provide builtins for compatibility with the XL compiler." Since th

[PATCH] D103125: [Clang][WIP] Allow renaming of "clang"

nemanjai created this revision. nemanjai added reviewers: rjmccall, rsmith, craig.topper, t.p.northover, arsenm, kparzysz, echristo. Herald added subscribers: usaxena95, s.egerton, kadircet, arphaman, delcypher, simoncook, mgorny. nemanjai requested review of this revision. Herald added subscribe

[PATCH] D102443: [PowerPC] Added multiple PowerPC builtins

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for implementing this. The redundant pseudo can be removed when committing. Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:2572 + [(in

[PATCH] D103235: [SPE] Disable strict-fp for SPE by default

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103235/new/ https://reviews.llvm.org/D103235 __

[PATCH] D103125: [Clang][WIP] Allow renaming of "clang"

nemanjai abandoned this revision. nemanjai added a comment. Thanks everyone for providing feedback on this. I posted this to gauge interest in the community for such a change. As it appears, the consensus seems to be that this isn't desired so I will abandon this change and vendors will continue

[PATCH] D103386: [PowerPC] Fix x86 vector intrinsics wrapper compilation under C++

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks for fixing this. Comment at: clang/lib/Headers/ppc_wrappers/xmmintrin.h:31 use vector SIMD operations. We recommend this for new applications. */ #error

[PATCH] D95634: [PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM as long as the nits are addressed on the commit. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8611 Subtarget.hasPrefixInstrs()) { -if (convertT

[PATCH] D110213: [PowerPC] Define XL-compatible macros only for AIX and Linux

nemanjai created this revision. nemanjai added reviewers: PowerPC, dim. Herald added subscribers: steven.zhang, shchenz, kbarton. nemanjai requested review of this revision. Herald added a project: clang. Since XLC only ever shipped on PowerPC AIX and Linux, it is not reasonable to provide the co

[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

nemanjai added a comment. In D104386#2979830 , @dim wrote: > In D104386#2977302 , @nemanjai > wrote: > >> The idea with putting all of these in a separate function was to: >> >> 1. Make it easy to limit it to spe

[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

nemanjai added a comment. The description says it causes issues but there is no test case. Please add the test case that causes issues. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110273/new/ https://reviews.llvm.org/D110273 ___

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

nemanjai accepted this revision. nemanjai added a comment. LGTM other than the code can be simplified as suggested. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15888-15895 +SmallVector RevOps; +unsigned NumVecs = +(BuiltinID == PPC::BI__builtin_mma_b

[PATCH] D69764: [clang-format] Add Left/Right Const fixer capability

nemanjai added a comment. This broke buildbots that have -Werror specified. I pushed in a fix in https://reviews.llvm.org/rG76d845cb169f048cb6f2176c3e7a6534dc5af097. Also, please consider formatting your commit messages to prevent wrapping. Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. There isn't enough information in the test to determine whether this adequately improves code generation (in fact, whether it improves code generation at all).

[PATCH] D110128: [Driver] Correctly handle static C++ standard library

nemanjai added a comment. In D110128#3018992 , @phosek wrote: > @MaskRay Do you think we should gate the use of this feature on > `-fbinutils-version=` or `-fuse-ld=lld`? It'd be nice if the owner of > `clang-ppc64le-rhel` builder could update the binut

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. I cannot tell without context whether the codegen changes for the `f32->i32` convert + insert case (for example `@test2` in `test/CodeGen/PowerPC/test-vector-insert.ll`) but it s

[PATCH] D106550: [PowerPC] Allow MMA built-ins to accept restrict and volatile qualified pointers

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106550/new/ https://reviews.llvm.org/D106550 __

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. I really don't understand what happened now. It seems that you have simply reverted to an older version of this patch. The test case appears to not have been pre-committed any lo

[PATCH] D110653: [PowerPC] The builtins load8r and store8r are Power 7 plus.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110653/new/ https://reviews.llvm.org/D110653 __

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109178/new/ https://reviews.llvm.org/D109178 __

[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Please note in the commit message that this is simply a wrapper for a floating point divide. XL provided this builtin because it doesn't produce software estimates by default at `-Of

[PATCH] D106191: [clang] Option control afn flag

nemanjai added a comment. Added @jansvoboda11 to the review as it appears he was the one that added the original option. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106191/new/ https://reviews.llvm.org/D106191 __

[PATCH] D110213: [PowerPC] Define XL-compatible macros only for AIX and Linux

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc9539f957f57: [PowerPC] Define XL-compatible macros only for AIX and Linux (authored by nemanjai). Changed prior to commit: https://reviews.llvm.o

[PATCH] D107899: [PowerPC] Implement builtin for vbpermd

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG09b67aa1c382: [PowerPC] Implement builtin for vbpermd (authored by nemanjai). Changed prior to commit: https://reviews.llvm.org/D107899?vs=365731&

[PATCH] D106409: [PowerPC] Truncate results for out of range values for vec_cts,vec_ctf

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. I may be wrong, but I really think this is incorrect. Please do some functional (execution) testing on this. Also, please re-title this from "truncate results" to something like

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109902/new/ https://reviews.llvm.org/D109902 ___ cfe-commits mailing list cfe-comm

[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Thanks. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110273/new/ https://reviews.llvm.org/D110273 ___ cfe-commits mailing list

[PATCH] D110824: [PowerPC] Fix to guard fetch and cas 64-bit builtin versions

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM with the test nit addressed. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c:1 +// NOTE: Assertions have been autogenerated by uti

[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM as long as you add the back end test. Comment at: clang/test/CodeGen/ppc-mma-types.c:2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py

[PATCH] D110858: [PowerPC] Implement vector float and vector double version for vec_orc builtin

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. Please run clang-format on the patch (only the modified lines). Comment at: clang/lib/Headers/altivec.h:7164 +vec_orc(vector double __a, vector double __b) { + ret

[PATCH] D110771: [PowerPC] Fix __builtin_ppc_load2r to return short instead of int.

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM as long as the sign-extending test is added. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll:52 define dso_local zeroext i16 @

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

nemanjai requested changes to this revision. nemanjai added a comment. This revision now requires changes to proceed. Can you please merge the tests into one file. There is no compelling reason to split them up and it is more difficult to review and make sense of what is going on. The test case

[PATCH] D96265: [PowerPC] Change target data layout for 16-byte stack alignment

nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Thank you for your patience. LGTM now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96265/new/ https://reviews.llvm.org/D96265 ___

[PATCH] D103615: [Clang] Add option for vector compare compatibility.

nemanjai added a comment. I haven't had time to review this yet, but I just wanted to chime in on the option spelling and description. I think we should go with: -faltivec-src-compat={xl|gcc|mixed} Source-level compatibility for Altivec vectors (for PowerPC targets). This includes resu

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