@@ -1133,6 +1133,9 @@ typedef struct __ifunc_arg_t {
#ifndef HWCAP2_SME_F64F64
#define HWCAP2_SME_F64F64 (1 << 25)
#endif
+#ifndef HWCAP2_SME_FA64
+#define HWCAP2_SME_FA64 (1 << 26)
MDevereau wrote:
This comes from here
https://github.com/torvalds/linux/blob/
@@ -491,13 +491,15 @@ bool AArch64Subtarget::isStreamingCompatible() const {
}
bool AArch64Subtarget::isNeonAvailable() const {
- return hasNEON() && !isStreaming() && !isStreamingCompatible();
+ if (hasSMEFA64())
+return true;
+ return (hasNEON() && !isStreaming() && !
@@ -491,13 +491,15 @@ bool AArch64Subtarget::isStreamingCompatible() const {
}
bool AArch64Subtarget::isNeonAvailable() const {
- return hasNEON() && !isStreaming() && !isStreamingCompatible();
+ if (hasSMEFA64())
+return true;
+ return (hasNEON() && !isStreaming() && !
@@ -508,6 +508,9 @@ def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64",
"HasSMEI16I64", "true",
def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true",
"Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>;
+def FeatureSMEFA64 : Su
@@ -162,6 +163,7 @@ enum ArchExtKind : unsigned {
AEK_FPMR = 58, // FEAT_FPMR
AEK_FP8 = 59, // FEAT_FP8
AEK_FAMINMAX = 60, // FEAT_FAMINMAX
+ AEK_SMEFA64 = 61, // FEAT_SMEFA64
MDevereau wrote:
I've moved it to be
AEK_SM
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/70809
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@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mattr=+sve -mattr=+sme-fa64 -force-streaming-compatible-sve < %s |
FileCheck %s -check-prefix=FA64
+; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/71795
Adds the builtins:
void svldr_zt(uint64_t zt, const void *rn)
void svstr_zt(uint64_t zt, void *rn)
And the intrinsics:
call void @llvm.aarch64.sme.ldr.zt(i32, ptr)
tail call void @llvm.aarch64.sme.str.zt(i32, p
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/71795
>From 9846bc9efd79e6e3c2662ea42367c102df88799d Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 10:50:05 +
Subject: [PATCH 1/2] [AArch64][SME2] Add ldr_zt, str_zt builtins and
intrinsics
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/71795
>From 9846bc9efd79e6e3c2662ea42367c102df88799d Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 10:50:05 +
Subject: [PATCH 1/3] [AArch64][SME2] Add ldr_zt, str_zt builtins and
intrinsics
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/71795
>From 9846bc9efd79e6e3c2662ea42367c102df88799d Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 10:50:05 +
Subject: [PATCH 1/4] [AArch64][SME2] Add ldr_zt, str_zt builtins and
intrinsics
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/71795
>From 9846bc9efd79e6e3c2662ea42367c102df88799d Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 10:50:05 +
Subject: [PATCH 1/4] [AArch64][SME2] Add ldr_zt, str_zt builtins and
intrinsics
MDevereau wrote:
Well spotted - I forgot to delete these. Removed
https://github.com/llvm/llvm-project/pull/71795
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https://github.com/llvm/llvm-project/pull/71953
Extend pfalse and ptrue builtins with svcount_t return types to be enabled for
sve2p1 and sme2
>From 79c05d1f8554d5a4469b9501b61b47863f086ffa Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 10 Nov 202
@@ -1992,3 +1986,12 @@ let TargetGuard = "sme2" in {
def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl",
MergeNon
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None
>From e03469125d082973451da609ad5edfd3065d94a5 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 16:08:57 +
Subject: [PATCH] Add SME2 builtins for zero { zt0 }
---
clang/include/cla
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/72274
>From e6240fa09aca504a9340ff7bfd88ad449d5775da Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 16:08:57 +
Subject: [PATCH] Add SME2 builtins for zero { zt0 }
Patch by: Kerry McLaughlin k
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@@ -321,9 +321,18 @@ let TargetGuard = "sme2" in {
let TargetGuard = "sme2" in {
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
def SVSTR_ZT : Ins
@@ -0,0 +1,280 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/74303
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https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/74450
Adds builtins for:
- FCVT
- BFCVT
- FCVTZS
- FCVTZU
- SCVTF
- UCVTF
- BFCVTN
- FCVTN
- SQCVT
- SQCVTU
- UQCVT
- SQCVTN
- SQCVTUN
- UQCVTN
See https://github.com/ARM-software/acle/pull/217
>From 07244773d073390
@@ -0,0 +1,233 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone
@@ -1864,6 +1866,35 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
+unsigned Nu
@@ -0,0 +1,1889 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llv
@@ -0,0 +1,1889 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llv
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/73317
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>From aaf7270f50c7deaebb34acab636cd1e40e872477 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/4] [SME2] Add LUTI2 and LUTI4 single Builtins and Intrinsics
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>From cb6e6b5c6fe76a2b4a3bd1d78f4f7cec82d84067 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 10 Nov 2023 13:40:31 +
Subject: [PATCH 1/3] Add SME2 builtins for pfalse and ptrue
Extend pfalse and p
@@ -1981,6 +1979,11 @@ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i",
"QcQsQiQl", MergeNone, "aarch64_sv
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
}
+let TargetGuard = "sve2p1|sme2" in {
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl",
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
https://github.com/MDevereau closed
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>From cb6e6b5c6fe76a2b4a3bd1d78f4f7cec82d84067 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 10 Nov 2023 13:40:31 +
Subject: [PATCH 1/4] Add SME2 builtins for pfalse and ptrue
Extend pfalse and p
@@ -15,7 +17,7 @@
// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
// CPP-CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svptrue_c8(void) {
+svcount_t test_svptrue_c8(void) __arm_streaming_compatibl
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73304
>From aaf7270f50c7deaebb34acab636cd1e40e872477 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/4] [SME2] Add LUTI2 and LUTI4 single Builtins and Intrinsics
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/73304
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>From 79c05d1f8554d5a4469b9501b61b47863f086ffa Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 10 Nov 2023 13:40:31 +
Subject: [PATCH 1/2] Add SME2 builtins for pfalse and ptrue
Extend pfalse and p
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
@@ -1981,6 +1979,11 @@ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i",
"QcQsQiQl", MergeNone, "aarch64_sv
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
}
+let TargetGuard = "sve2p1|sme2" in {
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl",
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@@ -1363,6 +1367,8 @@ static void __init_cpu_features_constructor(unsigned long
hwcap,
setCPUFeature(FEAT_SME_I64);
if (hwcap2 & HWCAP2_SME_F64F64)
setCPUFeature(FEAT_SME_F64);
+ if (hwcap2 & HWCAP2_SME_FA64)
+setCPUFeature(FEAT_SME_FA64);
MDeve
@@ -298,3 +298,48 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+// SME2 - MOVA
+
+//
+// 2 and 4 vector-group read/write intrinsics.
MDevereau wrote:
Opinion: Given you've defined write and read separately you should
@@ -0,0 +1,57 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN:-target-feature +sve2 -target-feature +sme2 -target-feature +sve
-fsyntax-only -verify %s
MDevereau wrote:
Can `-target-feature +sve2` be deleted?
https://github.com/llvm/llvm-pro
@@ -298,3 +298,48 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+// SME2 - MOVA
+
+//
+// 2 and 4 vector-group read/write intrinsics.
+//
+
+multiclass WriteHV_VG checks> {
+ let TargetGuard = "sme2" in {
+def NAME # _VG2_H : Inst<
@@ -508,6 +508,9 @@ def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64",
"HasSMEI16I64", "true",
def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true",
"Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>;
+def FeatureSMEFA64 : Su
@@ -1363,6 +1367,8 @@ static void __init_cpu_features_constructor(unsigned long
hwcap,
setCPUFeature(FEAT_SME_I64);
if (hwcap2 & HWCAP2_SME_F64F64)
setCPUFeature(FEAT_SME_F64);
+ if (hwcap2 & HWCAP2_SME_FA64)
+setCPUFeature(FEAT_SME_FA64);
MDeve
MDevereau wrote:
@mikaelholmen Thanks. I've reverted the patch
https://github.com/llvm/llvm-project/pull/71795
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https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/72849
Use ZTR instead of MatrixOP to prevent expensive test check and machine
verifier failures.
>From e1685cc0dea9501a993cbe3f8185a40e1f285591 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 10
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/72849
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>From 3b1d34afb1ae365f48716ae5eb9202a474adf234 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 10:49:27 +
Subject: [PATCH] [AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics
---
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/72849
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>From 3b1d34afb1ae365f48716ae5eb9202a474adf234 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 10:49:27 +
Subject: [PATCH 1/2] [AArch64][SME2] Add ldr_zt, str_zt builtins and
intrinsics
@@ -2,6 +2,8 @@
// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -m
@@ -491,13 +491,13 @@ bool AArch64Subtarget::isStreamingCompatible() const {
}
bool AArch64Subtarget::isNeonAvailable() const {
- return hasNEON() && !isStreaming() && !isStreamingCompatible();
+ return (hasNEON() || hasSMEFA64()) && !isStreaming() &&
MDever
@@ -508,6 +508,9 @@ def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64",
"HasSMEI16I64", "true",
def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true",
"Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>;
+def FeatureSMEFA64 : Su
@@ -1363,6 +1364,8 @@ static void __init_cpu_features_constructor(unsigned long
hwcap,
setCPUFeature(FEAT_SME_I64);
if (hwcap2 & HWCAP2_SME_F64F64)
setCPUFeature(FEAT_SME_F64);
+ if (hwcap2 & HWCAP2_SME_FA64)
MDevereau wrote:
I've defined it now.
@@ -248,8 +250,9 @@ inline constexpr ExtensionInfo Extensions[] = {
{"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD,
"+fp-armv8,+neon", 100},
{"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4,
"+sm4,+fp-armv8,+neon", 60},
{"sme-f16f16", AArch64::AEK_SMEF1
@@ -1133,6 +1133,9 @@ typedef struct __ifunc_arg_t {
#ifndef HWCAP2_SME_F64F64
#define HWCAP2_SME_F64F64 (1 << 25)
#endif
+#ifndef HWCAP2_SME_FA64
+#define HWCAP2_SME_FA64 (1 << 26)
MDevereau wrote:
Where did you get 30 from?
https://github.com/llvm/llvm-proj
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/70809
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@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN:-target-feature +sve2 -target-feature +sme2 -target-feature +sve
-fsyntax-only -verify %s
+
+// REQUIRES: aarch64-registered-target
+
+#include
+
+void test_outer_product(svbool_t pred, svint16_t s
@@ -298,3 +298,19 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// Outer produce and accumulate/subtract
+//
+
+let TargetGuard = "sme2" in {
+ def SVSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "s", MergeNone,
"aarch64_sme_smo
@@ -0,0 +1,170 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
MDevereau wrote:
Hi Dinar, I can see you've added FCLAMP to #72487. Given these builtins are all
defined in the same section in the acle
[here](https://github.com/ARM-software/acle/pull/217/files#diff-516526d4a18101dc85300bc2033d0f86dc46c505b7510a7694baabea851aedfaR11371-R11394)
I think it wou
https://github.com/MDevereau created
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See https://github.com/ARM-software/acle/pull/217
Patch by: Hassnaa Hamdi
>From bca5297fe897edf6faf51ffde3e8fe1baa26b148 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Sub
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/73305
See https://github.com/ARM-software/acle/pull/217
Patch by: Hassnaa Hamdi
>From 5aba2f1d2fe34f721a8e85eef6eecc25cb60851f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Sub
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/73317
See https://github.com/ARM-software/acle/pull/217
Patch by: Hassnaa Hamdi
>From f5b909e24e3cea49d98b40797880e4329a7a1e4f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Sub
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73305
>From 5aba2f1d2fe34f721a8e85eef6eecc25cb60851f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/2] [SME2] Add LUTI2 and LUTI4 double Builtins and Intrinsics
@@ -1,10 +1,17 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1
@@ -1859,19 +1859,28 @@ def SVBGRP : SInst<"svbgrp[_{d}]", "ddd",
"UcUsUiUl", MergeNone, "aarch64_sv
def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone,
"aarch64_sve_bgrp_x">;
}
+let TargetGuard = "sve2p1|sme" in {
MDevereau wrote:
```s
@@ -5,6 +5,11 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s |
FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-li
https://github.com/MDevereau approved this pull request.
https://github.com/llvm/llvm-project/pull/71176
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https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73317
>From f5b909e24e3cea49d98b40797880e4329a7a1e4f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/3] [SME2] Add LUTI2 and LUTI4 quad Builtins and Intrinsics
Se
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73317
>From f5b909e24e3cea49d98b40797880e4329a7a1e4f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/4] [SME2] Add LUTI2 and LUTI4 quad Builtins and Intrinsics
Se
@@ -5098,6 +5099,12 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
AArch64::LUTI2_4ZTZI_S}))
// Second Immediate must be <= 3:
SelectMultiVectorLuti<3>(Node, 4, Opc);
+ else if (auto Opc = SelectOpcodeFromVT(
MDevereau w
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/73317
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https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73305
>From 5aba2f1d2fe34f721a8e85eef6eecc25cb60851f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/3] [SME2] Add LUTI2 and LUTI4 double Builtins and Intrinsics
@@ -1666,7 +1674,8 @@ static unsigned SelectOpcodeFromVT(EVT VT,
ArrayRef Opcodes) {
return 0;
break;
case SelectTypeKind::FP:
-if (EltVT != MVT::f16 && EltVT != MVT::f32 && EltVT != MVT::f64)
+if (EltVT != MVT::bf16 && EltVT != MVT::f16 && EltVT != MVT::f3
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73317
>From f5b909e24e3cea49d98b40797880e4329a7a1e4f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/5] [SME2] Add LUTI2 and LUTI4 quad Builtins and Intrinsics
Se
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73304
>From bca5297fe897edf6faf51ffde3e8fe1baa26b148 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/3] [SME2] Add LUTI2 and LUTI4 single Builtins and Intrinsics
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/73305
>From 5aba2f1d2fe34f721a8e85eef6eecc25cb60851f Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/5] [SME2] Add LUTI2 and LUTI4 double Builtins and Intrinsics
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/72849
>From 3b1d34afb1ae365f48716ae5eb9202a474adf234 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 10:49:27 +
Subject: [PATCH 1/3] [AArch64][SME2] Add ldr_zt, str_zt builtins and
intrinsics
@@ -0,0 +1,51 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
@@ -2748,6 +2748,22 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
+MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
+ MachineBasicBlock
*B
MDevereau wrote:
> It looks like a few other pull requests are changing the same code around
> ImmToTile. Might be good to land this smaller patch first so you can rebase
> the others and reduce the diffs!
The idea was that the changes to `ImmToTile` were small and any of my in-flight
PRs cou
@@ -0,0 +1,280 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
+
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/73317
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https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/72849
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https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/72274
>From 86c61659cf99486965dffe201385b28420e93f41 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 16:08:57 +
Subject: [PATCH 1/3] Add SME2 builtins for zero { zt0 }
Patch by: Kerry McLaughl
@@ -305,4 +305,9 @@ defm SVSUB : ZAAddSub<"sub">;
let TargetGuard = "sme2" in {
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
def SVSTR_ZT : Inst
@@ -2746,19 +2746,25 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
-MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
- MachineBasicBlock
*
@@ -2746,19 +2746,25 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
-MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
- MachineBasicBlock
*
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/72274
>From 86c61659cf99486965dffe201385b28420e93f41 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 16:08:57 +
Subject: [PATCH 1/4] Add SME2 builtins for zero { zt0 }
Patch by: Kerry McLaughl
@@ -0,0 +1,23 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/72274
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