================
@@ -2748,6 +2748,22 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
+MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
+ MachineBasicBlock
*BB,
+ bool IsSpill) const {
+ const TargetInstrInfo *TII = Subtarget->getInstrInfo();
+ MachineInstrBuilder MIB;
+ if (IsSpill) {
----------------
MDevereau wrote:
This isn't quite equivalent as the different methods will implicitly define
registers in different manners causing the added tests in this patch to fail
the machine-verifier pass. However adding the line
`auto Rs = IsSpill ? RegState::Kill : RegState::Define;`
in addition to your suggestion works as intended.
https://github.com/llvm/llvm-project/pull/72849
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