[clang] ff13189 - [RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

Author: Kito Cheng Date: 2021-10-17T16:25:23+08:00 New Revision: ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92 URL: https://github.com/llvm/llvm-project/commit/ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92 DIFF: https://github.com/llvm/llvm-project/commit/ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92.diff LO

[clang] 8efa651 - [RISCV][NFC] Fix build error

Author: Kito Cheng Date: 2021-10-17T16:38:53+08:00 New Revision: 8efa6512e0662b813ab783ed937768cef28e5a8b URL: https://github.com/llvm/llvm-project/commit/8efa6512e0662b813ab783ed937768cef28e5a8b DIFF: https://github.com/llvm/llvm-project/commit/8efa6512e0662b813ab783ed937768cef28e5a8b.diff LO

[clang] [RISCV][FMV] Support target_clones (PR #85786)

@@ -2877,10 +2877,143 @@ void CodeGenFunction::EmitMultiVersionResolver( case llvm::Triple::aarch64: EmitAArch64MultiVersionResolver(Resolver, Options); return; + case llvm::Triple::riscv32: + case llvm::Triple::riscv64: +EmitRISCVMultiVersionResolver(Resolver,

[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/96465 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Introduce CodeGenModule::calcRISCVZicfilpFuncSigLabel() (PR #111661)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/111661 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Introduce CodeGenModule::calcRISCVZicfilpFuncSigLabel() (PR #111661)

https://github.com/kito-cheng commented: I would suggest either put more thing to make this PR test-able or write a unittest for this. https://github.com/llvm/llvm-project/pull/111661 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lis

[clang] [clang][RISCV] Introduce CodeGenModule::calcRISCVZicfilpFuncSigLabel() (PR #111661)

@@ -2829,6 +2829,56 @@ void CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD, F->addTypeMetadata(0, llvm::ConstantAsMetadata::get(CrossDsoTypeId)); } +uint32_t +CodeGenModule::calcRISCVZicfilpFuncSigLabel(const FunctionType &FT, +

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/112477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

https://github.com/kito-cheng commented: Test? https://github.com/llvm/llvm-project/pull/112477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -2022,6 +2035,22 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Name; } + if (const Arg *const A = Args.getLastArg(OPT_fcf_branch_label_scheme_EQ)) { -

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -3952,6 +3981,16 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, } } + if (const Arg *const A = Args.getLastArg(OPT_fcf_branch_label_scheme_EQ)) { kito-cheng wrote: ```suggestion if (const Arg *A = Args.getLastArg(OPT_

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -1781,3 +1781,35 @@ // RUN: %clang --target=riscv64-unknown-linux-gnu -mcpu=sifive-p450 -E -dM %s \ // RUN: -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST // CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1 + +// Landing Pad + +// RUN: %clang --target=riscv32 -men

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -2841,6 +2841,10 @@ def fcf_protection : Flag<["-"], "fcf-protection">, Group, Visibility<[ClangOption, CLOption, CC1Option]>, Alias, AliasArgs<["full"]>, HelpText<"Enable cf-protection in 'full' mode">; +def fcf_branch_label_scheme_EQ : Joined<["-"], "fcf-branch-labe

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

https://github.com/kito-cheng commented: BTW, the LLVM using one PR one commit policy, it only allow `squash and merge`, so I would suggest you split this into 3 PR. https://github.com/llvm/llvm-project/pull/109600 ___ cfe-commits mailing list cfe-com

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -0,0 +1,90 @@ +// Default cf-branch-label-scheme is func-sig +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zicfilp1p0 -fcf-protection=branch -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-ZICFILP-FUNC-SIG %s +// RUN: %

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/109600 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -0,0 +1,90 @@ +// Default cf-branch-label-scheme is func-sig +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zicfilp1p0 -fcf-protection=branch -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-ZICFILP-FUNC-SIG %s +// RUN: %

[clang] [clang][RISCV] Introduce command line options for RISC-V Zicfilp CFI (PR #109784)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/109784 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Introduce command line options for RISC-V Zicfilp CFI (PR #109784)

kito-cheng wrote: Could you update this PR? https://github.com/llvm/llvm-project/pull/109600/commits/4579272e057e6ec77a2a660384080e1f57a17cf0 is generally LGTM, but I assume this should process within this PR :) https://github.com/llvm/llvm-project/pull/109784

[clang] [clang][RISCV] Introduce command line options for RISC-V Zicfilp CFI (PR #109784)

https://github.com/kito-cheng approved this pull request. Still LGTM https://github.com/llvm/llvm-project/pull/109784 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

kito-cheng wrote: > @kito-cheng I need your input on this, since this would require a few updates > on various PRs to the RISC-V specs. Yeah, I just chat with Craig, I think that right way to go, and actually the PR in riscv-toolchain-conventions I has implicitly allow that, I mean I only writ

[clang] [Clang][RISCV] Support -fcf-protection=return for RISC-V (PR #112477)

@@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -triple riscv64-linux-unknown -target-feature +zimop -emit-llvm -o - %s -fcf-protection=return | FileCheck %s +// RUN: %clang_cc1 -triple riscv64-linux-unknown -target-feature +zimop -emit-llvm -o - %s | FileCheck -check-prefix=NOSHADOWSTACK %

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -32,3 +36,39 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) { __riscv_vse32_v_i32m1(base, val, vl); return ret; } + +// CHECK-LLVM: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce) +// CHECK-LLVM-ABI-VLEN: define dso_loca

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -32,3 +36,39 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) { __riscv_vse32_v_i32m1(base, val, vl); return ret; } + +// CHECK-LLVM: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce) +// CHECK-LLVM-ABI-VLEN: define dso_loca

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -32,3 +36,39 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) { __riscv_vse32_v_i32m1(base, val, vl); return ret; } + +// CHECK-LLVM: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce) +// CHECK-LLVM-ABI-VLEN: define dso_loca

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

@@ -519,9 +650,24 @@ void baremetal::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back(Arch == llvm::Triple::aarch64_be ? "-EB" : "-EL"); } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, - options::OPT_r

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

@@ -503,12 +624,22 @@ void baremetal::Linker::ConstructJob(Compilation &C, const JobAction &JA, const llvm::Triple::ArchType Arch = TC.getArch(); const llvm::Triple &Triple = getToolChain().getEffectiveTriple(); - AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA); + if (!D

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -1953,7 +1953,7 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase { /// Extra information which affects how the function is called, like /// regparm and the calling convention. LLVM_PREFERRED_TYPE(CallingConv) -unsigned ExtInfo : 13; +

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -3013,6 +3013,7 @@ enum CXCallingConv { CXCallingConv_M68kRTD = 19, CXCallingConv_PreserveNone = 20, CXCallingConv_RISCVVectorCall = 21, + CXCallingConv_RISCVVLSCall = 22, kito-cheng wrote: Just use different calling convention to distinguish, then i

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/kito-cheng approved this pull request. LGTM :) https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Merging RISCVToolChain and BareMetal toolchains (PR #118809)

kito-cheng wrote: I would suggest to break this PR into several small pieces, the clang/test folder should not having too much change during the merging, especially I feel not conformable changing the non-RISC-V file within this PR, I expect those change should happened in a separated patch.

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -5220,6 +5248,30 @@ bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC, case ParsedAttr::AT_RISCVVectorCC: CC = CC_RISCVVectorCall; break; + case ParsedAttr::AT_RISCVVLSCC: { +// If the riscv_abi_vlen doesn't have any argument, we set se

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -359,9 +405,153 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( return ABIArgInfo::getCoerceAndExpand(CoerceToType, UnpaddedCoerceToType); } +bool RISCVABIInfo::detectVLSCCEligibleStruct(QualType Ty, unsigned ABIVLen, +

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -359,9 +405,153 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( return ABIArgInfo::getCoerceAndExpand(CoerceToType, UnpaddedCoerceToType); } +bool RISCVABIInfo::detectVLSCCEligibleStruct(QualType Ty, unsigned ABIVLen, +

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -5220,6 +5248,30 @@ bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC, case ParsedAttr::AT_RISCVVectorCC: CC = CC_RISCVVectorCall; break; + case ParsedAttr::AT_RISCVVLSCC: { +// If the riscv_abi_vlen doesn't have any argument, we set se

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -5220,6 +5248,30 @@ bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC, case ParsedAttr::AT_RISCVVectorCC: CC = CC_RISCVVectorCall; break; + case ParsedAttr::AT_RISCVVLSCC: { +// If the riscv_abi_vlen doesn't have any argument, we set se

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -359,9 +405,153 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( return ABIArgInfo::getCoerceAndExpand(CoerceToType, UnpaddedCoerceToType); } +bool RISCVABIInfo::detectVLSCCEligibleStruct(QualType Ty, unsigned ABIVLen, +

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -111,9 +115,51 @@ void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr, } void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { + unsigned ABIVLen; + switch (FI.getExtInfo().getCC()) { + default: +ABIVLen = 1; kito-cheng wrote: Always

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -4992,7 +4992,6 @@ def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group, !eq(GlobalDocumentation.Program, "Flang") : "", true: " The value will be reflected in __riscv_v_fixed_vlen preprocessor define"), " (RISC-V only)")>; -

[clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)

@@ -335,6 +335,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-svukte`` LLVM implements the `0.3 draft specification `__. +``experimental-p``, ``experimental-p`` -

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

kito-cheng wrote: (Disclaimer: I am not intend to ignite the flames of war about the ISA string canonicalization!) Give few more background behind the PR, the issue we want to resolve is the multilib issue: we starting using `zc*` extension, but we also have user for using `c` extension, howe

[clang] [llvm] [RISCV] SiFive CLIC Support (PR #132481)

@@ -486,6 +486,24 @@ def : SysReg<"mctrctl", 0x34e>; // Vendor CSRs //===--- +// XSfmclic +let FeaturesRequired = [{ {RISCV::FeatureVendorXSfmclic} }] in { +def : SysReg<"mtvt", 0x307>; +def : SysReg<"mnxti", 0x345>; +def : SysReg<"m

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,34 @@ +# XAndesPerf - Andes Performance Extension +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesperf -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesperf < %s \ +# RUN

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,105 @@ +# XAndesPerf - Andes Performance Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesperf -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesperf < %s \ +# RU

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,105 @@ +# XAndesPerf - Andes Performance Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesperf -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesperf < %s \ +# RU

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,105 @@ +# XAndesPerf - Andes Performance Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesperf -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesperf < %s \ +# RU

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,34 @@ +# XAndesPerf - Andes Performance Extension +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesperf -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesperf < %s \ +# RUN

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/135110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/kito-cheng commented: I am really happy to see this finally start to upstream as ex-Ande guy :P --- Do you have plan send PR to https://github.com/riscv-non-isa/riscv-toolchain-conventions? https://github.com/llvm/llvm-project/pull/135110 ___

[clang] [llvm] [RISCV] SiFive CLIC Support (PR #132481)

https://github.com/kito-cheng approved this pull request. LGTM :) https://github.com/llvm/llvm-project/pull/132481 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/135110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix generation of DWARF info for vector segmented types (PR #137941)

https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/137941 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix generation of DWARF info for vector segmented types (PR #137941)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/137941 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Introduce preprocessor macro when Zicfiss-based shadow stack is enabled (PR #127592)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/127592 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][test] Fix -DBUILD_SHARED_LIBS build by adding depency on Targ… (PR #130105)

https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/130105 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Fix wrong VLS CC detection (PR #130107)

https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/130107 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -238,6 +238,25 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, else Builder.defineMacro("__riscv_32e"); } + + if (Opts.CFProtectionBranch) { +auto Scheme = Opts.getCFBranchLabelScheme(); +if (Scheme == CFBranchLabelSchemeKind::Default

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

https://github.com/kito-cheng commented: Just last one comment from me https://github.com/llvm/llvm-project/pull/109600 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/109600 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

@@ -1196,36 +1196,93 @@ SmallVector parsePrototypes(StringRef Prototypes) { return PrototypeDescriptors; } +#define STRINGIFY(NAME) \ + case NAME: \ +

[clang] [clang][RISCV] Fix RUN line and rename test name for pr129995 (PR #132676)

https://github.com/kito-cheng approved this pull request. https://github.com/llvm/llvm-project/pull/132676 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

@@ -25,8 +25,8 @@ addi a0, a1, 0 # CHECK: # encoding: [0xe0,0x1f] addi s0, sp, 1020 -# CHECK: .option arch, -c -.option arch, -c +# CHECK: .option arch, -c, -zca +.option arch, -c, -zca kito-cheng wrote: I guess `.opt arch, -zca` won't work because C will im

[clang] [Clang][RISCV] Add preprocessor macros for Zicfilp CFI scheme (PR #109600)

@@ -238,6 +238,25 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, else Builder.defineMacro("__riscv_32e"); } + + if (Opts.CFProtectionBranch) { +auto Scheme = Opts.getCFBranchLabelScheme(); +if (Scheme == CFBranchLabelSchemeKind::Default

[clang] [llvm] [clang][RISCV] Emit RISCV function-signature-based CFI label in llvm::Function metadata (PR #111661)

kito-cheng wrote: > I prefer to keep the function signature as an auxiliary metadata with the > name riscv_lpad_func_sig, so future schemes and other language frontends can > reuse the riscv_lpad_label metadata flow and have the opportunity of not > being forced to adopt the idea of function s

[clang] [llvm] [RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 (PR #141007)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/141007 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/kito-cheng commented: I thought it should have xandesperf extension? https://github.com/llvm/llvm-project/pull/140681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang][RISCV] Emit RISCV function-signature-based CFI label in llvm::Function metadata (PR #111661)

https://github.com/kito-cheng commented: A high level suggestion is don't hash that until MC layer, so that we can easier debug and observe that from the IR level, so that means we can drop the hash part from this PR. https://github.com/llvm/llvm-project/pull/111661 ___

[clang] [Clang][RISCV] Add Zicfilp CFI unlabeled scheme preprocessor macros (PR #109600)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/109600 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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