john.brawn created this revision.
john.brawn added reviewers: klimek, kfunk, milianw, rsmith.
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Currently when an AST plugin is loaded it must then be enabled by passing
-plugin pluginname or -ad
john.brawn added a comment.
Looking at http://reviews.llvm.org/D15729 I //think// there's no conflict
between what this patch is doing and what that patch is doing. If a plugin
returns AddBeforeMainAction or AddAfterMainAction then when ASTUnit in libclang
loads that plugin it should get automa
Author: john.brawn
Date: Tue Mar 15 07:51:40 2016
New Revision: 263546
URL: http://llvm.org/viewvc/llvm-project?rev=263546&view=rev
Log:
Make it possible for AST plugins to enable themselves by default
Currently when an AST plugin is loaded it must then be enabled by passing
-plugin pluginname or
This revision was automatically updated to reflect the committed changes.
Closed by commit rL263546: Make it possible for AST plugins to enable
themselves by default (authored by john.brawn).
Changed prior to commit:
http://reviews.llvm.org/D17959?vs=50037&id=50717#toc
Repository:
rL LLVM
h
john.brawn created this revision.
john.brawn added reviewers: bkramer, rsmith, rnk.
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john.brawn set the repository for this revision to rL LLVM.
This allows plugins which add AST passes to also define pragmas to do things
like only enable certain behavio
@@ -855,6 +863,25 @@ __rndrrs(uint64_t *__p) {
}
#endif
+/* 11.2 Guarded Control Stack intrinsics */
+#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
+static __inline__ void * __attribute__((__always_inline__, __nodebug__))
+__gcspr() {
+ return (void *)__builtin_arm_rsr6
john-brawn-arm wrote:
/cherry-pick b32aac4 c649194 3952910
https://github.com/llvm/llvm-project/pull/99335
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@@ -8,8 +8,8 @@ struct S0 {
// CHECK-LABEL: define dso_local void @_Z3fS0v
// CHECK:alloca %struct.S0, align 4
// CHECK-NEXT:[[TMP0:%.*]] = alloca %struct.S0, align 4
-// CHECK: call void @llvm.dbg.declare(metadata ptr [[TMP0]], metadata
[[S
https://github.com/john-brawn-arm created
https://github.com/llvm/llvm-project/pull/94632
Currently we use DW_OP_plus_uconst to handle the bitfield offset and handle the
bitfield size by choosing a type size that matches, but this doesn't work if
either offset or size aren't byte-aligned. Extr
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/94632
>From c490a8c7d16e03066a3a4ef4985fa64fb28d Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Thu, 14 Mar 2024 16:17:03 +
Subject: [PATCH] [DebugInfo] Change handling of structured bindings of
bitfie
https://github.com/john-brawn-arm ready_for_review
https://github.com/llvm/llvm-project/pull/94632
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https://github.com/john-brawn-arm edited
https://github.com/llvm/llvm-project/pull/94632
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https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/94632
>From c490a8c7d16e03066a3a4ef4985fa64fb28d Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Thu, 14 Mar 2024 16:17:03 +
Subject: [PATCH] [DebugInfo] Change handling of structured bindings of
bitfie
https://github.com/john-brawn-arm closed
https://github.com/llvm/llvm-project/pull/94632
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john-brawn-arm wrote:
After doing some more testing it turns out that DW_OP_bit_piece actually
doesn't work when we have a signed bitfield, as both gdb and lldb treat the
upper bits as zero. I think instead we have to do a sequence of operations to
extract the relevant bits from the value. I'v
https://github.com/john-brawn-arm closed
https://github.com/llvm/llvm-project/pull/85665
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john-brawn-arm wrote:
Ping
https://github.com/llvm/llvm-project/pull/99335
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https://github.com/john-brawn-arm created
https://github.com/llvm/llvm-project/pull/99335
AArch64 GCS (Guarded Control Stack) is similar enough to CET that we can re-use
the existing code that is guarded by _LIBUNWIND_USE_CET, so long as we also add
defines to locate the GCS stack and pop the
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/99335
>From e0f71863bd2f797c9208bdfc559bb69ade5a653a Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Wed, 17 Jul 2024 15:18:46 +0100
Subject: [PATCH 1/3] [libunwind] Add GCS support for AArch64
AArch64 GCS (Gua
@@ -8,8 +8,8 @@ struct S0 {
// CHECK-LABEL: define dso_local void @_Z3fS0v
// CHECK:alloca %struct.S0, align 4
// CHECK-NEXT:[[TMP0:%.*]] = alloca %struct.S0, align 4
-// CHECK: call void @llvm.dbg.declare(metadata ptr [[TMP0]], metadata
[[S
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/96903
>From 123ebe17131fcfc7662be6759327b311e90fb16d Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Tue, 25 Jun 2024 15:35:18 +0100
Subject: [PATCH 1/3] [AArch64] Implement GCS ACLE intrinsics
This adds intrin
john-brawn-arm wrote:
I've added a new change to work around a problem in intrinsic handling that's
detailed in
https://discourse.llvm.org/t/intrinsic-with-sideeffect-is-optimized-out/66053
(I previously had this workaround in, but removed it because it looked like it
was no longer needed, bu
john-brawn-arm wrote:
> Thanks, LGTM.
>
> As a follow-up, can you check that the instructions generated from this
> builtin do inhibit the machine outliner? Maybe all GCS-modifying functions
> have to inhibit the machine outliner, I'm not 100% sure.
The GCS instructions don't inhibit the mach
https://github.com/john-brawn-arm closed
https://github.com/llvm/llvm-project/pull/96903
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john-brawn-arm wrote:
Ping.
https://github.com/llvm/llvm-project/pull/85665
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https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/85665
>From 665d4034a1428d9b5cf1c4d4e89a16fa00b94fb5 Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Thu, 14 Mar 2024 16:17:03 +
Subject: [PATCH 1/2] [DebugInfo] Use DW_op_bit_piece for structured bindings
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/85665
>From 665d4034a1428d9b5cf1c4d4e89a16fa00b94fb5 Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Thu, 14 Mar 2024 16:17:03 +
Subject: [PATCH 1/3] [DebugInfo] Use DW_op_bit_piece for structured bindings
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/85665
>From 665d4034a1428d9b5cf1c4d4e89a16fa00b94fb5 Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Thu, 14 Mar 2024 16:17:03 +
Subject: [PATCH 1/4] [DebugInfo] Use DW_op_bit_piece for structured bindings
@@ -6178,10 +6178,16 @@ The current supported opcode vocabulary is limited:
the last entry from the second last entry and appends the result to the
expression stack.
- ``DW_OP_plus_uconst, 93`` adds ``93`` to the working expression.
-- ``DW_OP_LLVM_fragment, 16, 8`` specifi
@@ -6178,10 +6178,16 @@ The current supported opcode vocabulary is limited:
the last entry from the second last entry and appends the result to the
expression stack.
- ``DW_OP_plus_uconst, 93`` adds ``93`` to the working expression.
-- ``DW_OP_LLVM_fragment, 16, 8`` specifi
@@ -6178,10 +6178,16 @@ The current supported opcode vocabulary is limited:
the last entry from the second last entry and appends the result to the
expression stack.
- ``DW_OP_plus_uconst, 93`` adds ``93`` to the working expression.
-- ``DW_OP_LLVM_fragment, 16, 8`` specifi
@@ -6178,10 +6178,16 @@ The current supported opcode vocabulary is limited:
the last entry from the second last entry and appends the result to the
expression stack.
- ``DW_OP_plus_uconst, 93`` adds ``93`` to the working expression.
-- ``DW_OP_LLVM_fragment, 16, 8`` specifi
https://github.com/john-brawn-arm milestoned
https://github.com/llvm/llvm-project/pull/99335
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john-brawn-arm wrote:
Sorry to pester you about this, but would it be possible to get this approved
in time for LLVM19 RC2 on Monday? This is the last piece of GCS work and it
would be nice to have it all in a single LLVM release.
https://github.com/llvm/llvm-project/pull/99335
___
john-brawn-arm wrote:
> LGTM. Sorry for the delay.
>
> Q: Is there a way to play with the GCS feature in a VM? Do you have setup
> instructions?
https://git.yoctoproject.org/meta-arm/log/?h=testing/gcs is a demonstration
embedded linux that support GCS, including an emulator capable of runnin
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/99335
>From e0f71863bd2f797c9208bdfc559bb69ade5a653a Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Wed, 17 Jul 2024 15:18:46 +0100
Subject: [PATCH 1/4] [libunwind] Add GCS support for AArch64
AArch64 GCS (Gua
https://github.com/john-brawn-arm closed
https://github.com/llvm/llvm-project/pull/99335
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john-brawn-arm wrote:
> This seems to add a new feature, is it really relevant for a backport?
This is the last piece of work to enable GCS in the LLVM toolchain (clang and
lld support went in a while ago), and I was hoping to get everything in to LLVM
19. It would be rather annoying to have t
john-brawn-arm wrote:
/cherry-pick b32aac4358c1f6639de7c453656cd74fbab75d71
https://github.com/llvm/llvm-project/pull/99335
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john-brawn-arm wrote:
> Looks like this breaks building on Android:
> https://ci.chromium.org/ui/p/chromium/builders/try/android-arm64-rel/680348/overview
Looks like Android here is being built with
clang-llvmorg-19-init-14561-gecea8371-3004.tar.xz which looks like it's built
from commit http
https://github.com/john-brawn-arm created
https://github.com/llvm/llvm-project/pull/101973
We need both GCS to be enabled by the compiler (which we do by checking if
__ARM_FEATURE_GCS_DEFAULT is defined) and for arm_acle.h to define the GCS
intrinsics. Check the latter by checking if _CHKFEAT_
john-brawn-arm wrote:
https://github.com/llvm/llvm-project/pull/101973 for being more careful about
enabling GCS.
https://github.com/llvm/llvm-project/pull/99335
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@@ -680,7 +680,7 @@
DEFINE_LIBUNWIND_FUNCTION(__libunwind_Registers_arm64_jumpto)
ldrx16, [x0, #0x0F8]
ldpx0, x1, [x0, #0x000] // restore x0,x1
movsp,x16 // restore sp
- retx30// jump to pc
john-
https://github.com/john-brawn-arm created
https://github.com/llvm/llvm-project/pull/102322
The libunwind assembly files need adjustment in order to work correctly when
both BTI and GCS are both enabled (which will be the case when using
-mbranch-protection=standard):
* __libunwind_Registers_a
@@ -680,7 +680,7 @@
DEFINE_LIBUNWIND_FUNCTION(__libunwind_Registers_arm64_jumpto)
ldrx16, [x0, #0x0F8]
ldpx0, x1, [x0, #0x000] // restore x0,x1
movsp,x16 // restore sp
- retx30// jump to pc
john-
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/102322
>From 1c6cbe68b3d2698cf5958daf84ec25496bb7589a Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Wed, 7 Aug 2024 14:25:29 +0100
Subject: [PATCH 1/2] [libunwind] Fix problems caused by combining BTI and GCS
https://github.com/john-brawn-arm closed
https://github.com/llvm/llvm-project/pull/102322
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Author: John Brawn
Date: 2021-03-30T18:33:10+01:00
New Revision: eae3b2a715d7fd1aea0ce1c78ac7a04957b72728
URL:
https://github.com/llvm/llvm-project/commit/eae3b2a715d7fd1aea0ce1c78ac7a04957b72728
DIFF:
https://github.com/llvm/llvm-project/commit/eae3b2a715d7fd1aea0ce1c78ac7a04957b72728.diff
LO
Author: John Brawn
Date: 2021-03-30T18:33:10+01:00
New Revision: eae3b2a715d7fd1aea0ce1c78ac7a04957b72728
URL:
https://github.com/llvm/llvm-project/commit/eae3b2a715d7fd1aea0ce1c78ac7a04957b72728
DIFF:
https://github.com/llvm/llvm-project/commit/eae3b2a715d7fd1aea0ce1c78ac7a04957b72728.diff
LO
Author: John Brawn
Date: 2021-04-21T14:00:38+01:00
New Revision: 5f02c308e68d2412e2555017d4dbe3e2cc122913
URL:
https://github.com/llvm/llvm-project/commit/5f02c308e68d2412e2555017d4dbe3e2cc122913
DIFF:
https://github.com/llvm/llvm-project/commit/5f02c308e68d2412e2555017d4dbe3e2cc122913.diff
LO
https://github.com/john-brawn-arm created
https://github.com/llvm/llvm-project/pull/96903
This adds intrinsics defined in ARM-software/acle#260
Doing this requires some changes to the GCS instruction definitions, as these
intrinsics make use of how some instructions don't modify the input regi
john-brawn-arm wrote:
I'm not especially familiar with how pointer authentication works with
exception unwinding, but this looks OK to me with some minor comments.
https://github.com/llvm/llvm-project/pull/113368
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@@ -1845,8 +1884,14 @@ class _LIBUNWIND_HIDDEN Registers_arm64 {
uint64_t getSP() const { return _registers.__sp; }
void setSP(uint64_t value) { _registers.__sp = value; }
- uint64_t getIP() const { return _registers.__pc; }
- void setIP(uint6
@@ -1823,9 +1823,48 @@ extern "C" void *__libunwind_cet_get_jump_target() {
#endif
class _LIBUNWIND_HIDDEN Registers_arm64 {
+protected:
+ /// The program counter is used effectively as a return address
+ /// when the context is restored therefore protect it with PAC.
+ ///
@@ -1823,9 +1823,48 @@ extern "C" void *__libunwind_cet_get_jump_target() {
#endif
class _LIBUNWIND_HIDDEN Registers_arm64 {
+protected:
+ /// The program counter is used effectively as a return address
john-brawn-arm wrote:
"used effectively" should be "eff
@@ -1823,9 +1823,48 @@ extern "C" void *__libunwind_cet_get_jump_target() {
#endif
class _LIBUNWIND_HIDDEN Registers_arm64 {
+protected:
+ /// The program counter is used effectively as a return address
+ /// when the context is restored therefore protect it with PAC.
+ ///
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/115894
>From 9001ad621028caa0ca2095156f28fac88deb8525 Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Wed, 6 Nov 2024 12:15:17 +
Subject: [PATCH 1/2] [IR] Allow fast math flags on fptrunc and fpext
This con
https://github.com/john-brawn-arm created
https://github.com/llvm/llvm-project/pull/115894
This consists of:
* Make these instructions part of FPMathOperator.
* Adjust bitcode/ir readers/writers to expect fast math flags on these
instructions.
* Make IRBuilder set the fast math flags on thes
john-brawn-arm wrote:
> @john-brawn-arm This may be hard to remember, but this a path you've tread
> before could the LLVM_INSTANTIATE_REGISTRY just be changed to a fulll class
> explicit template instantiation?
It looks like the approach you're going for is:
* Registry is declared as extern
@@ -1875,13 +1873,17 @@ Instruction *InstCombinerImpl::visitFPTrunc(FPTruncInst
&FPT) {
// fptrunc (select Cond, (fpext X), Y --> select Cond, X, (fptrunc Y)
Value *NarrowY = Builder.CreateFPTrunc(Y, Ty);
Value *Sel = Builder.CreateSelect(Cond, X, NarrowY, "n
@@ -1875,13 +1873,17 @@ Instruction *InstCombinerImpl::visitFPTrunc(FPTruncInst
&FPT) {
// fptrunc (select Cond, (fpext X), Y --> select Cond, X, (fptrunc Y)
Value *NarrowY = Builder.CreateFPTrunc(Y, Ty);
Value *Sel = Builder.CreateSelect(Cond, X, NarrowY, "n
john-brawn-arm wrote:
Ping
https://github.com/llvm/llvm-project/pull/115894
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@@ -1875,13 +1873,17 @@ Instruction *InstCombinerImpl::visitFPTrunc(FPTruncInst
&FPT) {
// fptrunc (select Cond, (fpext X), Y --> select Cond, X, (fptrunc Y)
Value *NarrowY = Builder.CreateFPTrunc(Y, Ty);
Value *Sel = Builder.CreateSelect(Cond, X, NarrowY, "n
https://github.com/john-brawn-arm edited
https://github.com/llvm/llvm-project/pull/115894
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@@ -1875,13 +1873,17 @@ Instruction *InstCombinerImpl::visitFPTrunc(FPTruncInst
&FPT) {
// fptrunc (select Cond, (fpext X), Y --> select Cond, X, (fptrunc Y)
Value *NarrowY = Builder.CreateFPTrunc(Y, Ty);
Value *Sel = Builder.CreateSelect(Cond, X, NarrowY, "n
john-brawn-arm wrote:
Instcombine follow up : https://github.com/llvm/llvm-project/pull/118808
https://github.com/llvm/llvm-project/pull/115894
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https://github.com/john-brawn-arm closed
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john-brawn-arm wrote:
These functions aren't exposed in any of the header files in libunwind/include
so I don't think renaming them should be a problem. Renaming things to use
architecture-neutral terms sounds like a good idea to me.
https://github.com/llvm/llvm-project/pull/126663
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https://github.com/john-brawn-arm approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/126774
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@@ -161,5 +168,62 @@ int test_bitint8(){
}
// CHECK: ret i32 1
+// Over-sized bitfield, which results in a 64-bit container type, so 64-bit
+// alignment.
+struct OverSizedBitfield {
+ int x : 64;
+};
+
+unsigned sizeof_OverSizedBitfield = sizeof(OverSizedBitfield);
+unsigne
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