[PATCH] D116509: [Builtins] Add missing the macro 'y' description in comments

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9b70ddaff6e1: [Builtins] Add missing the macro 'y' description in comments (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

Jim created this revision. Jim added reviewers: khchen, craig.topper. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

Jim updated this revision to Diff 330888. Jim added a comment. Address @craig.topper 's comment. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98682/new/ https://reviews.llvm.org/D98682 Files: clang/include/clang/Basic/BuiltinsRISCV.def clang/utils/TableGen/RISCVVEmitter.cpp Inde

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG678241795c95: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D98923: [Driver] Pass -fexperimental-strict-floating-point to cc1 if it is specified

Jim created this revision. Jim added a reviewer: kpn. Jim requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. In my case, it has to enable strict floating-point by driver for default unsupported target. Repository: rG LLVM Github Monorepo

[PATCH] D98923: [Driver] Pass -fexperimental-strict-floating-point to cc1 if it is specified

Jim abandoned this revision. Jim added a comment. In D98923#2638061 , @craig.topper wrote: > Isn't OPT_fexperimental_strict_floating_point marked as a CC1Option in > Options.td. Can the driver even recognize it? > > Can you use -Xclang -fexperimental-str

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added a comment. In D99158#2645796 , @craig.topper wrote: > What are we gaining from making the intrinsics use vector types if no vector > operations are supported other than the intrinsics? Why can't we just use an > xlen integer type? It can supp

[PATCH] D99631: [RISCV] Refine pre-define macro tests

Jim created this revision. Jim added reviewers: craig.topper, simoncook, HsiangKai. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, jfb, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, sh

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

Jim added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:28 +TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr") + I don't know why it does

[PATCH] D99631: [RISCV] Refine pre-define macro tests

This revision was automatically updated to reflect the committed changes. Closed by commit rG32ca5a037ab9: [RISCV] Refine pre-define macro tests (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99631/new/ https://reviews.llvm.org/D99

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

Jim added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:26 + +} // TargetPrefix = "riscv" + How about put it between Atomics and Vector to follow canonical order? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 335416. Jim edited the summary of this revision. Jim added a comment. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/B

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setOperationAction(ISD::BITCAST, VT, Legal); + craig.topper wrote: > What about bitcast from float/double to any of these vector types? I'm guess > that's not legal.

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

Jim abandoned this revision. Jim added a comment. Herald added a subscriber: vkmr. Merge this patch into https://reviews.llvm.org/D95588 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95590/new/ https://reviews.llvm.org/D95590 _

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

Jim abandoned this revision. Jim added a comment. Herald added a subscriber: vkmr. Merge this patch into https://reviews.llvm.org/D95588 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95589/new/ https://reviews.llvm.org/D95589 _

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:17944 + + // P extension +#define EMIT_BUILTIN(NAME, INT) \ I have concern here. It has lots of duplicate code if the code style is the same as B in the top. And the name of macro is not goo

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 335428. Jim added a comment. Subtarget.hasStdExtP() -> Subtarget.hasStdExtZpn() for addRegisterClass CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setOperationAction(ISD::BITCAST, VT, Legal); + Jim wrote: > craig.topper wrote: > > What about bitcast from float/double to any of these vector types? I'm > > guess t

[PATCH] D71541: [NFC] [Clang]: fix spelling mistake in assert message

Jim updated this revision to Diff 336752. Jim added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71541/new/ https://reviews.llvm.org/D71541 Files: clang/lib/AST/VTableBuilder.cpp Index: clang/lib/AST/VTableBuilder.cpp ==

[PATCH] D71541: [NFC] [Clang]: fix spelling mistake in assert message

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8a2d375a77bf: [NFC] [Clang]: fix spelling mistake in assert message (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACT

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

Jim added a reviewer: Jim. Jim added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:993 +defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil", + [["v", "Uv", "UvUv"]]>; +defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd"

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

Jim added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1217 +defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil", + [["s", "ve", "ev"], +["s", "UvUe", "UeUv"]]>; Inden

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

Jim accepted this revision. Jim added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100266/new/ https://reviews.llvm.org/D100266 ___ cfe-commits mailing list cfe-commits@lists.llvm.org ht

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 338017. Jim added a comment. 1. Updating D99158 : [RISCV][WIP] Implement intrinsics for P extension # 2. Enter a brief description of the changes included in this update. 3. The first line is used as subject, next lines as comment

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:762 + for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) +setOperationAction(Opc, VT, Expand); + craig.topper wrote: > You probably need handling for insert_vect

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 338414. Jim added a comment. Fix typo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/Builtins.de

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added a comment. In D99158#2695125 , @craig.topper wrote: > Also can you please explain the vector codegen plan at a high level? Do you > intend to support auto vectorization or just using vector_size in C? Currently, it just supports vector type op

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

Jim added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:387 +ExtensionInfoIterator->Version.Minor); + if (ExtName == "e") +HasE = true; Does this need to check it is invalid if XLen is 64? ==

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

Jim added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:416 +ExtensionInfoIterator->Version.Minor); + if (ExtName == "e") { +if (XLen != 32) Could this checking put before ISAInfo->addExtension... Reposi

[PATCH] D108189: [RISCV] Add arch attribute support for P extension

Jim updated this revision to Diff 370484. Jim added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Base on D105168 to support arch features, arch attributes and preprocessor definitions. Repository: rG LLVM Github Monorepo

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Hi, @jrtc27 About the concern the invalid combination RV32 + zprvsfextra on riscv attribute, I upload a patch D108189 based on @kito-cheng 's patch D105168 to forbid emitting rv32+zprvsfextra arch stri

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.93

Jim updated this revision to Diff 372058. Jim added a comment. Update to 0.96 and remove Zprvsfextra Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108189/new/ https://reviews.llvm.org/D108189 Files: clang/test/Driver/riscv-arch.c clang/test/Pr

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