https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113623
>From 81dfa26a941f7a0926a3126fe3ebbb4d2a67cec1 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH 01/13] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed`
intrinsic
inbelic wrote:
Regarding the comments about differentiating between `OpSDot/DotProduct` and
`OpSDotKHR/DotProductKHR`:
I agree that these are different ops/capabilities in the SPIR-V spec.
However from a quick attempt to implement this, I found that since the
Capabilities share the same bit v
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inbelic wrote:
Please ignore the first commit when reviewing. It is separately reviewed here:
#114849
https://github.com/llvm/llvm-project/pull/114847
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https://github.com/llvm/llvm-project/pull/113623
>From 81dfa26a941f7a0926a3126fe3ebbb4d2a67cec1 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH 01/14] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed`
intrinsic
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113623
>From 136d5cb3fcda0d49183503fb26c60ffc79a17491 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH 01/15] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed`
intrinsic
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https://github.com/inbelic approved this pull request.
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inbelic wrote:
Rebased to help with resolve merge conflicts.
Thanks a lot for the time and reviews. Really helpful and I learned a lot.
https://github.com/llvm/llvm-project/pull/113623
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>From 136d5cb3fcda0d49183503fb26c60ffc79a17491 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH 01/15] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed`
intrinsic
@@ -934,6 +934,16 @@ uint64_t dot(uint64_t3, uint64_t3);
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_dot)
uint64_t dot(uint64_t4, uint64_t4);
+//===--===//
+// dot4add builtins
+//===---
@@ -559,7 +559,7 @@ class CompilerInstance : public ModuleLoader {
bool hasSema() const { return (bool)TheSema; }
Sema &getSema() const {
-assert(TheSema && "Compiler instance has no Sema object!");
inbelic wrote:
Why are we able to remove this assert
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/115068
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https://github.com/llvm/llvm-project/pull/115068
>From 414b07fd2276946936dc137fb633b04cd8c12fc4 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Tue, 5 Nov 2024 21:15:17 +
Subject: [PATCH 1/2] [HLSL][SPIRV][DXIL] Implement `dot4add_u8packed`
intrinsic
-
https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/115068
```- create a clang built-in in Builtins.td
- link dot4add_u8packed in hlsl_intrinsics.h
- add lowering to spirv backend through expansion of operation as OpUDot is
missing up to SPIRV 1.6 in SPIRVInstructionSel
https://github.com/inbelic approved this pull request.
https://github.com/llvm/llvm-project/pull/113649
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https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113623
>From 81dfa26a941f7a0926a3126fe3ebbb4d2a67cec1 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH 1/9] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed`
intrinsic
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113623
>From 81dfa26a941f7a0926a3126fe3ebbb4d2a67cec1 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH 1/9] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed`
intrinsic
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113623
>From 81dfa26a941f7a0926a3126fe3ebbb4d2a67cec1 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH 01/10] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed`
intrinsic
@@ -2527,6 +2640,11 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_udot:
case Intrinsic::spv_sdot:
return selectIntegerDot(ResVReg, ResType, I);
+ case Intrinsic::spv_dot4add_i8packed:
+if (STI.canUseExtension(SPIRV::Extens
@@ -85,6 +85,8 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113382
>From a9b7602da0f38aeef41ce4e0a8c6a4a6e0d71b0a Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Fri, 18 Oct 2024 15:48:29 -0700
Subject: [PATCH 1/3] [DXIL][SPIRV] Lower WaveActiveCountBits intrinsic
- add co
https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/113623
- create a clang built-in in Builtins.td
- link dot4add_i8packed in hlsl_intrinsics.h
- add lowering to spirv backend through expansion of operation as OPSDot is
missing up to SPIRV 1.6 in SPIRVInstr
@@ -0,0 +1,22 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-defaul
@@ -1920,6 +1923,24 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -19108,6 +19108,21 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Int
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -19108,6 +19108,21 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Int
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
inbelic wrote:
I think we prefer `-mtriple=spirv-unknown-unknown`. You might need to use
`spirv1.[5|6]` if you are using an new included spirv op.
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -fnative-half-type
-triple \
inbelic wrote:
I think we can remove the `-std=hlsl2021` flags.
https://github.com/llvm/llvm-project/pull/115902
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https://github.com/inbelic commented:
Nice work. Mostly just some nits and cleanups :)
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@@ -93,6 +93,7 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32
@@ -202,6 +202,7 @@ defset list OpClasses = {
def unpack4x8 : DXILOpClass;
def viewID : DXILOpClass;
def waveActiveAllEqual : DXILOpClass;
+ def waveActiveAnyTrue : DXILOpClass;
inbelic wrote:
You shouldn't define and use this, instead use `waveAnyTrue`
@@ -2091,6 +2091,12 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
return true;
break;
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+if (SemaRef.checkArgCount(TheCall, 1))
+ return true;
+
+break;
+
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https://github.com/llvm/llvm-project/pull/115902
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https://github.com/llvm/llvm-project/pull/110027
>From 95c42a442fed4bbaf1cb129cf0cb79d48c4e8cbd Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 25 Sep 2024 08:06:35 -0700
Subject: [PATCH] [HLSL] Implement `asint` casting using `bit_cast`
Using clang's
https://github.com/inbelic ready_for_review
https://github.com/llvm/llvm-project/pull/110027
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inbelic wrote:
Hm, the failing test-case is unrelated to these changes. But please let me know
if action is required.
https://github.com/llvm/llvm-project/pull/110027
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https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/110739
- create a clang built-in
- add mapping to dxil opcode
- add lowering to SPIR-V GroupNonUniformShuffle with Scope = 2
(Group)
- add sema checks
- add related tests
Resolves #70104
>Fr
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/110739
>From cb3467d7395f7a1a0d0acdaee305f8c3c41892b1 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 25 Sep 2024 15:09:48 -0700
Subject: [PATCH] [HLSL] Implement `WaveReadLaneAt` intrinsics
- create a clan
@@ -2653,6 +2653,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
+ case Intrinsic::spv_wave_read_lane_at: {
+assert(I.getNumOperands() == 4);
https://github.com/inbelic closed
https://github.com/llvm/llvm-project/pull/110739
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>From 0320a5acec2565608cb91b271f6cda49fc364bb7 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 25 Sep 2024 15:09:48 -0700
Subject: [PATCH] [HLSL] Implement `WaveReadLaneAt` intrinsics
- create a clan
@@ -414,13 +434,15 @@ Expected
DXILOpBuilder::tryCreateOp(dxil::OpCode OpCode,
uint16_t ValidTyMask = Prop->Overloads[*OlIndexOrErr].ValidTys;
- OverloadKind Kind = getOverloadKind(OverloadTy);
+ OverloadKind Kind = getOverloadKind(OverloadTy, Prop->AllowVectorOverloads)
https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/110027
Using clang's `__builtin_bit_cast`, implement the hlsl intrinsic `asint`.
Follows implementation details of `asuint/asfloat`.
Fixes #99091
>From 48ed7afee4dbe3735decff795aac26a6788f2680 Mon Sep 17 00:00:00 200
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/110739
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https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/111010
- create a clang built-in in Builtins.td
- add semantic checking in SemaHLSL.cpp
- create
- add lowering to spirv backend op GroupNonUniformShuffle
with Scope = 2 (Group) in SPIRVInstruction
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/111010
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@@ -812,6 +821,34 @@ def SplitDouble : DXILOp<102, splitDouble> {
let attributes = [Attributes];
}
+def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
inbelic wrote:
This reordering will be addressed as part of DXIL.td clean-up in #114461.
https://gith
@@ -75,7 +75,9 @@ static const std::map
{"SPV_KHR_cooperative_matrix",
SPIRV::Extension::Extension::SPV_KHR_cooperative_matrix},
{"SPV_KHR_non_semantic_info",
- SPIRV::Extension::Extension::SPV_KHR_non_semantic_info}};
+ SPIRV::Extension
@@ -2120,6 +2123,32 @@ bool
SPIRVInstructionSelector::selectSplatVector(Register ResVReg,
return MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectClip(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -89,6 +89,7 @@ let TargetPrefix = "spv" in {
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0,
llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int
@@ -456,6 +456,7 @@ defm VulkanMemoryModelDeviceScopeKHR :
CapabilityOperand<5346, 0, 0, [], []>;
defm ImageFootprintNV : CapabilityOperand<5282, 0, 0, [], []>;
defm FragmentBarycentricNV : CapabilityOperand<5284, 0, 0, [], []>;
defm ComputeDerivativeGroupQuadsNV : CapabilityO
@@ -63,6 +63,7 @@
#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
#include "llvm/Support/AMDGPUAddrSpace.h"
#include "llvm/Support/ConvertUTF.h"
+#include "llvm/Support/ErrorHandling.h"
inbelic wrote:
What is this used for?
https://github.com/llvm/llvm-
@@ -0,0 +1,77 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s --check-prefixes=CHECK,SPIRV15
+; RUN: llc -verify-machineinstrs
-spirv-ext=+SPV_EXT_demote_to_helper_invocation -O0
-mtriple=spirv32v1.6-unknown-unknown %s -o - | FileC
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https://github.com/llvm/llvm-project/pull/114588
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@@ -1762,6 +1765,37 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveCountBits(
+Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
+ assert(I.getNumOperands() == 3);
+ as
@@ -89,6 +89,7 @@ let TargetPrefix = "spv" in {
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0,
llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113382
>From 35731658c1769453f86dde6063b137a2c5aeca32 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Fri, 18 Oct 2024 15:48:29 -0700
Subject: [PATCH 1/4] [DXIL][SPIRV] Lower WaveActiveCountBits intrinsic
- add co
inbelic wrote:
Rebased to resolve conflicts.
https://github.com/llvm/llvm-project/pull/113382
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https://github.com/llvm/llvm-project/pull/113382
>From 35731658c1769453f86dde6063b137a2c5aeca32 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Fri, 18 Oct 2024 15:48:29 -0700
Subject: [PATCH 1/4] [DXIL][SPIRV] Lower WaveActiveCountBits intrinsic
- add co
https://github.com/inbelic ready_for_review
https://github.com/llvm/llvm-project/pull/113623
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https://github.com/inbelic approved this pull request.
https://github.com/llvm/llvm-project/pull/113730
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https://github.com/llvm/llvm-project/pull/113623
>From 81dfa26a941f7a0926a3126fe3ebbb4d2a67cec1 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 23 Oct 2024 22:59:15 +
Subject: [PATCH] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed` intrinsic
-
@@ -894,6 +894,16 @@ uint64_t dot(uint64_t3, uint64_t3);
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_dot)
uint64_t dot(uint64_t4, uint64_t4);
+//===--===//
+// dot4add builtins
+//===---
https://github.com/inbelic approved this pull request.
https://github.com/llvm/llvm-project/pull/112461
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@@ -2163,6 +2163,49 @@ static void BuildFlattenedTypeList(QualType BaseTy,
}
}
+bool SemaHLSL::IsLineVectorLayoutCompatibleType(clang::QualType QT) {
+ if (QT.isNull())
+return false;
+
+ llvm::SmallVector QTTypes;
+ BuildFlattenedTypeList(QT, QTTypes);
+
+ QualType
inbelic wrote:
Typo in filename: `TypeErros` -> `TypeErrors`
https://github.com/llvm/llvm-project/pull/113730
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https://github.com/llvm/llvm-project/pull/115068
>From 414b07fd2276946936dc137fb633b04cd8c12fc4 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Tue, 5 Nov 2024 21:15:17 +
Subject: [PATCH 1/4] [HLSL][SPIRV][DXIL] Implement `dot4add_u8packed`
intrinsic
-
@@ -1743,7 +1743,7 @@ bool
SPIRVInstructionSelector::selectDot4AddPackedExpansion(
assert(I.getOperand(4).isReg());
MachineBasicBlock &BB = *I.getParent();
- bool Result = false;
+ bool Result = true;
inbelic wrote:
Good idea. It would be probably also
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/115068
>From 414b07fd2276946936dc137fb633b04cd8c12fc4 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Tue, 5 Nov 2024 21:15:17 +
Subject: [PATCH 1/3] [HLSL][SPIRV][DXIL] Implement `dot4add_u8packed`
intrinsic
-
@@ -942,7 +942,13 @@ uint64_t dot(uint64_t4, uint64_t4);
_HLSL_AVAILABILITY(shadermodel, 6.4)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_dot4add_i8packed)
-int dot4add_i8packed(unsigned int, unsigned int, int);
+int dot4add_i8packed(uint, uint, int);
inbelic wrote:
S
@@ -0,0 +1,65 @@
+; RUN: llc -O0 -mtriple=spirv1.5-unknown-unknown %s -o - | FileCheck %s
--check-prefixes=CHECK,CHECK-EXP
+; RUN: llc -O0 -mtriple=spirv1.6-unknown-unknown %s -o - | FileCheck %s
--check-prefixes=CHECK,CHECK-DOT
+; RUN: llc -O0 -mtriple=spirv-unknown-unknown
-s
inbelic wrote:
> I didn't see `SemaHLSL.cpp` changes, I saw the tests though.
Since the function signature is completely captured in `hlsl_intrinsics.h` we
aren't required to manually define it in `SemaHLSL.cpp`
https://github.com/llvm/llvm-project/pull/115068
_
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/115068
>From 414b07fd2276946936dc137fb633b04cd8c12fc4 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Tue, 5 Nov 2024 21:15:17 +
Subject: [PATCH 1/4] [HLSL][SPIRV][DXIL] Implement `dot4add_u8packed`
intrinsic
-
https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/113382
>From 35731658c1769453f86dde6063b137a2c5aeca32 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Fri, 18 Oct 2024 15:48:29 -0700
Subject: [PATCH 1/4] [DXIL][SPIRV] Lower WaveActiveCountBits intrinsic
- add co
https://github.com/inbelic closed
https://github.com/llvm/llvm-project/pull/113382
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https://github.com/inbelic closed
https://github.com/llvm/llvm-project/pull/112400
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https://github.com/inbelic closed
https://github.com/llvm/llvm-project/pull/112991
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https://github.com/llvm/llvm-project/pull/112400
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@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -630,6 +630,15 @@ void RequirementHandler::initAvailableCapabilities(const
SPIRVSubtarget &ST) {
addAvailableCaps({Capability::Shader, Capability::Linkage, Capability::Int8,
Capability::Int16});
+ if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3)))
---
@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -2206,6 +2206,15 @@ float4 trunc(float4);
// Wave* builtins
//===--===//
+/// \brief Returns true if the expression is true in any active lane in the
+/// current wave.
+///
+/// \param Val The boolean exp
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
@@ -853,6 +853,15 @@ def CreateHandleFromBinding : DXILOp<217,
createHandleFromBinding> {
let stages = [Stages];
}
+def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
+ let Doc = "returns true if the expression is true in any of the active lanes
in the current wave";
+ l
@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -19120,6 +19120,15 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Val
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