[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -0,0 +1,57 @@ +; RUN: opt -S -dxil-intrinsic-expansion < %s | FileCheck %s --check-prefix=CHECK farzonl wrote: My point still stands why do you need two runs? https://github.com/llvm/llvm-project/pull/109180 ___

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

farzonl wrote: The SPIRV frem testing doesn't appear to be complete in `llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll` `llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll` for all our cases we defined in `hlsl_intrinsics.h`. Should we add more te

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

farzonl wrote: We should announce `__builtin_elementwise_fmod` here: `clang/docs/ReleaseNotes.rst` See @spall PR where we just did this: https://github.com/llvm/llvm-project/pull/108121/files https://github.com/llvm/llvm-project/pull/108849 ___ cfe

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -0,0 +1,38 @@ + +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected + +float test_too_few_arg() { farzonl wrote: These test cases are

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -0,0 +1,38 @@ + +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected + +float test_too_few_arg() { + return __builtin_elementwise_fmod(); + // expecte

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

farzonl wrote: This LGTM. There is one last thing we might want to do. But I'm not requiring it for sign off. We ussually add elementwise math builtins here: - `clang/test/CodeGen/builtins-elementwise-math.c` -`clang/test/CodeGen/strictfp-elementwise-bulitins.cpp` - `clang/test/Sema/builtins-ele

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

farzonl wrote: change the title of this PR to remove the word intrinsic. That word has a specific meaning in LLVM and folks might get confused. Something like: `[HLSL] Implementation of the fmod API` https://github.com/llvm/llvm-project/pull/108849

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -0,0 +1,79 @@ +// DirectX target: +// +// -- Native Half support test --- +// +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileC

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -0,0 +1,79 @@ +// DirectX target: +// +// -- Native Half support test --- +// +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileC

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

@@ -0,0 +1,38 @@ + +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected + +float test_too_few_arg() { + return __builtin_elementwise_fmod(); + // expecte

[clang] [HLSL] Implementation of the elementwise fmod builtin (PR #108849)

@@ -1645,6 +1645,18 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; break; } + case Builtin::BI__builtin_elementwise_fmod: { farzonl wrote: Delete this case block. Move Builtin::BI__builtin_elemen

[clang] [HLSL] Implementation of the elementwise fmod builtin (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the elementwise fmod builtin (PR #108849)

@@ -0,0 +1,37 @@ + +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected + +float test_too_few_arg() { + return __builtin_elementwise_fmod(); + // expecte

[clang] [HLSL] Implementation of the elementwise fmod builtin (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the elementwise fmod builtin (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the elementwise fmod builtin (PR #108849)

farzonl wrote: @lizhengxing please run clang-format. https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,63 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; ModuleID = '../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl' +source_filename = "../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl" +target datalayout

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,63 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; ModuleID = '../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl' +source_filename = "../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl" +target datalayout

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -88,4 +88,9 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>] def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>],

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,32 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.3-library %s -fnative-half-type -emit-llvm -O1 -o - | FileCheck %s +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple spirv--vulkan-library %s -fnative-half-type -emit-l

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -6,6 +6,10 @@ uint4 test_asuint_too_many_arg(float p0, float p1) { // expected-error@-1 {{no matching function for call to 'asuint'}} // expected-note@hlsl/hlsl_intrinsics.h:* {{candidate function template not viable: requires single argument 'V', but 2 arguments were pr

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18843,6 +18843,75 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { retType, CGM.getHLSLRuntime().getSignIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.sign"); } + // This should only be called when targeting DXIL + case Builtin::BI__builtin_hlsl_splitd

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -18843,6 +18843,75 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { retType, CGM.getHLSLRuntime().getSignIntrinsic(), ArrayRef{Op0}, nullptr, "hlsl.sign"); } + // This should only be called when targeting DXIL + case Builtin::BI__builtin_hlsl_splitd

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -422,6 +422,55 @@ template constexpr uint asuint(T F) { return __detail::bit_cast(F); } +//===--===// +// asuint splitdouble builtins +//===---

[clang] [HLSL] Implement `asint` casting using `bit_cast` (PR #110027)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/110027 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the elementwise fmod builtin (PR #108849)

https://github.com/farzonl closed https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,63 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; ModuleID = '../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl' +source_filename = "../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl" +target datalayout

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,63 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; ModuleID = '../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl' +source_filename = "../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl" +target datalayout

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,63 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; ModuleID = '../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl' +source_filename = "../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl" +target datalayout

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,63 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; ModuleID = '../clang/test/CodeGenHLSL/builtins/asuint-splitdouble.hlsl' farzonl wrote: delete lines 3 through 6. https://github.com/llvm/llvm-project/p

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -264,6 +265,31 @@ class OpLowerer { return lowerToBindAndAnnotateHandle(F); } + Error replaceSplitDoubleCallUsages(CallInst *Intrin, CallInst *Op) { +IRBuilder<> &IRB = OpBuilder.getIRB(); + +for (Use &U : make_early_inc_range(Intrin->uses())) { + if (au

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -85,4 +85,9 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>] def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>],

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -422,6 +422,55 @@ template constexpr uint asuint(T F) { return __detail::bit_cast(F); } +//===--===// +// asuint splitdouble builtins +//===---

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -18639,6 +18639,21 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, IsUnsigned ? Intrinsic::dx_uclamp : Intrinsic::dx_clamp, ArrayRef{OpX, OpMin, OpMax}, nullptr, "dx.clamp"); } + case Builtin::BI__builtin_hlsl_cross: { +Value *Op0 =

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -44,6 +44,7 @@ def int_dx_cast_handle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>; def int_dx_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; def int_dx_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; def int_dx_clamp : DefaultA

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109180 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -1704,6 +1704,20 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; break; } + case Builtin::BI__builtin_hlsl_cross: { +if (SemaRef.checkArgCount(TheCall, 2)) + return true; +if (CheckVectorElementCallA

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109180 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -73,6 +74,42 @@ static Value *expandAbs(CallInst *Orig) { "dx.max"); } +static Value *expandCrossIntrinsic(CallInst *Orig) { + + VectorType *VT = cast(Orig->getType()); + if (cast(VT)->getNumElements() != 3) +report_fatal_error(Twine("

[clang] [HLSL][clang] Add elementwise builtin for atan2 (p3) (PR #110187)

@@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -DTEST_FUNC=__builtin_elementwise_atan2 +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermode

[clang] [HLSL][clang] Add elementwise builtin for atan2 (p3) (PR #110187)

@@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -DTEST_FUNC=__builtin_elementwise_atan2 +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermode

[clang] [HLSL][clang] Add elementwise builtin for atan2 (p3) (PR #110187)

@@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -DTEST_FUNC=__builtin_elementwise_atan2 +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermode

[clang] [HLSL][clang] Add elementwise builtin for atan2 (p3) (PR #110187)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/110187 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,34 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.3-library %s -fnative-half-type -emit-llvm -O1 -o - | FileCheck %s +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple spirv--vulkan-library %s -fnative-half-type -emit-l

[clang] [HLSL] Treat `main` as any other function (PR #110546)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/110546 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Treat `main` as any other function (PR #110546)

@@ -4,7 +4,7 @@ // SPIRV: error: '-fnative-half-type' option requires target HLSL Version >= 2018, but HLSL Version is 'hlsl2016' // valid: "spirv-unknown-vulkan-library" -// valid: define spir_func void @main() #0 { +// valid: define spir_func void @{{.*}}main{{.*}}() #0 { -

[clang] [HLSL] Treat `main` as any other function (PR #110546)

@@ -1,7 +1,7 @@ // RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \ // RUN: spirv-pc-vulkan-library %s -emit-llvm -disable-llvm-passes -o - | FileCheck %s -// CHECK: define spir_func void @main() [[A0:#[0-9]+]] { +// CHECK: define spir_func void @{{.

[clang] [HLSL] Treat `main` as any other function (PR #110546)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/110546 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

farzonl wrote: In light of sarah’s comment we probably do want those extra test cases I mentioned here: https://github.com/llvm/llvm-project/pull/108849#issuecomment-2372671949 https://github.com/llvm/llvm-project/pull/108849 _

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

farzonl wrote: Good point. Yeah this needs to move to Semachecking, but we need `case Builtin::BI__builtin_elementwise_fmod` in SemaHLSL for the half float check https://github.com/llvm/llvm-project/pull/108849 ___ c

[clang] [HLSL] Add RWStructuredBuffer definition to HLSLExternalSemaSource (PR #113477)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/113477 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL][SPIRV] Add convergence tokens to entry point wrapper (PR #112757)

https://github.com/farzonl approved this pull request. Code looks correct. Issues found were minor so LGTM. https://github.com/llvm/llvm-project/pull/112757 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/

[clang] [HLSL][SPIRV] Add convergence tokens to entry point wrapper (PR #112757)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/112757 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL][SPIRV] Add convergence tokens to entry point wrapper (PR #112757)

@@ -0,0 +1,11 @@ +// RUN: %clang_cc1 -triple spirv-pc-vulkan-compute -finclude-default-header -fnative-half-type -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s farzonl wrote: This test doesn't do anything with `native half types why do you need the `-fn

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -95,6 +99,144 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslSplitdouble(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); +

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl approved this pull request. LGTM. Please address the issue linking and Tex's testing requests. https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/111010 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement `WaveReadLaneAt` intrinsic (PR #111010)

@@ -0,0 +1,44 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; Test lowering to spir-v backend for various types an

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -2206,6 +2206,15 @@ float4 trunc(float4); // Wave* builtins //===--===// +/// \brief Returns true if the expression is true in any active lane in the +/// current wave. +/// +/// \param Val The boolean exp

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/115902 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, case Intrinsic::spv_wave_active_countbits: return selectWaveActiveCountBits(ResVReg, ResType, I); case Intrinsic::spv_wave_any: -return selectWaveActiveAnyTrue(ResVReg, ResType,

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

https://github.com/farzonl approved this pull request. lgtm https://github.com/llvm/llvm-project/pull/115902 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -2826,6 +2843,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp); case Intrinsic::spv_wave_active_countbits: return selectWaveActiveCountBits(ResVReg, ResType, I); + case Intrin

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, return Result; } +bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg, + const SPIRVType *ResType, +

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, return Result; } +bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg, + const SPIRVType *ResType, +

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, return Result; } +bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg, + const SPIRVType *ResType, +

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -4744,6 +4744,12 @@ def HLSLAny : LangBuiltin<"HLSL_LANG"> { let Prototype = "bool(...)"; } +def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> { + let Spellings = ["__builtin_hlsl_wave_active_any_true"]; + let Attributes = [NoThrow, Const]; + let Prototype = "bool(b

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -94,6 +94,7 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, return Result; } +bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg, + const SPIRVType *ResType, +

[clang] [llvm] [HLSL] Implement WaveActiveAnyTrue intrinsic (PR #115902)

@@ -630,6 +630,15 @@ void RequirementHandler::initAvailableCapabilities(const SPIRVSubtarget &ST) { addAvailableCaps({Capability::Shader, Capability::Linkage, Capability::Int8, Capability::Int16}); + if (ST.isAtLeastSPIRVVer(VersionTuple(1, 3))) ---

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -99,6 +99,7 @@ def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, L def int_dx_splitdouble : DefaultAttrsIntrinsic<[llvm_anyint_ty, LLVMMatchType<0>], [LLVMScalarOrSameVectorWidth<0, llvm_double_ty>], [IntrNoMem]>; def int_dx_radians : Defa

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.3-pixel %s -fnative-half-type -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple spirv-vulkan-pixel %s -fnative-half-type -emit-llvm -o -

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -91,6 +91,7 @@ let TargetPrefix = "spv" in { def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>; def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; def int

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -164,6 +164,9 @@ class SPIRVInstructionSelector : public InstructionSelector { unsigned comparisonOpcode, MachineInstr &I) const; bool selectCross(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; + bool selectClip(Re

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -633,7 +633,8 @@ void RequirementHandler::initAvailableCapabilities(const SPIRVSubtarget &ST) { if (ST.isAtLeastSPIRVVer(VersionTuple(1, 6))) addAvailableCaps({Capability::DotProduct, Capability::DotProductInputAll, Capability::DotProductInput4x8

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -1407,6 +1408,19 @@ void addInstrRequirements(const MachineInstr &MI, Reqs.addCapability(SPIRV::Capability::SplitBarrierINTEL); } break; + case SPIRV::OpKill: { +Reqs.addCapability(SPIRV::Capability::Shader); + } break; + case SPIRV::OpDemoteToHelperInvo

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -770,6 +770,15 @@ def CheckAccessFullyMapped : DXILOp<71, checkAccessFullyMapped> { let stages = [Stages]; } +def Discard : DXILOp<82, discard> { + let Doc = "discard the current pixel"; + let LLVMIntrinsic = int_dx_discard; + let arguments = [Int1Ty]; ---

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -19180,6 +19221,11 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: { "asuint operands types mismatch"); return handleHlslSplitdouble(E, this); } + case Builtin::BI__builtin_hlsl_elementwise_clip: + farzonl wrote: delete the space htt

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -0,0 +1,22 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -verify + + +void test_arg_missing() { + __builtin_hlsl_elementwise_clip(); + // expected-error@-1 {{too few arguments to function call, expected 1, have 0

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl approved this pull request. Minor comments, but rest LGTM. Code correct as ticket is currently defined. We may want to move the behavior you currently have in cgbuiltins to hlsl_intrinsics.h. That way for spirv instead of a basic block we could do a c++ if statement

[clang] [NFC][HLSL] Allow target intrinsic switching to optionally be set. (PR #117648)

@@ -30,22 +30,36 @@ #include #include +#define GENERATE_HLSL_INTRINSIC_FUNCTION_DEFAULT(FunctionName, \ + IntrinsicPostfix) \ + GENERATE_HLSL_INTRINSIC_FUNCTION(FunctionName, IntrinsicPostfix, 1,

[clang] [NFC][HLSL] Allow target intrinsic switching to optionally be set. (PR #117648)

https://github.com/farzonl deleted https://github.com/llvm/llvm-project/pull/117648 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC][HLSL] Allow target intrinsic switching to optionally be set. (PR #117648)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/117648 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC][HLSL] Allow target intrinsic switching to optionally be set. (PR #117648)

@@ -30,22 +30,36 @@ #include #include +#define GENERATE_HLSL_INTRINSIC_FUNCTION_DEFAULT(FunctionName, \ + IntrinsicPostfix) \ + GENERATE_HLSL_INTRINSIC_FUNCTION(FunctionName, IntrinsicPostfix, 1,

[clang] [NFC][HLSL] Allow target intrinsic switching to optionally be set. (PR #117648)

https://github.com/farzonl updated https://github.com/llvm/llvm-project/pull/117648 >From 15b31c3528de5a955b465da2ab2699070628e64f Mon Sep 17 00:00:00 2001 From: Farzon Lotfi Date: Mon, 25 Nov 2024 19:04:47 -0500 Subject: [PATCH] [NFC] Allow target intrinsic switching to optionally be set. ---

[clang] [NFC] Allow target intrinsic switching to optionally be set. (PR #117648)

https://github.com/farzonl created https://github.com/llvm/llvm-project/pull/117648 This will make it easier for us to define an intrinsic optionally per backend. >From 0e8261c5def9b7ac3aa879b2ebc16d98f0c631ee Mon Sep 17 00:00:00 2001 From: Farzon Lotfi Date: Mon, 25 Nov 2024 19:04:47 -0500 Su

[clang] [NFC][HLSL] Allow target intrinsic switching to optionally be set. (PR #117648)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/117648 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (PR #114014)

https://github.com/farzonl approved this pull request. Lgtm https://github.com/llvm/llvm-project/pull/114014 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Implement a header only distance intrinsic (PR #117240)

https://github.com/farzonl updated https://github.com/llvm/llvm-project/pull/117240 >From 271141588db106f888dd6abb3ad7da41732a4f52 Mon Sep 17 00:00:00 2001 From: Farzon Lotfi Date: Thu, 21 Nov 2024 14:46:31 -0500 Subject: [PATCH] [HLSL] Implement a header only distance intrinsic Addressing RFC

[clang] [llvm] [HLSL] Implement a header only distance intrinsic (PR #117240)

https://github.com/farzonl updated https://github.com/llvm/llvm-project/pull/117240 >From 89507233b8b7ac859e1abbedb97e69574e54dfc8 Mon Sep 17 00:00:00 2001 From: Farzon Lotfi Date: Thu, 21 Nov 2024 14:46:31 -0500 Subject: [PATCH] [HLSL] Implement a header only distance intrinsic Addressing RFC

<    4   5   6   7   8   9   10   11   12   13   >