[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -264,6 +265,31 @@ class OpLowerer { return lowerToBindAndAnnotateHandle(F); } + Error replaceSplitDoubleCallUsages(CallInst *Intrin, CallInst *Op) { +IRBuilder<> &IRB = OpBuilder.getIRB(); + +for (Use &U : make_early_inc_range(Intrin->uses())) { + if (au

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,14 @@ +; RUN: opt -S -scalarizer -mtriple=spirv-vulkan-library %s 2>&1 | llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown -o - | FileCheck %s farzonl wrote: I don't think this file should exist. I don't understand why we are using `opt` t

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,16 @@ +; RUN: not opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s 2>&1 | FileCheck %s + +; DXIL operation splitdouble doesn't support vector types. +; CHECK: in function test_vector_double_split +; CHECK-SAME: splitdouble doesn't support lo

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,16 @@ +; RUN: not opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s 2>&1 | FileCheck %s + +; DXIL operation splitdouble doesn't support vector types. farzonl wrote: This is the test I would like to see become an XFAIL https

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,16 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; Make sure lowering is correctly generating spirv code. + +defi

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -489,6 +542,9 @@ class OpLowerer { case Intrinsic::dx_typedBufferStore: HasErrors |= lowerTypedBufferStore(F); break; + case Intrinsic::dx_splitdouble: farzonl wrote: I'd like to see all the changes to `DXILOpLowering.cpp` removed

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -82,5 +82,5 @@ let TargetPrefix = "spv" in { [llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>], [IntrNoMem, Commutative] >; def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; - def int_spv_sign : D

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl deleted https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -85,4 +85,9 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>] def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>],

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -0,0 +1,37 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} farzonl wrote: I dunno if you have to remove the

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2515,6 +2525,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt); case Intrinsic::spv_sign: return selectSign(ResVReg, ResType, I); + case Intrinsic::spv_firstbituhigh:

[clang] [clang][HLSL] Add radians intrinsic (PR #110802)

https://github.com/farzonl closed https://github.com/llvm/llvm-project/pull/110802 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][HLSL] Add radians intrinsic (PR #110802)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/110802 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -424,7 +424,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull( LLT LLTy = LLT::scalar(64); Register SpvVecConst = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); -CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass); +

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -808,6 +835,20 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, return false; } +bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg, +const SPIRVType *ResType, +

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2547,6 +2588,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt); case Intrinsic::spv_sign: return selectSign(ResVReg, ResType, I); + case Intrinsic::spv_firstbituhigh: // T

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2547,6 +2588,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt); case Intrinsic::spv_sign: return selectSign(ResVReg, ResType, I); + case Intrinsic::spv_firstbituhigh: // T

[clang] [llvm] [HLSL] Re-implement countbits with the correct return type (PR #113189)

https://github.com/farzonl approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/113189 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -0,0 +1,153 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s -DTARGET=dx +// RUN: %clang_cc1 -finclude-default-header -x hlsl -tripl

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -424,7 +424,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull( LLT LLTy = LLT::scalar(64); Register SpvVecConst = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); -CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass); +

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/111082 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2626,6 +2671,148 @@ Register SPIRVInstructionSelector::buildPointerToResource( MIRBuilder); } +bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg, +const

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2626,6 +2671,148 @@ Register SPIRVInstructionSelector::buildPointerToResource( MIRBuilder); } +bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg, +const

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -28,6 +28,8 @@ bool DirectXTTIImpl::isTargetIntrinsicTriviallyScalarizable( switch (ID) { case Intrinsic::dx_frac: case Intrinsic::dx_rsqrt: + case Intrinsic::dx_firstbituhigh: + case Intrinsic::dx_firstbitshigh: farzonl wrote: you will want to reba

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

farzonl wrote: This looks really good. I hade a few minor things and questions about either pulling things out of this pr and putting them into their own changes or future clean up to consolidate things. One more iteration and I'll be happy to approve. https://github.com/llvm/llvm-project/pull

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,15 @@ +; RUN: not opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s 2>&1 | FileCheck %s + +; DXIL operation splitdouble doesn't support vector types. + +define noundef <3 x i32> @test_vector_double_split(<3 x double> noundef %D) local_unnamed_addr { +en

[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -0,0 +1,130 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} farzonl wrote: Thats a artifact of the early d

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -95,6 +99,125 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslSplitdouble(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); +

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -99,6 +99,42 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslClip(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); + + Const

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -99,6 +99,42 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslClip(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); + + Const

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -99,6 +99,42 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslClip(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); + + Const

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -99,6 +99,42 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslClip(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); + + Const

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/114588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL][SPIRV][DXIL] Implement `dot4add_i8packed` intrinsic (PR #113623)

@@ -934,6 +934,16 @@ uint64_t dot(uint64_t3, uint64_t3); _HLSL_BUILTIN_ALIAS(__builtin_hlsl_dot) uint64_t dot(uint64_t4, uint64_t4); +//===--===// +// dot4add builtins +//===---

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2717,82 +2717,82 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg, Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT)); Result &= selectFirstBitHigh32(FBHReg, postCastT, I, bitcastReg, IsSigned); - // 3. check if result of e

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2626,6 +2671,151 @@ Register SPIRVInstructionSelector::buildPointerToResource( MIRBuilder); } +bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg, +const

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/111082 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/111082 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2626,6 +2671,151 @@ Register SPIRVInstructionSelector::buildPointerToResource( MIRBuilder); } +bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg, +const

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -37,13 +39,12 @@ define noundef i32 @firstbituhigh_i64(i64 noundef %a) { entry: ; CHECK: [[O:%.*]] = OpBitcast %[[#]] %[[#]] ; CHECK: [[N:%.*]] = OpExtInst %[[#]] %[[#]] FindUMsb [[O]] -; CHECK: [[M:%.*]] = OpVectorShuffle %[[#]] [[N]] [[N]] 0 -; CHECK: [[L:%.*]] = OpVectorS

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -449,6 +449,15 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull( return Res; } +Register SPIRVGlobalRegistry::getOrCreateConstScalarOrVector( +uint64_t Val, MachineInstr &I, SPIRVType *SpvType, +const SPIRVInstrInfo &TII, bool ZeroAsNull) { + if (SpvTy

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/111082 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2626,6 +2671,151 @@ Register SPIRVInstructionSelector::buildPointerToResource( MIRBuilder); } +bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg, +const

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2626,6 +2671,151 @@ Register SPIRVInstructionSelector::buildPointerToResource( MIRBuilder); } +bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg, +const

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -2717,82 +2717,82 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg, Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT)); Result &= selectFirstBitHigh32(FBHReg, postCastT, I, bitcastReg, IsSigned); - // 3. check if result of e

[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -40,8 +40,9 @@ def int_dx_cast_handle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>; def int_dx_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; def int_dx_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; -def int_dx_clamp : Defaul

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -808,6 +835,20 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, return false; } +bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg, +const SPIRVType *ResType, +

[clang] Emit constrained atan2 intrinsic for clang builtin (PR #113636)

@@ -13,7 +13,7 @@ using size_t = unsigned long; #endif // SPIR } // namespace std -float __builtin_atan2f(float, float); +float __builtin_erff(float); farzonl wrote: Just want to put a note here we are doing this because atan2 would no longer test the callin

[clang] [llvm] [HLSL] Adding HLSL `clip` function. (PR #114588)

@@ -633,7 +633,8 @@ void RequirementHandler::initAvailableCapabilities(const SPIRVSubtarget &ST) { if (ST.isAtLeastSPIRVVer(VersionTuple(1, 6))) addAvailableCaps({Capability::DotProduct, Capability::DotProductInputAll, Capability::DotProductInput4x8

[clang] Emit constrained atan2 intrinsic for clang builtin (PR #113636)

farzonl wrote: So the minute this lands our change is going to be visible across all backends. Should we add any constraint intrinsic tests to `PowerPC`, `RISCV`, `SystemZ`, etc? Here are just a handful of tests that we might want to update, but there are others: - llvm/test/CodeGen/PowerPC/

[clang] Emit constrained atan2 intrinsic for clang builtin (PR #113636)

https://github.com/farzonl approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/113636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Emit constrained atan2 intrinsic for clang builtin (PR #113636)

farzonl wrote: > @farzonl > > > Here are just a handful of tests that we might want to update, but there > > are others: > > I'm updating these tests that were called out. What others do I need to look > for? How do I know if I've found all the tests I need to update? I found them via `git g

[clang] [llvm] [HLSL][DXIL] Implement `asdouble` intrinsic (PR #114847)

farzonl wrote: LGTM, but won't sign off until the `TargetTransformInfo` issue on the precursor pr is resolved. https://github.com/llvm/llvm-project/pull/114847 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -18661,14 +18661,30 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, Value *OpMax = EmitScalarExpr(E->getArg(2)); QualType Ty = E->getArg(0)->getType(); -bool IsUnsigned = false; if (auto *VecTy = Ty->getAs()) Ty = VecTy->getElemen

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

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[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -18661,14 +18661,30 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, Value *OpMax = EmitScalarExpr(E->getArg(2)); QualType Ty = E->getArg(0)->getType(); -bool IsUnsigned = false; if (auto *VecTy = Ty->getAs()) Ty = VecTy->getElemen

[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

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[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -2559,6 +2559,12 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, } break; case Intrinsic::spv_saturate: return selectSaturate(ResVReg, ResType, I); + case Intrinsic::spv_fclamp: +return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::FCla

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -95,6 +99,144 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslSplitdouble(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); +

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -0,0 +1,98 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple dxil-pc-shadermodel6.3-library %s -fnative-half-type -emit-llvm -O1 -o - | FileCheck %s +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple spirv-vulkan-library %s -fnative-half-type -emit-ll

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/111082 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -95,6 +99,144 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslSplitdouble(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); +

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -4197,7 +4198,7 @@ static void emitWriteback(CodeGenFunction &CGF, // Release the old value. CGF.EmitARCRelease(oldValue, srcLV.isARCPreciseLifetime()); - // Otherwise, we can just do a normal lvalue store. +// Otherwise, we can just do a normal lvalue store. -

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -1698,18 +1698,27 @@ static bool CheckVectorElementCallArgs(Sema *S, CallExpr *TheCall) { return true; } -static bool CheckArgsTypesAreCorrect( +bool CheckArgTypeIsCorrect( +Sema *S, Expr *Arg, QualType ExpectedType, +llvm::function_ref Check) { + QualType Passe

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -95,6 +99,144 @@ static void initializeAlloca(CodeGenFunction &CGF, AllocaInst *AI, Value *Size, I->addAnnotationMetadata("auto-init"); } +static Value *handleHlslSplitdouble(const CallExpr *E, CodeGenFunction *CGF) { + Value *Op0 = CGF->EmitScalarExpr(E->getArg(0)); +

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -36,6 +37,11 @@ define noundef <3 x i32> @test_vector_double_split(<3 x double> noundef %d) { ; CHECK-NEXT:[[DOTUPTO116:%.*]] = insertelement <3 x i32> [[DOTUPTO015]], i32 [[DOTI1]], i64 1 ; CHECK-NEXT:[[TMP1:%.*]] = insertelement <3 x i32> [[DOTUPTO116]], i32 [[DO

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

@@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -passes='function(scalarizer)' -S -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s +; RUN: opt -passes='function(scalarizer),module(dxil-op-lower

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

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[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

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[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

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[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

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[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -1,133 +1,143 @@ // RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \ // RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF +// RUN: FileCheck %s --check-prefixes=CHE

[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -0,0 +1,130 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} farzonl wrote: What is the reason for having a

[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

@@ -0,0 +1,107 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpMemoryModel Logical GLSL450 + +define noundef i32 @f

[clang] [llvm] Adding splitdouble HLSL function (PR #109331)

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[clang] [HLSL][SPIRV] Add convergence tokens to entry point wrapper (PR #112757)

@@ -469,14 +479,22 @@ void CGHLSLRuntime::generateGlobalCtorDtorCalls() { for (auto &F : M.functions()) { if (!F.hasFnAttribute("hlsl.shader")) continue; -IRBuilder<> B(&F.getEntryBlock(), F.getEntryBlock().begin()); +auto *Token = getConvergenceToken(F.getE

[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

https://github.com/farzonl approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/113394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

@@ -83,12 +83,210 @@ entry: ret i64 %0 } -declare half @llvm.dx.clamp.f16(half, half, half) -declare float @llvm.dx.clamp.f32(float, float, float) -declare double @llvm.dx.clamp.f64(double, double, double) -declare i16 @llvm.dx.clamp.i16(i16, i16, i16) -declare i32 @llvm.dx.

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

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[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -1704,6 +1704,20 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; break; } + case Builtin::BI__builtin_hlsl_cross: { +if (SemaRef.checkArgCount(TheCall, 2)) + return true; +if (CheckVectorElementCallA

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -0,0 +1,31 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -disable-llvm-passes -verify -verify-ignore-unexpected + +void test_too_few_arg() +{ + return __builtin_hlsl_cross(); + // expected-error@-1 {{too few arg

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109180 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

https://github.com/farzonl edited https://github.com/llvm/llvm-project/pull/109180 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -0,0 +1,31 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -disable-llvm-passes -verify -verify-ignore-unexpected + +void test_too_few_arg() +{ + return __builtin_hlsl_cross(); + // expected-error@-1 {{too few arg

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

@@ -0,0 +1,57 @@ +; RUN: opt -S -dxil-intrinsic-expansion < %s | FileCheck %s --check-prefix=CHECK farzonl wrote: typicall we do `--check-prefix` if one run is different than the other. in this case they are the same. My recommendation is to drop one of thes

[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

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[clang] [llvm] Add cross builtins and cross HLSL function to DirectX and SPIR-V backend (PR #109180)

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[clang] [HLSL] Implementation of the fmod intrinsic (PR #108849)

https://github.com/farzonl approved this pull request. https://github.com/llvm/llvm-project/pull/108849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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