================
@@ -2626,6 +2671,151 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
MIRBuilder);
}
+bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I,
+ bool IsSigned) const {
+ unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
+ // zero or sign extend
+ Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
+ bool Result =
+ selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(), Opcode);
+ return Result & selectFirstBitHigh32(ResVReg, ResType, I, ExtReg, IsSigned);
----------------
farzonl wrote:
While this works, don't use a bit cast `&` with a bool do `&&`.
https://github.com/llvm/llvm-project/pull/111082
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