[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap( continue; } -if (Feature.substr(0, 7) == "+avx10.") { - HasAVX10 = true; - HasAVX512F = true; - if (Feature.substr(Feature.size() - 3, 3) == "512") { -HasEVEX512 = true; - } els

[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

e-kud wrote: I'm a little bit confused, What's the expected behavior of `+avx10.1-512 -avx10.1-256` in codegen aspect. Should we generate only instructions in the difference of sets? Or do we consider `avx10.1-256` as a base of `avx10.1-512` and if it is disabled `avx10.1-512` can't be enabled

[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)

https://github.com/e-kud approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/71318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)

https://github.com/e-kud approved this pull request. Interesting. LGTM https://github.com/llvm/llvm-project/pull/72126 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86][AVX10] Allow 64-bit mask register used without EVEX512 (PR #75571)

e-kud wrote: LGTM. Thanks! https://github.com/llvm/llvm-project/pull/75571 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [llvm] [X86][GlobalISel] Remove G_OR/G_AND/G_XOR test duplication (NFC) (PR #79088)

https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/79088 >From 8ba23b70c07f21be03102b2975046ca9a5afb90b Mon Sep 17 00:00:00 2001 From: Evgenii Kudriashov Date: Mon, 22 Jan 2024 18:00:19 -0800 Subject: [PATCH] [X86][GlobalISel] Remove G_OR/G_AND/G_XOR test duplication (NF

[clang-tools-extra] [llvm] [clang] [X86][GlobalISel] Remove G_OR/G_AND/G_XOR test duplication (NFC) (PR #79088)

https://github.com/e-kud closed https://github.com/llvm/llvm-project/pull/79088 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [mlir] [compiler-rt] [libunwind] [flang] [lldb] [llvm] [clang-tools-extra] [openmp] [lld] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

@@ -0,0 +1,80 @@ +; RUN: llc -mtriple=x86_64-pc-windows-msvc %s e-kud wrote: It seems we still have this file on `avx512-intel64` worker: https://lab.llvm.org/buildbot/#/builders/258/builds/12970 https://lab.llvm.org/buildbot/#/builders/258/builds/12971 https://

[lld] [llvm] [lldb] [libunwind] [compiler-rt] [clang] [flang] [clang-tools-extra] [mlir] [openmp] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[lld] [llvm] [lldb] [libunwind] [compiler-rt] [clang] [flang] [clang-tools-extra] [mlir] [openmp] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[lld] [llvm] [lldb] [libunwind] [compiler-rt] [clang] [flang] [clang-tools-extra] [mlir] [openmp] [BranchFolding] Fix missing predecessors of landing-pad (PR #77608)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77608 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

@@ -3963,6 +3963,60 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL +`Intel AVX10 ISA

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

@@ -3963,6 +3963,60 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL +`Intel AVX10 ISA

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

@@ -3963,6 +3963,60 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL +`Intel AVX10 ISA

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/e-kud approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[libunwind] [X86][RFC] Support AVX10 options (PR #67278)

https://github.com/e-kud approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/67278 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

https://github.com/e-kud approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/67278 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86][RFC] Support AVX10 options (PR #67278)

https://github.com/e-kud approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/67278 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86][RFC] Support AVX10 options (PR #67278)

@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap( continue; } -if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") +if (Feature.substr(0, 7) == "+avx10.") { + HasAVX10 = true; HasAVX512F = true; -if (HasAVX512F && Feature == "-avx512

[clang-tools-extra] [X86][RFC] Support AVX10 options (PR #67278)

@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap( continue; } -if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") +if (Feature.substr(0, 7) == "+avx10.") { + HasAVX10 = true; HasAVX512F = true; -if (HasAVX512F && Feature == "-avx512

[clang] [X86][RFC] Support AVX10 options (PR #67278)

@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap( continue; } -if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") +if (Feature.substr(0, 7) == "+avx10.") { + HasAVX10 = true; HasAVX512F = true; -if (HasAVX512F && Feature == "-avx512

[clang] [compiler-rt] [llvm] Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (PR #101616)

https://github.com/e-kud approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101616 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (PR #101616)

@@ -978,8 +978,20 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, bool HasLeaf24 = MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX); - if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1) && HasLeaf24 && ((EBX >> 18) & 1))

[clang] [compiler-rt] [llvm] Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (PR #101616)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/101616 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (PR #101616)

@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const { insnContext = EVEX_KB_U(IC_EVEX_XD); else if (OpPrefix == X86Local::PS) insnContext = EVEX_KB_U(IC_EVEX); +else { + errs() << "Instruction does not use

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

https://github.com/e-kud created https://github.com/llvm/llvm-project/pull/96363 Introduce more detailed diagnostics for the constrains. Also provide an opportunity for backends to provide detailed diagnostics for target specific constraints based on enabled features. We provide features as a p

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

e-kud wrote: Initially I've implemented the target errors through std::string. Then changed to diag::kind after reading InternalsManual. I'm not sure what is better. The drawback of returning diagnoistics by reference is that we can't customize them, only fixed messages. Maybe this is not a bi

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

e-kud wrote: > It's really unfortunate to have to add all this asm handling to clang. Can't > it rely on backend diagnostic remarks for this? I've tried to do the similar thing in the backend: https://reviews.llvm.org/D152332. The problem I see is that `llc`'s error handler ignores errors and

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

e-kud wrote: So, I think this PR still makes sense but without target changes, right? I've taken a look at the backend and constraints are checked in `getRegForInlineAsmConstraint`. We either need to return an error message or pass `Context` into it. The former is preferrable because a call of

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

@@ -309,6 +309,39 @@ def err_asm_invalid_type : Error< def err_ms_asm_bitfield_unsupported : Error< "an inline asm block cannot have an operand which is a bit-field">; +def asm_invalid_constraint_generic : TextSubstitution< + "invalid %select{input|output}0 constraint '%1'

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/96363 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/96363 >From 4f8504878da33925609d52912e8d0e1f64c41066 Mon Sep 17 00:00:00 2001 From: Evgenii Kudriashov Date: Fri, 21 Jun 2024 14:00:58 -0700 Subject: [PATCH 1/2] [clang] Improve diagnostics for constraints of inline asm

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/96363 >From 4f8504878da33925609d52912e8d0e1f64c41066 Mon Sep 17 00:00:00 2001 From: Evgenii Kudriashov Date: Fri, 21 Jun 2024 14:00:58 -0700 Subject: [PATCH 1/3] [clang] Improve diagnostics for constraints of inline asm

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

e-kud wrote: > I think the specific checks clang is doing here have to be part of clang: in > particular, clang needs to translate from gcc syntax to LLVM IR asm syntax, > and that requires parsing the constraints. So these checks are necessary, and > emitting better diagnostics for checks we

[clang] [clang] Improve diagnostics for constraints of inline asm (NFC) (PR #96363)

e-kud wrote: > What exactly does it mean for a constraint to conflict with a feature? The > only thing I can think of is if it somehow involves a register class that > doesn't exist on the target with the current set of target features. I guess > we could try to diagnose that, but I'm not sure

[clang] [Headers][X86] amxintrin.h - fix attributes according to Intel SDM (PR #122204)

https://github.com/e-kud created https://github.com/llvm/llvm-project/pull/122204 `tileloadd`, `tileloaddt1` and `tilestored` are part of `amx-tile` feature. The problem is observed if `__tile_loadd` intrinsic is invoked, `_tile_loadd_internal` requiring `amx-int8` is inlined into `__tile_load

[clang] [Headers][X86] amxintrin.h - fix attributes according to Intel SDM (PR #122204)

https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/122204 >From c4b07dd5c89ec97a59a3f30edaadbe50422bf87e Mon Sep 17 00:00:00 2001 From: Evgenii Kudriashov Date: Wed, 8 Jan 2025 17:15:29 -0800 Subject: [PATCH 1/2] [Headers][X86] amxintrin.h - fix attributes according to

[clang] [llvm] [X86][AVX10.2-MINMAX][NFC] Remove NE[P] from intrinsic and instruction (PR #123272)

https://github.com/e-kud approved this pull request. LGTM. Couldn't grep something `minmax`-like that hasn't been covered. https://github.com/llvm/llvm-project/pull/123272 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[clang] [llvm] [X86][AVX10.2-BF16] Remove [NE]P from intrinsic and instruction name (PR #123335)

@@ -5385,120 +5385,120 @@ let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth< } let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { - def vcmppbf16512_mask : X86Builtin<"unsigned int(_Vector<32, __bf16>, _

[clang] [llvm] [X86][AVX10.2-BF16] Remove [NE]P from intrinsic and instruction name (PR #123335)

https://github.com/e-kud approved this pull request. LGTM. However some clang-format changes for `llvm/lib/Target/X86/X86InstrFMA3Info.cpp` look reasonable for me. https://github.com/llvm/llvm-project/pull/123335 ___ cfe-commits mailing list cfe-commi

[clang] [llvm] [X86][AVX10.2-BF16] Update VCOMISBF16 intrinsics and instructions (PR #123307)

@@ -5376,12 +5376,12 @@ let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth< } let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { - def vcomsbf16eq : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)"

[clang] [llvm] [X86][AVX10.2-BF16] Update VCOMISBF16 intrinsics and instructions (PR #123307)

https://github.com/e-kud approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/123307 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86][AVX10.2-BF16] Update VCOMISBF16 intrinsics and instructions (PR #123307)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/123307 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86][AVX10.2-BF16] Update VCOMISBF16 intrinsics and instructions (PR #123307)

@@ -5376,12 +5376,12 @@ let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth< } let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { - def vcomsbf16eq : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)"

[clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (PR #124511)

e-kud wrote: I've been playing around and found that `-mavx10.2 -mno-avx10.2-512` enables `avx10.1-512` but `-mavx10.2-512 -mno-avx10.2-512` obviously doesn't. Does it make sense? It happens because when options match, they are eliminated before processing. But this is a problem not related to

[clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (PR #124511)

https://github.com/e-kud approved this pull request. LGTM. I think complete disable of AVX10 versions later or equal than specified in `-mno` is more clear than implicitly disabling only 512 version instructions. https://github.com/llvm/llvm-project/pull/124511 _

[clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (PR #124511)

e-kud wrote: > Let me know whether you are happy with this solution or not. Yes, thanks, I agree, this is better. Since we disable AVX10 version completely with any of options 256 or 512 (some kind of duplication), it means that we can't partially disable it, so these options doesn't make much

[clang] [Headers][X86] amxintrin.h - fix attributes according to Intel SDM (PR #122204)

https://github.com/e-kud closed https://github.com/llvm/llvm-project/pull/122204 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] amxintrin.h - fix attributes according to Intel SDM (PR #122204)

e-kud wrote: I'm not sure if tests are needed. Let me know. https://github.com/llvm/llvm-project/pull/122204 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86][CodeGen] - Use shift operators for const value shifts, instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)

@@ -1115,11 +1115,11 @@ _mm_srl_si64(__m64 __m, __m64 __count) /// \param __count ///A 32-bit integer value. /// \returns A 64-bit integer vector containing the right-shifted value. -static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 -_mm_srli_si64(__m64 __m, int __count) -{ -

[clang] [llvm] [X86][CodeGen] - Use shift operators for const value shifts, instead of built-ins for SSE emulation of MMX intrinsics. (PR #129197)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/129197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86][AVX10.2] Use 's_' for saturate-convert intrinsics (PR #131592)

https://github.com/e-kud approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/131592 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS (PR #132426)

https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/132426 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS (PR #132426)

https://github.com/e-kud approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/132426 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86][AVX10.2] Replace nepbh with bf16 to match with others, NFCI (PR #134240)

https://github.com/e-kud approved this pull request. LGTM. Looks like the last nep. https://github.com/llvm/llvm-project/pull/134240 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits