Author: David Sherwood
Date: 2020-07-07T09:33:20+01:00
New Revision: 9a1a7d888b53ebe5a934a8193de37da86e276f1e
URL:
https://github.com/llvm/llvm-project/commit/9a1a7d888b53ebe5a934a8193de37da86e276f1e
DIFF:
https://github.com/llvm/llvm-project/commit/9a1a7d888b53ebe5a934a8193de37da86e276f1e.diff
Author: David Sherwood
Date: 2020-06-26T08:16:40+01:00
New Revision: ae47d158a096abad43d8f9056518d83b66c5a4b7
URL:
https://github.com/llvm/llvm-project/commit/ae47d158a096abad43d8f9056518d83b66c5a4b7
DIFF:
https://github.com/llvm/llvm-project/commit/ae47d158a096abad43d8f9056518d83b66c5a4b7.diff
Author: David Sherwood
Date: 2020-06-30T08:11:41+01:00
New Revision: c02332a69399a82244298f0097bc98fafdeb3042
URL:
https://github.com/llvm/llvm-project/commit/c02332a69399a82244298f0097bc98fafdeb3042
DIFF:
https://github.com/llvm/llvm-project/commit/c02332a69399a82244298f0097bc98fafdeb3042.diff
david-arm wrote:
Hi @AaronBallman, yes the problem I found with always choosing `char` as the
alias type is that LLVM will just assume that enum types alias with absolutely
everything. This is a conservative approach that works fine, but it does
prevent important type-based alias optimisations
david-arm wrote:
Gentle ping!
https://github.com/llvm/llvm-project/pull/73515
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https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/73326
>From af76f6b6b3469fd0f5f24427c5a175c8d9d7c83a Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Fri, 24 Nov 2023 13:20:23 +
Subject: [PATCH 1/3] [Clang] Emit TBAA info for enums in C
When emitting TBAA
david-arm wrote:
> Do you think it's worth adding something to the Clang release note?
Done. Hope the documentation I added makes sense!
https://github.com/llvm/llvm-project/pull/73326
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david-arm wrote:
> I thought the suggestion was to add a few lines to
> https://github.com/llvm/llvm-project/blob/main/clang/docs/ReleaseNotes.rst
Yes you're right! For some reason I got mixed up with the LangRef, but I guess
adding something to the LangRef does no harm either. I'll put someth
https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/73326
>From af76f6b6b3469fd0f5f24427c5a175c8d9d7c83a Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Fri, 24 Nov 2023 13:20:23 +
Subject: [PATCH 1/4] [Clang] Emit TBAA info for enums in C
When emitting TBAA
https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/73326
>From af76f6b6b3469fd0f5f24427c5a175c8d9d7c83a Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Fri, 24 Nov 2023 13:20:23 +
Subject: [PATCH 1/5] [Clang] Emit TBAA info for enums in C
When emitting TBAA
@@ -196,6 +196,9 @@ C Language Changes
number of elements in the flexible array member. This information can improve
the results of the array bound sanitizer and the
``__builtin_dynamic_object_size`` builtin.
+- Enums will now be represented in TBAA metadata using their a
https://github.com/david-arm closed
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@@ -346,7 +346,9 @@ void RuntimePointerChecking::tryToCreateDiffCheck(
auto *SinkStartAR = cast(SinkStartInt);
const Loop *StartARLoop = SrcStartAR->getLoop();
if (StartARLoop == SinkStartAR->getLoop() &&
-StartARLoop == InnerLoop->getParentLoop()) {
+
https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/73515
>From 30251642f8c208c63f3f3097c337ef0d5bc633b5 Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Mon, 27 Nov 2023 13:43:26 +
Subject: [PATCH 1/4] [LoopVectorize] Improve algorithm for hoisting runtime
ch
https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/73515
>From 30251642f8c208c63f3f3097c337ef0d5bc633b5 Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Mon, 27 Nov 2023 13:43:26 +
Subject: [PATCH 1/5] [LoopVectorize] Improve algorithm for hoisting runtime
ch
https://github.com/david-arm commented:
Wow, this is a huge patch. :) It took me a few hours to work through all the
tests, and it's quite possible I've missed something. However, overall it looks
fine and I can't see any major issues. I think there is one missing test, but
once that's fixed I
https://github.com/david-arm edited
https://github.com/llvm/llvm-project/pull/70474
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@@ -0,0 +1,2503 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1
-target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-ll
https://github.com/david-arm approved this pull request.
LGTM. I think I would have preferred the patch to be split up into 3 - one for
contiguous extending loads/truncating stores, one for structured loads/stores,
and one for the gathers. That's why it took me so long to review this patch as
https://github.com/david-arm approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/70959
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https://github.com/david-arm commented:
Thanks for this! I've not done an exhaustive review, but I'll leave the
comments I have so far.
https://github.com/llvm/llvm-project/pull/70474
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@@ -9702,17 +9727,34 @@ Value *CodeGenFunction::EmitSVEMaskedStore(const
CallExpr *E,
auto VectorTy = cast(Ops.back()->getType());
auto MemoryTy = llvm::ScalableVectorType::get(MemEltTy, VectorTy);
- Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy);
+ auto Pred
@@ -2614,6 +2619,37 @@ def int_aarch64_sve_ld1_pn_x4 :
SVE2p1_Load_PN_X4_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x2 : SVE2p1_Load_PN_X2_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x4 : SVE2p1_Load_PN_X4_Intrinsic;
+//
+// SVE2.1 - Contiguous loads to quadword (single vector)
+//
@@ -9671,28 +9677,47 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const
CallExpr *E,
// The vector type that is returned may be different from the
// eventual type loaded from memory.
auto VectorTy = cast(ReturnTy);
- auto MemoryTy = llvm::ScalableVectorType::get(MemElt
@@ -9702,17 +9727,34 @@ Value *CodeGenFunction::EmitSVEMaskedStore(const
CallExpr *E,
auto VectorTy = cast(Ops.back()->getType());
auto MemoryTy = llvm::ScalableVectorType::get(MemEltTy, VectorTy);
- Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy);
+ auto Pred
@@ -9671,28 +9677,47 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const
CallExpr *E,
// The vector type that is returned may be different from the
// eventual type loaded from memory.
auto VectorTy = cast(ReturnTy);
- auto MemoryTy = llvm::ScalableVectorType::get(MemElt
@@ -2614,6 +2619,37 @@ def int_aarch64_sve_ld1_pn_x4 :
SVE2p1_Load_PN_X4_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x2 : SVE2p1_Load_PN_X2_Intrinsic;
def int_aarch64_sve_ldnt1_pn_x4 : SVE2p1_Load_PN_X4_Intrinsic;
+//
+// SVE2.1 - Contiguous loads to quadword (single vector)
+//
https://github.com/david-arm approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/71289
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https://github.com/david-arm closed
https://github.com/llvm/llvm-project/pull/73515
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https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/71538
>From 8a2af20a52fd851eaff1cfa7d50df8b994d0db0d Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Tue, 7 Nov 2023 13:57:17 +
Subject: [PATCH 1/2] [LoopVectorize] Enable hoisting of runtime checks by
defau
@@ -0,0 +1,726 @@
+
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,726 @@
+
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
david-arm wrote:
Gentle ping! https://github.com/llvm/llvm-project/pull/73515 has now landed so
I think this patch should be ready to go.
https://github.com/llvm/llvm-project/pull/71538
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david-arm wrote:
For builtins that operate purely on SVE vectors I think we've used the
convention of adding _vector_ to the test name, i.e. see
acle_sme2_vector_rshl.c, etc. Should we do the same here?
https://github.com/llvm/llvm-project/pull/74841
@@ -0,0 +1,839 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,839 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,726 @@
+
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,726 @@
+
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/david-arm approved this pull request.
LGTM! I had one minor comment, but I won't hold up the patch for it.
https://github.com/llvm/llvm-project/pull/71191
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@@ -299,6 +299,44 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+// SME2 - MOVA
+
+//
+// Single, 2 and 4 vector-group read/write intrinsics.
+//
+
+multiclass ZAWrite_VG checks> {
+ def NAME # _VG2_H : Inst<"svwrite_hor_" # n # "_vg2",
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https://github.com/david-arm created
https://github.com/llvm/llvm-project/pull/73326
When emitting TBAA information for enums in C code we currently just treat the
data as an 'omnipotent char'. However, with C strict aliasing this means we
fail to optimise certain cases. For example, in the SP
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@@ -196,11 +196,14 @@ llvm::MDNode *CodeGenTBAA::getTypeInfoHelper(const Type
*Ty) {
// Enum types are distinct types. In C++ they have "underlying types",
// however they aren't related for TBAA.
if (const EnumType *ETy = dyn_cast(Ty)) {
+if (!Features.CPlusPlus)
+
https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/73326
>From af76f6b6b3469fd0f5f24427c5a175c8d9d7c83a Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Fri, 24 Nov 2023 13:20:23 +
Subject: [PATCH 1/2] [Clang] Emit TBAA info for enums in C
When emitting TBAA
@@ -196,11 +196,14 @@ llvm::MDNode *CodeGenTBAA::getTypeInfoHelper(const Type
*Ty) {
// Enum types are distinct types. In C++ they have "underlying types",
// however they aren't related for TBAA.
if (const EnumType *ETy = dyn_cast(Ty)) {
+if (!Features.CPlusPlus)
+
@@ -0,0 +1,384 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm
david-arm wrote:
Should the file be renamed to acle_sme2_vector_selx4? This would make it
consistent with the existing acle_sme2_vector_add.c file, which also has
SVE-like instructions that only operate on SVE vectors.
https://github.com/llvm/llvm-project/pul
david-arm wrote:
Should the file be renamed to acle_sme2_vector_selx2? This would make it
consistent with the existing acle_sme2_vector_add.c file, which also has
SVE-like instructions that only operate on SVE vectors.
https://github.com/llvm/llvm-project/pul
https://github.com/david-arm approved this pull request.
LGTM! Thanks for the changes. :)
https://github.com/llvm/llvm-project/pull/73188
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https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/73515
>From 30251642f8c208c63f3f3097c337ef0d5bc633b5 Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Mon, 27 Nov 2023 13:43:26 +
Subject: [PATCH 1/3] [LoopVectorize] Improve algorithm for hoisting runtime
ch
@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+template
david-arm wrote:
Rather than create two almost identical copies of the function with a templat
@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
+
@@ -0,0 +1,280 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
@@ -0,0 +1,51 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
@@ -0,0 +1,51 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
@@ -2748,6 +2748,22 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
+MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
+ MachineBasicBlock
*B
david-arm wrote:
It looks like a few other pull requests are changing the same code around
ImmToTile. Might be good to land this smaller patch first so you can rebase the
others and reduce the diffs!
https://github.com/llvm/llvm-project/pull/72849
__
https://github.com/david-arm approved this pull request.
LGTM! C'est parfait!
https://github.com/llvm/llvm-project/pull/72849
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@@ -0,0 +1,280 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
https://github.com/david-arm commented:
This looks good to me, but I think it needs rebasing after
https://github.com/llvm/llvm-project/pull/72849 landed. It also looks like
@sdesmalen-arm left a comment about renaming ImmToTile - perhaps that could be
done in this patch?
https://github.com/l
@@ -319,7 +319,7 @@ let TargetGuard = "sme2" in {
// Spill and fill of ZT0
//
let TargetGuard = "sme2" in {
- def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck
david-arm wrote:
Gentle ping!
https://github.com/llvm/llvm-project/pull/73326
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https://github.com/david-arm approved this pull request.
LGTM. Absolute perfection!
https://github.com/llvm/llvm-project/pull/75941
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https://github.com/david-arm approved this pull request.
LGTM! A lovely patch. :)
https://github.com/llvm/llvm-project/pull/75821
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@@ -0,0 +1,816 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,816 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,816 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,816 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,816 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,816 @@
+//===- AArch64LoopIdiomTransform.cpp - Loop idiom recognition
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/76034
>From a4caa47dc8d2db75f6bb2ac3f880da4e1f6bea82 Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Tue, 19 Dec 2023 16:07:33 +
Subject: [PATCH 1/2] Add tests showing runtime checks cost with low trip
count
https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/76034
>From a4caa47dc8d2db75f6bb2ac3f880da4e1f6bea82 Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Tue, 19 Dec 2023 16:07:33 +
Subject: [PATCH 1/6] Add tests showing runtime checks cost with low trip
count
https://github.com/david-arm closed
https://github.com/llvm/llvm-project/pull/72273
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david-arm wrote:
Hi @dyung, sorry about this! It passed for me locally. It sounds like it needs
a REQUIRED aarch64-target somewhere then.
I'll try to fix it asap.
https://github.com/llvm/llvm-project/pull/72273
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david-arm wrote:
@dyung - fix pending here https://github.com/llvm/llvm-project/pull/77467
https://github.com/llvm/llvm-project/pull/72273
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david-arm wrote:
@dyung - fix pending here https://github.com/llvm/llvm-project/pull/77467
https://github.com/llvm/llvm-project/pull/72273
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@@ -34,118 +34,118 @@ define
@multi_vector_cvt_x2_bf16( %unu
;
; FCVTZS
;
-define {, }
@multi_vector_cvt_x2_f32_s32( %unused,
%zn0, %zn1) {
-; CHECK-LABEL: multi_vector_cvt_x2_f32_s32:
+define {, }
@multi_vector_cvt_x2_s32_f32( %unused,
%zn0, %zn1) {
+; CHECK-LABEL:
Author: David Sherwood
Date: 2022-07-21T15:23:00+01:00
New Revision: ceb6c23b708d4cae3fbb0a569c5ac14069524a63
URL:
https://github.com/llvm/llvm-project/commit/ceb6c23b708d4cae3fbb0a569c5ac14069524a63
DIFF:
https://github.com/llvm/llvm-project/commit/ceb6c23b708d4cae3fbb0a569c5ac14069524a63.diff
david-arm wrote:
> Hi! I wonder that have you conducted any tests to determine the potential
> performance increase of this pass in the SPEC2017 557xz benchmark? I
> attempted to apply it to the xz benchmark, but only one copy(--copies=1)
> demonstrated a significant increase(about 3%), but th
https://github.com/david-arm approved this pull request.
LGTM as well!
https://github.com/llvm/llvm-project/pull/78749
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david-arm wrote:
Gentle ping!
https://github.com/llvm/llvm-project/pull/76034
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https://github.com/david-arm updated
https://github.com/llvm/llvm-project/pull/76034
>From a4caa47dc8d2db75f6bb2ac3f880da4e1f6bea82 Mon Sep 17 00:00:00 2001
From: David Sherwood
Date: Tue, 19 Dec 2023 16:07:33 +
Subject: [PATCH 1/6] Add tests showing runtime checks cost with low trip
count
@@ -2076,16 +2081,61 @@ class GeneratedRTChecks {
LLVM_DEBUG(dbgs() << " " << C << " for " << I << "\n");
RTCheckCost += C;
}
-if (MemCheckBlock)
+if (MemCheckBlock) {
+ InstructionCost MemCheckCost = 0;
for (Instruction &I : *MemChec
@@ -31,3 +31,31 @@
// RUN: %clang -fveclib=Accelerate %s -nodefaultlibs -target
arm64-apple-ios8.0.0 -### 2>&1 | FileCheck
--check-prefix=CHECK-LINK-NODEFAULTLIBS %s
// CHECK-LINK-NODEFAULTLIBS-NOT: "-framework" "Accelerate"
+
+
+/* Verify that the correct vector library is
@@ -783,6 +783,28 @@ void tools::addLTOOptions(const ToolChain &ToolChain,
const ArgList &Args,
"-generate-arange-section"));
}
+ // Pass vector library arguments to LTO.
+ Arg *ArgVecLib = Args.getLastArg(options::OPT_fveclib);
+
@@ -783,6 +783,28 @@ void tools::addLTOOptions(const ToolChain &ToolChain,
const ArgList &Args,
"-generate-arange-section"));
}
+ // Pass vector library arguments to LTO.
+ Arg *ArgVecLib = Args.getLastArg(options::OPT_fveclib);
+
https://github.com/david-arm approved this pull request.
LGTM! An outstanding work of art @paulwalker-arm!
https://github.com/llvm/llvm-project/pull/69460
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https://github.com/david-arm edited
https://github.com/llvm/llvm-project/pull/69725
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@@ -9893,24 +9888,37 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
@@ -1016,29 +1021,24 @@ std::string Intrinsic::mangleName(ClassKind LocalCK)
const {
getMergeSuffix();
}
-void Intrinsic::emitIntrinsic(raw_ostream &OS, SVEEmitter &Emitter) const {
+void Intrinsic::emitIntrinsic(raw_ostream &OS, ACLEKind Kind) const {
bool IsOver
https://github.com/david-arm commented:
I've not done an exhaustive review, but thought I'd leave the comments I have
so far!
https://github.com/llvm/llvm-project/pull/69725
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@@ -10272,29 +10291,13 @@ Value
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
david-arm wrote:
Do we still need this code given we're now checking the ICE arguments in
GetAArch64
@@ -9893,24 +9888,37 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
@@ -9893,24 +9888,37 @@ Value *CodeGenFunction::FormSVEBuiltinResult(Value
*Call) {
return Call;
}
-Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
- const CallExpr *E) {
+void CodeGenFunction::GetAArch6
https://github.com/david-arm edited
https://github.com/llvm/llvm-project/pull/69725
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https://github.com/david-arm commented:
This looks a lot better now @kmclaughlin-arm - thanks for the changes! I just
have a couple of comments about the tests that I missed previously...
https://github.com/llvm/llvm-project/pull/69725
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@@ -0,0 +1,418 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-fe
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