================
@@ -2748,6 +2748,22 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
+MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
+ MachineBasicBlock
*BB,
+ bool IsSpill) const {
+ const TargetInstrInfo *TII = Subtarget->getInstrInfo();
+ MachineInstrBuilder MIB;
+ if (IsSpill) {
----------------
david-arm wrote:
I think this can be simplified to
```
unsigned Opc = IsSpill ? AArch64::STR_TX : AArch64::LDR_TX;
MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opc));
MIB.addReg(MI.getOperand(0).getReg());
MIB.add(MI.getOperand(1)); // Base
```
https://github.com/llvm/llvm-project/pull/72849
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