Author: ctopper
Date: Fri Jun 1 11:26:35 2018
New Revision: 333778
URL: http://llvm.org/viewvc/llvm-project?rev=333778&view=rev
Log:
[X86] Rewrite avx512vbmi unmasked and maskz macro intrinsics to be wrappers
around their __builtin function with appropriate arguments rather than just
passing ar
Author: ctopper
Date: Sun Jun 3 11:08:37 2018
New Revision: 333848
URL: http://llvm.org/viewvc/llvm-project?rev=333848&view=rev
Log:
[X86] Pass ArrayRef instead of SmallVectorImpl& to the X86 builtin helper
functions. NFC
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
Modified: cfe/trunk/li
Author: ctopper
Date: Sun Jun 3 11:08:34 2018
New Revision: 333846
URL: http://llvm.org/viewvc/llvm-project?rev=333846&view=rev
Log:
[X86] Mark the pointer arguments to expandload builtins as const consistently.
Some of them had it and some didn't. This should make them consistent.
Modified:
Author: ctopper
Date: Sun Jun 3 11:08:36 2018
New Revision: 333847
URL: http://llvm.org/viewvc/llvm-project?rev=333847&view=rev
Log:
[X86] When emitting masked loads/stores don't check for all ones mask.
This seems like a premature optimization. It's unlikely a user would pass
something the fro
Author: ctopper
Date: Sun Jun 3 11:41:22 2018
New Revision: 333850
URL: http://llvm.org/viewvc/llvm-project?rev=333850&view=rev
Log:
Revert r333848 "[X86] Pass ArrayRef instead of SmallVectorImpl& to the X86
builtin helper functions. NFC"
Looks like I missed some changes to make this work.
Mod
Author: ctopper
Date: Sun Jun 3 12:02:57 2018
New Revision: 333851
URL: http://llvm.org/viewvc/llvm-project?rev=333851&view=rev
Log:
[X86] Pass ArrayRef instead of SmallVectorImpl& to the X86 builtin helper
functions. NFC
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
Modified: cfe/trunk/li
Author: ctopper
Date: Sun Jun 3 12:42:59 2018
New Revision: 333853
URL: http://llvm.org/viewvc/llvm-project?rev=333853&view=rev
Log:
[X86] Replace __builtin_ia32_vbroadcastf128_pd256 and
__builtin_ia32_vbroadcastf128_ps256 with an unaligned load intrinsics and a
__builtin_shufflevector call.
M
Author: ctopper
Date: Sun Jun 3 15:05:19 2018
New Revision: 333855
URL: http://llvm.org/viewvc/llvm-project?rev=333855&view=rev
Log:
[X86] Explicitly make the arguments to __slwpcb intrinsic 'void'.
This is the correct way to say it takes no arguments in C.
Modified:
cfe/trunk/lib/Headers/l
Author: ctopper
Date: Sun Jun 3 16:31:01 2018
New Revision: 333858
URL: http://llvm.org/viewvc/llvm-project?rev=333858&view=rev
Log:
[X86] Remove superfluous escaped new lines from intrinsic files.
Modified:
cfe/trunk/lib/Headers/avx512fintrin.h
Modified: cfe/trunk/lib/Headers/avx512fintrin
Author: ctopper
Date: Sun Jun 3 19:56:18 2018
New Revision: 333865
URL: http://llvm.org/viewvc/llvm-project?rev=333865&view=rev
Log:
[X86] Fix a couple places that were using macro arguments twice when of the
usages could just be undefined.
One of the arguments was being used when the passthru
Author: ctopper
Date: Mon Jun 4 12:28:09 2018
New Revision: 333944
URL: http://llvm.org/viewvc/llvm-project?rev=333944&view=rev
Log:
[X86] Avoid passing _mm_undefined* to builtin_shufflevector if we are able to
pass the first input a second time.
This is more consistent with other usages of bui
Author: ctopper
Date: Mon Jun 4 20:12:14 2018
New Revision: 333980
URL: http://llvm.org/viewvc/llvm-project?rev=333980&view=rev
Log:
[X86] Mark all the builtins and intrinsics that require MMX and an SSE feature
as requiring both mmx and the sse feature.
Previously we only checked the sse featu
Author: ctopper
Date: Tue Jun 5 14:54:35 2018
New Revision: 334051
URL: http://llvm.org/viewvc/llvm-project?rev=334051&view=rev
Log:
[X86] Make __builtin_ia32_vec_ext_v2si require ICE for its index argument. Add
warnings for out of range indices for __builtin_ia32_vec_ext_v2si,
__builtin_ia32_v
Author: ctopper
Date: Tue Jun 5 15:40:03 2018
New Revision: 334054
URL: http://llvm.org/viewvc/llvm-project?rev=334054&view=rev
Log:
[X86] Implement __builtin_ia32_vec_ext_v2si correctly even though we only use
it with an index of 0.
This builtin takes an index as its second operand, but the co
Author: ctopper
Date: Tue Jun 5 17:24:55 2018
New Revision: 334057
URL: http://llvm.org/viewvc/llvm-project?rev=334057&view=rev
Log:
[X86] Add builtins for vector element insert and extract for different 128 and
256 bit vector types. Use them to implement the extract and insert intrinsics.
Prev
Author: ctopper
Date: Tue Jun 5 21:51:52 2018
New Revision: 334061
URL: http://llvm.org/viewvc/llvm-project?rev=334061&view=rev
Log:
[X86] Move the vec_set/vec_ext builtins for 64-bit elements to
BuiltinsX86_64.def.
The instructions these correspond to and the intrinsics that use them are only
Author: ctopper
Date: Wed Jun 6 19:46:02 2018
New Revision: 334159
URL: http://llvm.org/viewvc/llvm-project?rev=334159&view=rev
Log:
[X86] Add back _mask, _maskz, and _mask3 builtins for some 512-bit
fmadd/fmsub/fmaddsub/fmsubadd builtins.
Summary:
We recently switch to using a selects in the i
Author: ctopper
Date: Thu Jun 7 10:28:03 2018
New Revision: 334208
URL: http://llvm.org/viewvc/llvm-project?rev=334208&view=rev
Log:
[X86] Add back builtins for _mm_slli_si128/_mm_srli_si128 and similar
intrinsics.
We still lower them to native shuffle IR, but we do it in CGBuiltin.cpp now.
T
Author: ctopper
Date: Thu Jun 7 14:27:41 2018
New Revision: 334237
URL: http://llvm.org/viewvc/llvm-project?rev=334237&view=rev
Log:
[X86] Add builtins for VALIGNQ/VALIGND to enable proper target feature checking.
We still emit shufflevector instructions we just do it from CGBuiltin.cpp now.
Th
Author: ctopper
Date: Thu Jun 7 16:03:08 2018
New Revision: 334244
URL: http://llvm.org/viewvc/llvm-project?rev=334244&view=rev
Log:
[X86] Add builtins for shuff32x4/shuff64x2/shufi32x4/shuff64x2 to enable target
feature checking and immediate range checking.
Modified:
cfe/trunk/include/cla
Author: ctopper
Date: Thu Jun 7 17:00:21 2018
New Revision: 334249
URL: http://llvm.org/viewvc/llvm-project?rev=334249&view=rev
Log:
[X86] Add builtins for blend with immediate control to enforce target feature
requirements and check immediate range.
Modified:
cfe/trunk/include/clang/Basic/
Author: ctopper
Date: Thu Jun 7 17:59:27 2018
New Revision: 334256
URL: http://llvm.org/viewvc/llvm-project?rev=334256&view=rev
Log:
[X86] Add builtins for vpermilps/pd instructions to enable target feature
checking.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/lib/
Author: ctopper
Date: Thu Jun 7 20:24:47 2018
New Revision: 334261
URL: http://llvm.org/viewvc/llvm-project?rev=334261&view=rev
Log:
[X86] Add subvector insert and extract builtins to enable target feature
checking and immediate range checking.
Test changes are due to differences in how we gene
Author: ctopper
Date: Thu Jun 7 21:09:14 2018
New Revision: 334264
URL: http://llvm.org/viewvc/llvm-project?rev=334264&view=rev
Log:
[X86] Fix some typecasts in intrinsic headers that I messed up in r334261.
This was caught by the Header tests, but not the CodeGen tests.
Modified:
cfe/trunk
Author: ctopper
Date: Thu Jun 7 23:13:16 2018
New Revision: 334265
URL: http://llvm.org/viewvc/llvm-project?rev=334265&view=rev
Log:
[X86] Add builtins for pshufd, pshuflw, and pshufhw to enable target feature
and immediate range checking.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86
Author: ctopper
Date: Fri Jun 8 00:18:33 2018
New Revision: 334266
URL: http://llvm.org/viewvc/llvm-project?rev=334266&view=rev
Log:
[X86] Add builtins for shufps and shufpd to enable target feature and immediate
range checking.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cf
Maybe we're checking the range too early. Maybe we need to do it during IR
emission instead of during semantic analysis.
~Craig
On Fri, Jun 8, 2018 at 12:59 AM Martin Storsjö via cfe-commits <
cfe-commits@lists.llvm.org> wrote:
> On Thu, 7 Jun 2018, Craig Topper via cfe
Author: ctopper
Date: Fri Jun 8 11:00:25 2018
New Revision: 334311
URL: http://llvm.org/viewvc/llvm-project?rev=334311&view=rev
Log:
[X86] Add builtins for vpermq/vpermpd instructions to enable target feature
checking.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/li
Author: ctopper
Date: Fri Jun 8 11:00:22 2018
New Revision: 334310
URL: http://llvm.org/viewvc/llvm-project?rev=334310&view=rev
Log:
[X86] Change immediate type for some builtins from char to int.
These builtins are all handled by CGBuiltin.cpp so it doesn't much matter what
the immediate type
Author: ctopper
Date: Fri Jun 8 14:50:07 2018
New Revision: 334330
URL: http://llvm.org/viewvc/llvm-project?rev=334330&view=rev
Log:
[X86] Fold masking into subvector extract builtins.
I'm looking into making the select builtins require avx512f, avx512bw, or
avx512vl since masking operations ge
Author: ctopper
Date: Fri Jun 8 14:50:08 2018
New Revision: 334331
URL: http://llvm.org/viewvc/llvm-project?rev=334331&view=rev
Log:
[X86] Add back some masked vector truncate builtins. Custom IRgen a a few
others.
I'd like to make the select builtins require an avx512f, avx512bw, or avx512vl
Author: ctopper
Date: Fri Jun 8 15:19:42 2018
New Revision: 334334
URL: http://llvm.org/viewvc/llvm-project?rev=334334&view=rev
Log:
[X86] Add avx512 feature flags to __builtin_ia32_select*.
There are many masked intrinsics that just wrap a select around a legacy
intrinsic from a pre-avx512 ins
Author: ctopper
Date: Fri Jun 8 17:30:45 2018
New Revision: 334339
URL: http://llvm.org/viewvc/llvm-project?rev=334339&view=rev
Log:
Use SmallPtrSet instead of SmallSet in places where we iterate over the set.
SmallSet forwards to SmallPtrSet for pointer types. SmallPtrSet supports
iteration, b
Author: ctopper
Date: Sat Jun 9 23:01:42 2018
New Revision: 334359
URL: http://llvm.org/viewvc/llvm-project?rev=334359&view=rev
Log:
[X86] Remove masking from the 512-bit packed floating point add/sub/mul/div
builtins. Use select in IR instead.
Modified:
cfe/trunk/include/clang/Basic/Builti
Author: ctopper
Date: Sun Jun 10 10:27:05 2018
New Revision: 334366
URL: http://llvm.org/viewvc/llvm-project?rev=334366&view=rev
Log:
[X86] Use target independent masked expandload and compressstore intrinsics to
implement expandload/compressstore builtins.
Summary: We've had these target indepe
Author: ctopper
Date: Sun Jun 10 23:18:29 2018
New Revision: 334385
URL: http://llvm.org/viewvc/llvm-project?rev=334385&view=rev
Log:
[X86] Remove masking from dbpsadbw builtins, use select builtin instead.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/lib/Headers/avx5
Author: ctopper
Date: Mon Jun 11 09:34:10 2018
New Revision: 334416
URL: http://llvm.org/viewvc/llvm-project?rev=334416&view=rev
Log:
[X86] Properly account for the immediate being multiplied by 8 in the immediate
range checking for BI__builtin_ia32_psrldqi128 and friends.
The limit was set to 1
Author: ctopper
Date: Mon Jun 11 10:06:01 2018
New Revision: 334422
URL: http://llvm.org/viewvc/llvm-project?rev=334422&view=rev
Log:
[X86] Fix operand order in the shuffle created for blend builtins.
This was broken when the builtin was added in r334249.
Modified:
cfe/trunk/lib/CodeGen/CGBu
Author: ctopper
Date: Wed Jun 13 00:19:28 2018
New Revision: 334577
URL: http://llvm.org/viewvc/llvm-project?rev=334577&view=rev
Log:
[X86] Remove masking from avx512vbmi2 concat and shift by immediate builtins.
Use select builtins instead.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86
Author: ctopper
Date: Thu Jun 14 11:43:52 2018
New Revision: 334751
URL: http://llvm.org/viewvc/llvm-project?rev=334751&view=rev
Log:
[X86] Add inline assembly versions of _InterlockedExchange_HLEAcquire/Release
and _InterlockedCompareExchange_HLEAcquire/Release for MSVC compatibility.
Clang/LLV
Author: ctopper
Date: Thu Jun 14 15:02:35 2018
New Revision: 334773
URL: http://llvm.org/viewvc/llvm-project?rev=334773&view=rev
Log:
[X86] Rename __builtin_ia32_pslldqi128 to __builtin_ia32_pslldqi128_byteshift
and similar for other sizes. Remove the multiply by 8 from the header files.
The pre
Author: ctopper
Date: Fri Jun 15 10:03:32 2018
New Revision: 334846
URL: http://llvm.org/viewvc/llvm-project?rev=334846&view=rev
Log:
[X86] The immediate argument to getmantpd*_mask should be an ICE and it should
only be 4 bits wide.
We already checked this for the scalar version, but missed the
Author: ctopper
Date: Fri Jun 15 10:40:37 2018
New Revision: 334847
URL: http://llvm.org/viewvc/llvm-project?rev=334847&view=rev
Log:
[X86] __builtin_ia32_prord512_mask, __builtin_ia32_prorq512_mask,
__builtin_ia32_shufpd should only accept an ICE constant.
The rotates also need to check for the
Author: ctopper
Date: Tue Jun 19 17:31:39 2018
New Revision: 335086
URL: http://llvm.org/viewvc/llvm-project?rev=335086&view=rev
Log:
[X86] Undefine _mm512_mask_reduce_operator macro in avx512fintrin.h before
redefining it.
Modified:
cfe/trunk/lib/Headers/avx512fintrin.h
Modified: cfe/trunk
Author: ctopper
Date: Wed Jun 20 22:01:01 2018
New Revision: 335200
URL: http://llvm.org/viewvc/llvm-project?rev=335200&view=rev
Log:
[X86] Remove masking from the 512-bit floating point max/min builtins. Use
select in IR instead.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
c
Author: ctopper
Date: Thu Jun 21 09:41:28 2018
New Revision: 335253
URL: http://llvm.org/viewvc/llvm-project?rev=335253&view=rev
Log:
[X86] Rewrite the add/mul/or/and reduction intrinsics to make better use of
other intrinsics and remove undef shuffle indices.
Similar to what was done to max/min
Author: ctopper
Date: Thu Jun 21 10:07:04 2018
New Revision: 335259
URL: http://llvm.org/viewvc/llvm-project?rev=335259&view=rev
Log:
[Intrinsics] Add/move some builtin declarations in intrin.h to get
ms-intrinsics.c to not issue warnings
ud2 and int2c were missing declarations entirely. And the
Author: ctopper
Date: Thu Jun 21 11:56:30 2018
New Revision: 335270
URL: http://llvm.org/viewvc/llvm-project?rev=335270&view=rev
Log:
[X86] Correct the inline assembly implementations of __movsb/w/d/q and
__stosw/d/q to mark registers/memory as modified
The inline assembly for these didn't mark
Author: ctopper
Date: Thu Jun 21 16:39:47 2018
New Revision: 335308
URL: http://llvm.org/viewvc/llvm-project?rev=335308&view=rev
Log:
[X86] Update handling in CGBuiltin to be tolerant of out of range immediates.
D48464 contains changes that will loosen some of the range checks in
SemaChecking to
Author: ctopper
Date: Wed Oct 10 00:43:45 2018
New Revision: 344117
URL: http://llvm.org/viewvc/llvm-project?rev=344117&view=rev
Log:
[X86] Remove FeatureRTM from Skylake processor list
Summary:
There are a LOT of Skylakes and later without TSX-NI. Examples:
- SKL:
https://ark.intel.com/products
Author: ctopper
Date: Fri Oct 19 18:30:00 2018
New Revision: 344824
URL: http://llvm.org/viewvc/llvm-project?rev=344824&view=rev
Log:
[X86] When checking the bits in cpu_features for function multiversioning
dispatcher in the resolver, make sure all the required bits are set. Not just
one of the
Author: ctopper
Date: Fri Oct 19 20:51:52 2018
New Revision: 344832
URL: http://llvm.org/viewvc/llvm-project?rev=344832&view=rev
Log:
[X86] Add support for more than 32 features for __builtin_cpu_is
libgcc supports more than 32 features by adding a new 32-bit variable
__cpu_features2.
This adds
Author: ctopper
Date: Sat Oct 20 12:28:50 2018
New Revision: 344861
URL: http://llvm.org/viewvc/llvm-project?rev=344861&view=rev
Log:
[X86] Add missing intrinsics to match icc.
This adds
_mm_and_epi32, _mm_and_epi64
_mm_andnot_epi32, _mm_andnot_epi64
_mm_or_epi32, _mm_or_epi64
_mm_xor_epi32, _mm_
Author: ctopper
Date: Sat Oct 20 12:28:52 2018
New Revision: 344862
URL: http://llvm.org/viewvc/llvm-project?rev=344862&view=rev
Log:
[X86] Add more intrinsics to match icc.
This adds
_mm_loadu_epi8, _mm256_loadu_epi8, _mm512_loadu_epi8
_mm_loadu_epi16, _mm256_loadu_epi16, _mm512_loadu_epi16
_mm_
Author: ctopper
Date: Mon Oct 22 10:59:58 2018
New Revision: 344929
URL: http://llvm.org/viewvc/llvm-project?rev=344929&view=rev
Log:
[X86] Add new features to the priority list for target attribute
multiversioning.
Modified:
cfe/trunk/include/clang/Basic/X86Target.def
Modified: cfe/trunk/i
Author: ctopper
Date: Mon Oct 22 17:15:37 2018
New Revision: 344978
URL: http://llvm.org/viewvc/llvm-project?rev=344978&view=rev
Log:
[X86] Remove 'rtm' feature from KNL.
I'm unsure if KNL has this feature, but the backend never thought it did, only
clang did. The predefined-arch-macros test los
Author: ctopper
Date: Wed Oct 24 11:45:44 2018
New Revision: 345176
URL: http://llvm.org/viewvc/llvm-project?rev=345176&view=rev
Log:
[CodeGen] Update test checks missed in r345168.
These tests don't run unless the aarch64 target is registered and my testing
had been on an x86 only build directo
Author: ctopper
Date: Wed Oct 24 22:04:35 2018
New Revision: 345237
URL: http://llvm.org/viewvc/llvm-project?rev=345237&view=rev
Log:
[CodeGen] Always emit the 'min-legal-vector-width' attribute even when the
value is 0.
The X86 backend will need to see the attribute to make decisions. If it isn
Author: ctopper
Date: Sun Jan 13 16:03:55 2019
New Revision: 351029
URL: http://llvm.org/viewvc/llvm-project?rev=351029&view=rev
Log:
[X86] Remove mask parameter from vpshufbitqmb intrinsics. Change result to a
vXi1 vector.
We'll do the scalar<->vXi1 conversions with bitcasts in IR.
Fixes PR402
Author: ctopper
Date: Mon Jan 14 00:46:51 2019
New Revision: 351036
URL: http://llvm.org/viewvc/llvm-project?rev=351036&view=rev
Log:
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in
IR instead.
Fixes PR40259
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86
Author: ctopper
Date: Mon Jan 14 21:03:18 2019
New Revision: 351160
URL: http://llvm.org/viewvc/llvm-project?rev=351160&view=rev
Log:
[X86] Make _xgetbv/_xsetbv on non-windows platforms
Summary:
This patch attempts to redo what was tried in r278783, but was reverted.
These intrinsics should be a
^
>> lib/clang/include/xsaveintrin.h:49:53: note: expanded from macro '_xgetbv'
>> #define _xgetbv(A) __builtin_ia32_xgetbv((long long)(A))
>>
>> On Tue, Jan 15, 2019 at 6:06 AM Craig Topper via cfe-commits <
>> cfe-commits@lists.llvm.org&
Author: ctopper
Date: Tue Jan 15 11:58:36 2019
New Revision: 351230
URL: http://llvm.org/viewvc/llvm-project?rev=351230&view=rev
Log:
[Nios2] Remove Nios2 backend
As mentioned here
http://lists.llvm.org/pipermail/llvm-dev/2019-January/129121.html This backend
is incomplete and has not been main
expected ')'
>>>> V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
>>>> ^
>>>> src/x64/assembler-x64.cc:35:20: note: to match this '('
>>>> V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
>>>&g
cro 'V8_INLINE'
>>>>>> # define V8_INLINE inline __attribute__((always_inline))
>>>>>>^
>>>>>> src/x64/assembler-x64.cc:35:41: error: expected ')'
>>>>>> V8_INLINE uint64_t _xgetbv(unsigned in
Author: ctopper
Date: Tue Jan 15 23:17:14 2019
New Revision: 351301
URL: http://llvm.org/viewvc/llvm-project?rev=351301&view=rev
Log:
[X86] Correct the type string for __builtin_ia32_gathersiv16sf to make the
indices an integer type not an FP type.
The element count and width remain the same. Th
Author: ctopper
Date: Wed Jan 16 14:34:33 2019
New Revision: 351390
URL: http://llvm.org/viewvc/llvm-project?rev=351390&view=rev
Log:
[X86] Add versions of the avx512 gather intrinsics that take the mask as a vXi1
vector instead of a scalar
We need to custom handle these so we can turn the scala
Author: ctopper
Date: Wed Jan 16 14:56:25 2019
New Revision: 351391
URL: http://llvm.org/viewvc/llvm-project?rev=351391&view=rev
Log:
Recommit r351160 "[X86] Make _xgetbv/_xsetbv on non-windows platforms"
V8 has been fixed now.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/
Author: ctopper
Date: Wed Jan 16 16:34:19 2019
New Revision: 351408
URL: http://llvm.org/viewvc/llvm-project?rev=351408&view=rev
Log:
[X86] Add custom emission for the avx512 scatter builtins to convert from
scalar integer to vXi1 for the mask arguments to the intrinsics.
Modified:
cfe/trunk
Author: ctopper
Date: Fri Jan 18 09:51:51 2019
New Revision: 351568
URL: http://llvm.org/viewvc/llvm-project?rev=351568&view=rev
Log:
[X86] Only define _XCR_XFEATURE_ENABLED_MASK in xsaveintrin.h when _MSC_VER is
defined. Remove from intrin.h.
I think this was my intention when I added it xsavei
Author: ctopper
Date: Sun Jan 20 11:04:56 2019
New Revision: 351694
URL: http://llvm.org/viewvc/llvm-project?rev=351694&view=rev
Log:
[X86] Remove the cvtuqq2ps256/cvtqq2ps256 mask builtins. Replace with
uitofp/sitofp and select.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: kri
Author: ctopper
Date: Sun Jan 20 15:49:50 2019
New Revision: 351708
URL: http://llvm.org/viewvc/llvm-project?rev=351708&view=rev
Log:
[X86] Add missing test cases for some int/fp->fp conversion intrinsics with
rounding mode. Use non-default rounding mode on some tests.
For some reason we were mi
Author: ctopper
Date: Thu Jan 24 23:08:22 2019
New Revision: 352173
URL: http://llvm.org/viewvc/llvm-project?rev=352173&view=rev
Log:
[X86] Remove mask and passthru arguments from vpconflict builtins. Use select
in IR instead.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/t
Author: ctopper
Date: Fri Jan 25 18:42:01 2019
New Revision: 352267
URL: http://llvm.org/viewvc/llvm-project?rev=352267&view=rev
Log:
[X86] Custom codegen 512-bit cvt(u)qq2tops, cvt(u)qqtopd, and cvt(u)dqtops
intrinsics.
Summary:
The 512-bit cvt(u)qq2tops, cvt(u)qqtopd, and cvt(u)dqtops intrinsi
Author: ctopper
Date: Sun Jan 27 23:03:10 2019
New Revision: 352344
URL: http://llvm.org/viewvc/llvm-project?rev=352344&view=rev
Log:
[X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types
for the mask argument.
Custom lower the builtins to these intrinsics. This enables th
Author: ctopper
Date: Tue Nov 27 10:05:14 2018
New Revision: 347682
URL: http://llvm.org/viewvc/llvm-project?rev=347682&view=rev
Log:
[X86] Add -march=cascadelake support in clang.
This is skylake-avx512 with the addition of avx512vnni ISA.
Patch by Jianping Chen
Differential Revision: https://
Author: ctopper
Date: Sun Dec 9 22:07:59 2018
New Revision: 348738
URL: http://llvm.org/viewvc/llvm-project?rev=348738&view=rev
Log:
[X86] Remove the addcarry builtins. Leaving only the addcarryx builtins since
that matches gcc.
The addcarry and addcarryx builtins do the same thing. The only di
Author: ctopper
Date: Tue Feb 26 11:20:04 2019
New Revision: 354915
URL: http://llvm.org/viewvc/llvm-project?rev=354915&view=rev
Log:
[X86] Add 'znver2' and 'cascadelake' to the __builtin_cpu_is test.
These are supported by at least libgcc trunk so we can include them now.
Modified:
cfe/trun
Author: ctopper
Date: Thu Mar 7 17:15:18 2019
New Revision: 355659
URL: http://llvm.org/viewvc/llvm-project?rev=355659&view=rev
Log:
[X86] Make x86-intrinsics-headers-clean.cpp stricter.
Remove the -Wno-ignored-attributes.
Add -fno-lax-vector-conversions
Also use -ffreestanding instead of defi
Author: ctopper
Date: Tue Mar 12 22:14:52 2019
New Revision: 356008
URL: http://llvm.org/viewvc/llvm-project?rev=356008&view=rev
Log:
[X86] Remove 'cx16' from 'prescott' and 'yonah' as they are 32-bit only CPUs
and cmpxchg16b requires 64-bit mode.
Modified:
cfe/trunk/lib/Basic/Targets/X86.cp
Author: ctopper
Date: Tue Mar 12 22:14:50 2019
New Revision: 356007
URL: http://llvm.org/viewvc/llvm-project?rev=356007&view=rev
Log:
[X86] Add 'yonah' test to predefined-arch-macros.c test.
Modified:
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
Modified: cfe/trunk/test/Preprocessor/
Author: ctopper
Date: Wed Mar 13 22:45:42 2019
New Revision: 356118
URL: http://llvm.org/viewvc/llvm-project?rev=356118&view=rev
Log:
[X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode.
Summary:
This define should correspond to CMPXCHG16B being available which requires
64-bit m
Author: ctopper
Date: Mon Mar 18 15:25:57 2019
New Revision: 356423
URL: http://llvm.org/viewvc/llvm-project?rev=356423&view=rev
Log:
[X86] Add gcc rotate intrinsics to ia32intrin.h
This is another attempt at what Erich Keane tried to do in r355322.
This adds rolb, rolw, rold, rolq and their ror
Author: ctopper
Date: Wed Mar 20 00:31:18 2019
New Revision: 356537
URL: http://llvm.org/viewvc/llvm-project?rev=356537&view=rev
Log:
[X86] Separate PentiumPro and i686. They aren't aliases in the backend.
PentiumPro has HasNOPL set in the backend. i686 does not.
Despite having a function that l
Author: ctopper
Date: Wed Mar 20 10:26:51 2019
New Revision: 356580
URL: http://llvm.org/viewvc/llvm-project?rev=356580&view=rev
Log:
[X86] Remove getCPUKindCanonicalName which is unused.
Differential Revision: https://reviews.llvm.org/D59578
Modified:
cfe/trunk/lib/Basic/Targets/X86.cpp
Author: ctopper
Date: Wed Mar 20 13:25:28 2019
New Revision: 356609
URL: http://llvm.org/viewvc/llvm-project?rev=356609&view=rev
Log:
[X86] Add __crc32b/__crc32w/__crc32d/__crc32q intrinsics to match gcc and icc.
gcc has these intrinsics in ia32intrin.h as well. And icc implements them
though the
Author: ctopper
Date: Thu Mar 21 10:33:20 2019
New Revision: 356686
URL: http://llvm.org/viewvc/llvm-project?rev=356686&view=rev
Log:
[X86] Use the CPUKind enum from PROC_ALIAS to directly get the CPUKind in
fillValidCPUList.
We were using getCPUKind which translates the string to the enum also
Author: ctopper
Date: Thu Mar 21 10:43:53 2019
New Revision: 356689
URL: http://llvm.org/viewvc/llvm-project?rev=356689&view=rev
Log:
[X86] Add __popcntd and __popcntq to ia32intrin.h to match gcc and icc. Remove
popcnt feature flag from _popcnt32/_popcnt64 and move to ia32intrin.h to match
gcc
Author: ctopper
Date: Thu Mar 21 13:07:24 2019
New Revision: 356706
URL: http://llvm.org/viewvc/llvm-project?rev=356706&view=rev
Log:
[Driver] Pass -malign-double from the driver to the cc1 command line
-malign-double is currently only implemented in the -cc1 interface. But its
declared in Optio
Author: ctopper
Date: Thu Mar 21 13:36:08 2019
New Revision: 356709
URL: http://llvm.org/viewvc/llvm-project?rev=356709&view=rev
Log:
[X86] Correct the value of MaxAtomicInlineWidth for pre-586 cpus
Use the new cx8 feature flag that was added to the backend to represent support
for cmpxchg8b. Us
Author: ctopper
Date: Sat Mar 23 17:56:52 2019
New Revision: 356848
URL: http://llvm.org/viewvc/llvm-project?rev=356848&view=rev
Log:
[X86] Add BSR/BSF/BSWAP intrinsics to ia32intrin.h to match gcc.
Summary:
These are all implemented by icc as well.
I made bit_scan_forward/reverse forward to the
Author: ctopper
Date: Sun Mar 24 11:00:20 2019
New Revision: 356862
URL: http://llvm.org/viewvc/llvm-project?rev=356862&view=rev
Log:
[X86] Make _bswap intrinsic a function instead of a macro to hopefully fix the
chromium build.
This intrinsic was added in r356848 but was implemented as a macro
Could
> _bswap be an inline function instead?
>
> https://bugs.chromium.org/p/chromium/issues/detail?id=945172
>
> On Sat, Mar 23, 2019 at 8:55 PM Craig Topper via cfe-commits <
> cfe-commits@lists.llvm.org> wrote:
>
>> Author: ctopper
>> Date: Sat Mar
Author: ctopper
Date: Mon Apr 8 10:05:57 2019
New Revision: 357924
URL: http://llvm.org/viewvc/llvm-project?rev=357924&view=rev
Log:
[X86] Add some fp to integer conversion intrinsics to
Sema::CheckX86BuiltinRoundingOrSAE so their rounding controls will be checked.
If we don't check this in the
Author: ctopper
Date: Mon Apr 15 10:17:35 2019
New Revision: 358427
URL: http://llvm.org/viewvc/llvm-project?rev=358427&view=rev
Log:
[X86] Restore the pavg intrinsics.
The pattern we replaced these with may be too hard to match as demonstrated by
PR41496 and PR41316.
This patch restores the int
Author: ctopper
Date: Mon Apr 15 11:39:36 2019
New Revision: 358435
URL: http://llvm.org/viewvc/llvm-project?rev=358435&view=rev
Log:
[X86] Improve avx512-kconstraints-att_inline_asm.c to not be easily defeated by
deadcode elimination. Improve CHECK lines to check IR types used. NFC
I plan to us
Author: ctopper
Date: Wed Sep 26 10:01:44 2018
New Revision: 343126
URL: http://llvm.org/viewvc/llvm-project?rev=343126&view=rev
Log:
[X86] For lzcnt/tzcnt intrinsics use cttz/ctlz intrinsics with zero_undef flag
set to false.
Previously we used a select and the zero_undef=true intrinsic. In -O2
Author: ctopper
Date: Fri Sep 28 10:09:51 2018
New Revision: 343343
URL: http://llvm.org/viewvc/llvm-project?rev=343343&view=rev
Log:
[X86] Add the movbe instruction intrinsics from icc.
These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide
website.
All the backend supp
Author: ctopper
Date: Sat Sep 29 10:49:42 2018
New Revision: 343388
URL: http://llvm.org/viewvc/llvm-project?rev=343388&view=rev
Log:
[X86] Add more of the icc unaligned load/store to/from 128 bit vector intrinsics
Summary:
This patch adds
_mm_loadu_si32
_mm_loadu_si16
_mm_storeu_si64
_mm_storeu_
Author: ctopper
Date: Mon Feb 4 22:13:14 2019
New Revision: 353142
URL: http://llvm.org/viewvc/llvm-project?rev=353142&view=rev
Log:
[X86] Change MS inline asm clobber list filter to check for 'fpsr' instead of
'fpsw' after D57641.
Summary: The backend used to print the x87 FPSW register as 'fp
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