[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3896 +// encoder. Prefixes |= X86::IP_USE_VEX3; +Prefixes |= X86::Force_VEX3Encoding; Why do we need Force_VEX3Encoding and IP_USE_VEX3?

[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp:354 + else if (Flags & X86::Force_VEX2Encoding) +O << "\t{vex2}"; + else if (Flags & X86::Force_VEX3Encoding) craig.topper wrote: > Is it important tha

[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp:358 + else if (Flags & X86::Force_EVEXEncoding) +O << "\t{evex}"; } We also need to print {disp8} and {disp32} here to fix the same bug with those rig

[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

craig.topper added a comment. Does this bug only effect the printing of inline assembly to a .s file? The encoder should work correctly even without this I think? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90009/new/ https://reviews.llvm.org/D9

[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3896 +// encoder. Prefixes |= X86::IP_USE_VEX3; +Prefixes |= X86::Force_VEX3Encoding; LiuChen3 wrote: > craig.topper wrote: > > Why do we need Force_VEX3En

[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90009/new/ https://reviews.llvm.org/D90009 _

[PATCH] D87528: Enable '#pragma STDC FENV_ACCESS' in frontend

craig.topper added a comment. In D87528#2357043 , @mibintc wrote: > Actually kludging it by just removing the assert isn't going to work. I'll > ping Pengfei to see about developing a patch for this problem. This is likely a WebAssembly backend problem.

[PATCH] D75579: Replace MCTargetOptionsCommandFlags.inc and CommandFlags.inc by runtime-registration

craig.topper added inline comments. Comment at: llvm/tools/llvm-mc/CMakeLists.txt:6 AllTargetsInfos + CodeGen MC Why did this patch need to make llvm-mc dependent on CodeGen? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revi

[PATCH] D90544: [X86] NOT FOR COMMIT. Emit lifetime markers for MXCSR temporaries.

craig.topper created this revision. craig.topper added reviewers: andreadb, RKSimon, spatel. Herald added a project: clang. Herald added a subscriber: cfe-commits. craig.topper requested review of this revision. My experimental patch for PR48033 so I can share it in the bug. Repository: rG LLV

[PATCH] D102822: [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.

craig.topper added a comment. Am I mistaken, or does this test already pass without these changes? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102822/new/ https://reviews.llvm.org/D102822 ___ cfe-commi

[PATCH] D102839: [RISCV][Clang] Add -mno-idiv option to disable hardware int division

craig.topper added a comment. Isn't the gcc name for this -mno-div? Should we be consistent? Comment at: clang/lib/Basic/Targets/RISCV.cpp:154 + if (DisableHardwareIntDiv) { +Builder.defineMacro("__riscv_no_idiv"); } Does gcc also have this define? Why

[PATCH] D102995: errorUnsupported should be non-fatal

craig.topper added a comment. "fatal" in the comment means don't diagnose any additional errors and immediately stop. We attempt to recover to detect more errors, but the emitted binary code is likely incorrect. I don't think we can just emit a warning. Repository: rG LLVM Github Monorepo C

[PATCH] D102995: errorUnsupported should be non-fatal

craig.topper added a comment. X86-64 ABI requires float/double arguments to use XMM registers. All x86-64 CPUs have SSE2. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102995/new/ https://reviews.llvm.org/D102995 _

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaRISCV.cpp:21 + PP.getIdentifierTable(), PP.getLangOpts(), Builtin::RISCV_VECTOR_KIND); + Builtin::RegisterOverloadBuiltinFunc F = [](Sema &S, const Builtin::Info &BI, +

[PATCH] D103313: [RISCV][Clang] Implement support for zmmul-experimental

craig.topper added a comment. Do we need to add this to RISCVTargetStreamer::emitTargetAttributes? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103313/new/ https://reviews.llvm.org/D103313 ___ cfe-commi

[PATCH] D103491: [ADT] Move DenseMapInfo for ArrayRef/StringRef into respective headers (NFC)

craig.topper added inline comments. Comment at: llvm/include/llvm/ADT/ArrayRef.h:595-600 + if (RHS.data() == getEmptyKey().data()) +return LHS.data() == getEmptyKey().data(); + if (RHS.data() == getTombstoneKey().data()) +return LHS.data() == getTombston

[PATCH] D102822: [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp:3 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-v \ +// RUN: -emit-llvm -O1 -o - %s | FileCheck %s

[PATCH] D103527: [Clang][RISCV] Implement vlseg and vlsegff.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:807 + // intrinsic: (ptr, vl) + SmallVector Operands = {Ops[NF], Ops[NF + 1]}; + llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); This can be a `llvm

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:772 + // Parse records + SmallVector, 512> Defs; + std::vector RV = Records.getAllDerivedDefinitions("RVVBuiltin"); This getAllDerivedDefinitions, loop, call createRVVIntrin

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:772 + // Parse records + SmallVector, 512> Defs; + std::vector RV = Records.getAllDerivedDefinitions("RVVBuiltin"); craig.topper wrote: > craig.topper wrote: > > This getAll

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

craig.topper updated this revision to Diff 318548. craig.topper added a comment. Remove reference to version from the rori comment. The version doesn't really matter, I doubt the encoding will ever be added. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm

[PATCH] D94582: [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.

This revision was automatically updated to reflect the committed changes. Closed by commit rGb825278364d9: [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llv

[PATCH] D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it.

This revision was automatically updated to reflect the committed changes. Closed by commit rG4e6ad11bc6f2: [RISCV] Add Zba feature and move add.uw and slli.uw to it. (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D94617?vs=318217&id=318616#toc Repository: rG LL

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG20f2e32d2c54: [RISCV] Update B extension version to 0.93. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTI

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

craig.topper added a comment. I wonder if these types should be prefixed with "__clang_" like AArch64 tuple types? Comment at: clang/lib/AST/ASTContext.cpp:3875 +IsFP) \ + if (!EltTy->isBooleanType() &&

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

craig.topper added a comment. In D92715#2544178 , @HsiangKai wrote: > In D92715#2520925 , @craig.topper > wrote: > >> I wonder if these types should be prefixed with "__clang_" like AArch64 >> tuple types? > > It

[PATCH] D109799: [RISCV] add Half-precision test for clang

craig.topper added a comment. This patch is really large and touches tests for integer operations. Can you just pre-commit the removal of lines with just comment characters. No need to review for that. That should reduce the noise in this patch. Repository: rG LLVM Github Monorepo CHANGES S

[PATCH] D109799: [RISCV] add Half-precision test for clang

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109799/new/ https://reviews.llvm.org/D109799 ___

[PATCH] D109658: [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:2972 #define _mm_mask_fcmadd_round_sch(A, U, B, C, R) \ ((__m128h)__builtin_ia32_selectps_128( \ (__mmask8)(U & 1)

[PATCH] D109658: [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:2972 #define _mm_mask_fcmadd_round_sch(A, U, B, C, R) \ ((__m128h)__builtin_ia32_selectps_128( \ (__mmask8)(U & 1)

[PATCH] D109658: [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109658/new/ https://reviews.llvm.org/D109658 ___

[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105092/new/ https://reviews.llvm.org/D105092 ___

[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

craig.topper requested changes to this revision. craig.topper added inline comments. This revision now requires changes to proceed. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1315 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, -

[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. Nevermind. LGTM Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1315 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,

[PATCH] D110336: [X86][FP16] Add more builtins to avoid multi evaluation problems & add 2 missed intrinsics

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsX86.def:2021 TARGET_BUILTIN(__builtin_ia32_vfmaddcph256_maskz, "V8fV8fV8fV8fUc", "ncV:256:", "avx512fp16,avx512vl") -TARGET_BUILTIN(__builtin_ia32_vfmaddcph512_mask, "V16fV16fV16fV16fUsIi", "nc

[PATCH] D109322: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c:8 -// // CHECK-RV64-LABEL: @test_vadd_vv_i8mf8( Please pre-commit this change to reduce noise Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D110336: [X86][FP16] Add more builtins to avoid multi evaluation problems & add 2 missed intrinsics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110336/new/ https://reviews.llvm.org/D110336 ___

[PATCH] D110871: [RISCV] Remove rvbproposedc extension

craig.topper created this revision. craig.topper added reviewers: asb, luismarques, evandro, HsiangKai, frasercrmck, jrtc27, PaoloS, kito-cheng, khchen, arcbbb. Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr, jdoerfert, apazos, sameer.abuasal, s.egerton, Jim, benna, psn

[PATCH] D110871: [RISCV] Remove Zbproposedc extension

This revision was automatically updated to reflect the committed changes. Closed by commit rGa21c557955c6: [RISCV] Remove Zbproposedc extension (authored by craig.topper). Herald added a project: clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1

[PATCH] D110216: [clang] retain type sugar in auto / template argument deduction

craig.topper added inline comments. Comment at: clang/include/clang/ASTMatchers/ASTMatchersInternal.h:1032 if (const auto *S = dyn_cast(&Node)) { - EffectiveType = S->getDeducedType().getTypePtrOrNull(); - if (!EffectiveType) -return false; + QualType

[PATCH] D110216: [clang] retain type sugar in auto / template argument deduction

craig.topper added a comment. Looks like this fixes PR51282. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110216/new/ https://reviews.llvm.org/D110216 ___ cfe-commits mailing list cfe-commits@lists.llvm

[PATCH] D106044: [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106044/new/ https://reviews.llvm.org/D106044 ___

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:89 +#define BUILTIN(ID, TYPE, ATTRS) \ + {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, +#include "clang/Basic/BuiltinsRISCV.de

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new/ https://reviews.llvm.org/D92715 _

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

craig.topper added a comment. Is this change specific to fixed vectors declared with arm_sve_vector_bits or any of the subclasses of VectorType? If it allows the others, how do we know for sure that there are enough bits in the scalable type for the fixed vector. I ask because RISCV is also usi

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:1 +#if defined(BUILTIN) && !defined(RISCVV_BUILTIN) +#define RISCVV_BUILTIN(ID, TYPE, ATTRS) BUILTIN(ID, TYPE, ATTRS) Need copyright header Comment at:

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93446/new/ https://reviews.llvm.org/D93446 _

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:59 #ifndef RVV_VECTOR_TYPE_FLOAT #define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true) -

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

craig.topper added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:10672 + if (Ty->isRecordType() && !Ty->getAsRecordDecl()->field_empty() && + Ty->getAsRecordDecl()->field_begin()->getType()->isSizelessType()) Are we able to test this yet?

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1024 +#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \ + QualType SingletonId; #include "clang/Basic/RISCVVTypes.def" Why is this QualType and not

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1024 +#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \ + QualType SingletonId; #include "clang/Basic/RISCVVTypes.def" craig.topper wrote: > Why is

[PATCH] D97264: [RISCV] Define types for Zvlsseg.

craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1024 +#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NE, EB, NF, IsSigned, IsFP) \ + QualType SingletonId; #include "clang/Basic/RISCVVTypes.def" HsiangKai wrote: > craig.top

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:148 + // If HasMask, this flag states that this builtin has a maskedoff operand. It + // is always the first operand. + bit HasMaskedOffOperand = true; Isn't mask the fir

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:567 + // Compute type transformers + for (char I : Transformer.take_front(Transformer.size() - 1)) { +switch (I) { Can we do Transformer = Transformer.drop_back() right b

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:70 + // passing to the BUILTIN() macro in Builtins.def. + const std::string &builtin_str() const { return BuiltinStr; } + These method names should use CamelCase and start wi

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:873 + // Dump switch body when the ir name changes from previous iteration. + RVVIntrinsic *PrevDef = Defs.begin()->get(); + for (auto &Def : Defs) { khchen wrote: > craig.t

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:678 +else + OS << ", Ops[" << Twine(static_cast(Idx)) << "]->getType()"; + } We don't need Twine here Comment at: clang/utils/TableGen/RISCVVEmitte

[PATCH] D99675: [llvm][clang] Create new intrinsic llvm.arith.fence to control FP optimization at expression level

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IRBuilder.h:903 + const Twine &Name = "") { +return CreateIntrinsic(Intrinsic::arithmetic_fence, {DstType}, {Val}, nullptr, + Name); --

[PATCH] D102822: [Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp:3 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-v \ +// RUN: -emit-llvm -O1 -o - %s | FileCheck %s

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:950 + assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid register"); + if ((Reg - RISCV::X0) % 2 || Reg == RISCV::X0) +return false; I think this can ju

[PATCH] D104790: [x86] fix mm*_undefined* intrinsics to use arbitrary frozen bit pattern

craig.topper added a comment. In D104790#2836253 , @aqjune wrote: > I couldn't find end-to-end tests for checking assembly generation. > To check whether this is working ok, which tests should I write and how would > it look like? There are tests like t

[PATCH] D104790: [x86] fix mm*_undefined* intrinsics to use arbitrary frozen bit pattern

craig.topper added a comment. We may want to update the code in X86ISelLowering getAVX2GatherNode and getGatherNode to replace freeze+poison on Src with a zero vector. We already do this when the Src is undef. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.l

[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

craig.topper created this revision. craig.topper added reviewers: frasercrmck, rogfer01, kito-cheng, khchen, arcbbb, HsiangKai, evandro. Herald added subscribers: StephenFan, vkmr, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, M

[PATCH] D104854: Introduce intrinsic llvm.isnan

craig.topper added a comment. Doesn't gcc also fold isnan to false under fast math? If we diverge here that means your code would only work correctly with clang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104854/new/ https://reviews.llvm.org/D1

[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

craig.topper updated this revision to Diff 354297. craig.topper added a comment. Add constant argument range checking to SemaChecking Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104822/new/ https://reviews.llvm.org/D104822 Files: clang/include

[PATCH] D107139: [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:108 case 'v': -R = std::string("v"); +R = std::string("@2") + std::string(Constraint, 2); Constraint += 1; I believe most targets use `std::string("^") + std::string

[PATCH] D107139: [RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107139/new/ https://reviews.llvm.org/D107139 ___

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:179 const std::vector &IntrinsicTypes, - StringRef RequiredExtension, unsigned NF); + const std::vector RequiredExtensions, unsigned NF); ~RVVIntr

[PATCH] D106738: [RISCV] Use getNaturalPointeeTypeAlignment to get alignment for stores created for vector builtins.

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106738/new/ https://reviews.llvm.org/D106738 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D107420: [sema] Disallow __builtin_mul_overflow under special condition.

craig.topper added a comment. I put up a patch for a simple fix for this in the backend. https://reviews.llvm.org/D107581 The generated code is not optimal, but maybe better than frontend workarounds. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/

[PATCH] D107420: [sema] Disallow __builtin_mul_overflow under special condition.

craig.topper added a comment. In D107420#2929039 , @aaron.ballman wrote: > In D107420#2928975 , @craig.topper > wrote: > >> I put up a patch for a simple fix for this in the backend. >> https://reviews.llvm.org

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:4478 + let Predicates = [HasFP16] in { +def VMOVSHZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), +(ins VR128X:$src1, VR128X:$src2), pengfei wrote: > LuoYuank

[PATCH] D106701: [clang] Implement -falign-loops=N (N is a power of 2) for non-LTO

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:4749 + << A->getAsString(Args) << A->getValue(); +else if (Value & Value - 1) + TC.getDriver().Diag(diag::err_drv_alignment_not_power_of_two) gcc 5.4 is throwi

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:599 * SPIR +* X86 Might be worth mentioning that it requires AVX512FP16 here Comment at: clang/lib/CodeGen/TargetInfo.cpp:2817 Current = SSE; +} els

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105263/new/ https://reviews.llvm.org/D105263 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D107843: [X86] Add parentheses around casts in some of the X86 intrinsic headers.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel, pengfei. craig.topper requested review of this revision. Herald added a project: clang. This covers the SSE and AVX/AVX2 headers. AVX512 has a lot more macros due to rounding mode. Fixes part of PR51324. Reposito

[PATCH] D107843: [X86] Add parentheses around casts in some of the X86 intrinsic headers.

craig.topper updated this revision to Diff 365880. craig.topper added a comment. Fix two functions I missed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107843/new/ https://reviews.llvm.org/D107843 Files: clang/lib/Headers/__wmmintrin_aes.h

[PATCH] D107946: [X86] Reverse *_set_ph and *_setr_ph 's set order.

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:92 #define _mm512_setr_ph(__h1, __h2, __h3, __h4, __h5, __h6, __h7, __h8, __h9, \ __h10, __h11, __h12, __h13, __h14, __h15, __h16, __h17, \ Can we

[PATCH] D106738: [RISCV] Use getNaturalPointeeTypeAlignment to get alignment for stores created for vector builtins.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG6171f84942ce: [RISCV] Use getNaturalPointeeTypeAlignment to get alignment for stores created… (authored by craig.topper). Repository: rG LLVM Gith

[PATCH] D107843: [X86] Add parentheses around casts in some of the X86 intrinsic headers.

craig.topper updated this revision to Diff 366071. craig.topper added a comment. Add test case to the bottom of sse41-builtins.c Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107843/new/ https://reviews.llvm.org/D107843 Files: clang/lib/Headers/

[PATCH] D105265: [X86] AVX512FP16 instructions enabling 3/6

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:953 +#define _mm512_cvt_roundpd_ph(A, R) \ + (__m128h) __builtin_ia32_vcvtpd2ph512_mask( \ + (__v8df)(A), (__v8

[PATCH] D107843: [X86] Add parentheses around casts in some of the X86 intrinsic headers.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4190d99dfcab: [X86] Add parentheses around casts in some of the X86 intrinsic headers. (authored by craig.topper). Repository: rG LLVM Github Mono

[PATCH] D105264: [X86] AVX512FP16 instructions enabling 2/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3197 + else if (PatchedName.endswith("sh")) +PatchedName = IsVCMP ? "vcmpsh" : "cmpsh"; + else if (PatchedName.endswith("ph")) pengfei wrote: > LuoYua

[PATCH] D105265: [X86] AVX512FP16 instructions enabling 3/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:1955 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32f16, Custom); + setOperationAction(ISD::SINT_TO_FP, MVT::v32i16, Legal); + setOperationAction(ISD::STR

[PATCH] D105265: [X86] AVX512FP16 instructions enabling 3/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:31087 +// Now widen to 128 bits. +unsigned NumConcats = 128 / TmpVT.getSizeInBits(); +MVT ConcatVT = MVT::getVectorVT(EleVT.getSimpleVT(), 8 * NumConcats);

[PATCH] D108151: [NFC][clang] Use X86 Features declaration from X86TargetParser

craig.topper added a comment. The order in X86Parser.def is determined by how bits are allocated in to feature vector in libgcc. They're not in any priority order that I know of. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108151/new/ https://re

[PATCH] D105267: [X86] AVX512FP16 instructions enabling 4/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:1920 + setOperationAction(ISD::STRICT_FTRUNC, VT, Legal); + setOperationAction(ISD::FRINT, VT, Legal); + setOperationAction(ISD::STRICT_FRINT, VT, Legal)

[PATCH] D108151: [NFC][clang] Use X86 Features declaration from X86TargetParser

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1061 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { - enum class FeatPriority { -#define FEATURE(FEAT) FEAT, -#include "clang/Basic/X86Target.def" + // Check that priorites

[PATCH] D108151: [NFC][clang] Use X86 Features declaration from X86TargetParser

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:1071 +assert(llvm::is_contained(Priorities, Priority) && + "Priorites don't form consequtive range!"); + } erichkeane wrote: > If all you care about is whether they are

[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsX86.def:2014 + +TARGET_BUILTIN(__builtin_ia32_vfmaddsh3_mask, "V8xV8xV8xV8xUcIi", "ncV:128:", "avx512fp16") +TARGET_BUILTIN(__builtin_ia32_vfmaddsh3_maskz, "V8xV8xV8xV8xUcIi", "ncV:128:", "avx512f

[PATCH] D108412: [WebAssembly] Add SIMD intrinsics using unsigned integers

craig.topper added a comment. Did you read this twitter thread too or just coincidence? https://twitter.com/rygorous/status/1428207170403725316?s=20 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108412/new/ https://reviews.llvm.org/D108412 __

[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

This revision was automatically updated to reflect the committed changes. Closed by commit rGf225367305c8: [RISCV] Add vget/vset intrinsics for inserting and extracting between different… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://review

[PATCH] D104854: Introduce intrinsic llvm.isnan

craig.topper added inline comments. Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:662 + EVT NewResultVT = TLI.getTypeToTransformTo(*DAG.getContext(), ResultVT); + return DAG.getNode(N->getOpcode(), DL, NewResultVT, N->getOperand(0)); +} Don

[PATCH] D104854: Introduce intrinsic llvm.isnan

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:22039 + // Move FPSW to AX. + SDValue FPSW = DAG.getCopyToReg(DAG.getEntryNode(), DL, X86::FPSW, Test, + SDValue()); The code you copied thi

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/Builtins.def:27 // i -> int -// h -> half +// h -> half (__fp16) +// x -> half (_Float16) This also includes OpenCL half Comment at: clang/test/CodeGen/RISCV/rvv-int

[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1148 +if (HasPolicy) { + ProtoMaskSeq.push_back("z"); +} khchen wrote: > maybe the policy argument should be a constant value ("Kz")? Agreed. Co

[PATCH] D104766: [X86] Zero some outputs of Keylocker intrinsics in error case

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14834 +BasicBlock *NoError = createBasicBlock(StrNoErr, this->CurFn); +BasicBlock *Error = createBasicBlock(StrErr, this->CurFn); Sorry I'm late here. Instead of having 3 se

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:51 + +static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_undefined_ph() { + return (__m256h)__builtin_ia32_undef256(); I think this should be `_mm256_undefined_ph(void)`

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to to RISCVArchStringParser.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.h:29 std::string ABI, CPU; - bool HasM = false; - bool HasA = false; - bool HasF = false; - bool HasD = false; - bool HasC = false; - bool HasB = false; - bool HasV = false; - bool HasZba = f

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to to RISCVArchStringParser.

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:644 + "invalid extension prefix '%s'", + Ext.str().c_str()); +} craig.topper wrote: > does createStringError really r

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