[PATCH] D79910: [x86][seses] Add clang flag; Use lvi-cfi with seses

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/X86.cpp:200 +if (!Args.hasArg(options::OPT_mno_lvi_cfi)) { + Features.push_back("+lvi-cfi"); + LVIOpt = options::OPT_mlvi_cfi; sconstab wrote: > zbrid wrote: > > sconst

[PATCH] D82731: [X86] Move frontend CPU feature initialization to a look up table based implementation.

craig.topper added a comment. @RKSimon do you mind taking a look at this too? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82731/new/ https://reviews.llvm.org/D82731 ___ cfe-commits mailing list cfe-c

[PATCH] D82562: Implement AVX ABI Warning/error

craig.topper added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:2497 + bool IsArgument) { + if (!CallerMap.lookup(Feature) && !CalleeMap.lookup(Feature)) +return Diag.Report(CallLoc, diag::warn_avx_calling_convention)

[PATCH] D82731: [X86] Move frontend CPU feature initialization to a look up table based implementation.

This revision was automatically updated to reflect the committed changes. Closed by commit rG3537939cda86: [X86] Move frontend CPU feature initialization to a look up table based… (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D82731?vs=274161&id=274586#toc Repos

[PATCH] D82562: Implement AVX ABI Warning/error

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM other than that one minor. Comment at: clang/lib/CodeGen/TargetInfo.cpp:2515 + SourceLocation CallLoc, + ll

[PATCH] D78443: [Local] Update getOrEnforceKnownAlignment/getKnownAlignment to use Align/MaybeAlign.

craig.topper updated this revision to Diff 258859. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Fix for clang usage. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78443/new/ https://reviews.ll

[PATCH] D78443: [Local] Update getOrEnforceKnownAlignment/getKnownAlignment to use Align/MaybeAlign.

craig.topper updated this revision to Diff 258876. craig.topper added a comment. Use getAsAlign Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78443/new/ https://reviews.llvm.org/D78443 Files: clang/lib/CodeGen/CGCall.cpp llvm/include/llvm/Tran

[PATCH] D78443: [Local] Update getOrEnforceKnownAlignment/getKnownAlignment to use Align/MaybeAlign.

This revision was automatically updated to reflect the committed changes. Closed by commit rG68b2e507e4fd: [Local] Update getOrEnforceKnownAlignment/getKnownAlignment to use… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D7

[PATCH] D78785: Fix x86/x86_64 calling convention for _ExtInt

craig.topper added a comment. I think you're missing a check for ExtInt in X86_64ABIInfo::getIndirectReturnResult Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78785/new/ https://reviews.llvm.org/D78785 ___ cfe-comm

[PATCH] D62368: Add support for Hygon Dhyana processor

craig.topper added inline comments. Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85 + (Ecx == signature_HYGON_ecx); + if (!IsIntel && !IsAMD && !IsHygon) return false; What's the rationale for the vendor check here anyway? Why isn

[PATCH] D78874: [clang] Add vendor identity for Hygon Dhyana processor

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78874/new/ https://reviews.llvm.org/D78874 ___

[PATCH] D78882: [IR] Replace all uses of CallBase::getCalledValue() with getCalledOperand().

craig.topper created this revision. craig.topper added a reviewer: dblaikie. Herald added subscribers: lldb-commits, cfe-commits, Kayjukh, frgossen, grosul1, dantrushin, Joonsoo, kerbowa, liufengdb, lucyrfox, mgester, arpith-jacob, csigg, nicolasvasilache, antiagainst, shauheen, jpienaar, rriddl

[PATCH] D62368: Add support for Hygon Dhyana processor

craig.topper added inline comments. Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85 + (Ecx == signature_HYGON_ecx); + if (!IsIntel && !IsAMD && !IsHygon) return false; fanjinke wrote: > craig.topper wrote: > > What's the rationale

[PATCH] D78882: [IR] Replace all uses of CallBase::getCalledValue() with getCalledOperand().

This revision was automatically updated to reflect the committed changes. Closed by commit rGa58b62b4a2b9: [IR] Replace all uses of CallBase::getCalledValue() with getCalledOperand(). (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D75936: Add a Pass to X86 that builds a Condensed CFG for Load Value Injection (LVI) Gadgets [4/6]

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp:322 + DenseSet> GadgetEdgeSet; + auto AnalyzeUse = [&](NodeAddr Use, MachineInstr *MI) { +assert(!(Use.Addr->getFlags() & NodeAttrs::PhiRef)); mattdr

[PATCH] D78785: Fix x86/x86_64 calling convention for _ExtInt

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78785/new/ https://reviews.llvm.org/D78785 ___ cfe-commits mailing list c

[PATCH] D79194: Add header guards for header files that should not be included on the PS4 platform

craig.topper added inline comments. Comment at: clang/test/Headers/x86intrin-2.c:3 +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fsyntax-only -ffreestanding -Wcast-qual %s -verify +// RUN: %clang_cc1 -triple i386-unknown-unknown -fsyntax-only -ffreestanding -flax-vector-c

[PATCH] D79194: Add header guards for header files that should not be included on the PS4 platform

craig.topper accepted this revision. craig.topper added inline comments. This revision is now accepted and ready to land. Comment at: clang/test/Headers/x86intrin-2.c:3 +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fsyntax-only -ffreestanding -Wcast-qual %s -verify +// RUN

[PATCH] D78874: [clang] Add vendor identity for Hygon Dhyana processor

This revision was automatically updated to reflect the committed changes. Closed by commit rGaf28e02e74fb: [clang] Add vendor identity for Hygon Dhyana processor to cpuid.h (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D788

[PATCH] D83273: [X86] Remove the feature dependency handling in X86TargetInfo::setFeatureEnabledImpl to a table based lookup in X86TargetParser.cpp

craig.topper added a comment. It's a pretty nasty revert in our downstream tree where we have prototyped future ISAs. So I'd like a little time to take a look. @nickdesaulniers what cpu and fetaures are on your command lines. getImpliedDisabledFeatures should only be called if some feature is e

[PATCH] D85384: [X86] Add basic support for -mtune command line option in clang

craig.topper created this revision. craig.topper added reviewers: echristo, RKSimon, spatel, efriedma. Herald added a subscriber: dang. craig.topper requested review of this revision. Building on the backend support from D85165 . This parses the command line optio

[PATCH] D85385: [X86][FPEnv] Teach X86 mask compare intrinsics to respect strict FP semantics.

craig.topper added inline comments. Comment at: clang/test/CodeGen/avx512f-builtins-constrained-cmp.c:793 // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_true_us - // CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 3

[PATCH] D85385: [X86][FPEnv] Teach X86 mask compare intrinsics to respect strict FP semantics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D85385/new/ https://reviews.llvm.org/D85385 _

[PATCH] D83360: [InstSimplify] Remove select ?, undef, X -> X and select ?, X, undef -> X

craig.topper added a comment. In D83360#2210630 , @nikic wrote: > D85684 has landed, so we can try reapplying > this change. I've put up D85765 with this patch and the follow ups re-ena

[PATCH] D83273: [X86] Remove the feature dependency handling in X86TargetInfo::setFeatureEnabledImpl to a table based lookup in X86TargetParser.cpp

craig.topper added a comment. In D83273#2195033 , @nickdesaulniers wrote: > In D83273#2194869 , @echristo wrote: > >> That said, it's a 10% compile time regression for compiling something like >> the linux kernel

[PATCH] D85806: [WebAssembly] Don't depend on the flags set by handleTargetFeatures in initFeatureMap.

craig.topper created this revision. craig.topper added a reviewer: tlively. Herald added subscribers: jfb, sunfish, jgravelle-google, sbc100, dschuff. Herald added a project: clang. craig.topper requested review of this revision. Herald added a subscriber: aheejin. Properly set "simd128" in the fe

[PATCH] D85807: [Target] Cache the command line derived feature map in TargetOptions.

craig.topper created this revision. craig.topper added reviewers: echristo, erichkeane, nickdesaulniers. Herald added a project: clang. craig.topper requested review of this revision. We can use this to remove some calls to initFeatureMap from Sema and CodeGen when a function doesn't have a target

[PATCH] D85543: Limit Max Vector alignment on COFF targets to 8192

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D85543/new/ https://reviews.llvm.org/D85543 ___ cfe-commits mailing list cfe

[PATCH] D85806: [WebAssembly] Don't depend on the flags set by handleTargetFeatures in initFeatureMap.

This revision was automatically updated to reflect the committed changes. Closed by commit rG2b8ad6b60408: [WebAssembly] Don't depend on the flags set by handleTargetFeatures in… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.or

[PATCH] D85807: [Target] Cache the command line derived feature map in TargetOptions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG5c1fe4e20f88: [Target] Cache the command line derived feature map in TargetOptions. (authored by craig.topper). Repository: rG LLVM Github Monorep

[PATCH] D85384: [X86] Add basic support for -mtune command line option in clang

craig.topper added a comment. Ping CHANGES SINCE LAST ACTION https://reviews.llvm.org/D85384/new/ https://reviews.llvm.org/D85384 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D85384: [X86] Add basic support for -mtune command line option in clang

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CodeGenModule.cpp:1752 StringRef TargetCPU = getTarget().getTargetOpts().CPU; + StringRef TuneCPU = getTarget().getTargetOpts().TuneCPU; std::vector Features; erichkeane wrote: > Does this l

[PATCH] D85384: [X86] Add basic support for -mtune command line option in clang

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CodeGenModule.cpp:1752 StringRef TargetCPU = getTarget().getTargetOpts().CPU; + StringRef TuneCPU = getTarget().getTargetOpts().TuneCPU; std::vector Features; erichkeane wrote: > craig.toppe

[PATCH] D79448: [X86] Allow Yz inline assembly constraint to choose ymm0 or zmm0 when avx/avx512 are enabled and type is 256 or 512 bits

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel, rnk, echristo. Herald added a subscriber: hiraditya. Herald added a project: LLVM. gcc supports selecting ymm0/zmm0 for the Yz constraint when used with 256 or 512 bit vector types. Fixes PR45806 https://reviews

[PATCH] D79448: [X86] Allow Yz inline assembly constraint to choose ymm0 or zmm0 when avx/avx512 are enabled and type is 256 or 512 bits

This revision was automatically updated to reflect the committed changes. Closed by commit rG0fac1c191281: [X86] Allow Yz inline assembly constraint to choose ymm0 or zmm0 when… (authored by craig.topper). Herald added a project: clang. Changed prior to commit: https://reviews.llvm.org/D79448?v

[PATCH] D79472: [X86] Remove support some inline assembly constraints that are no longer supported by gcc.

craig.topper created this revision. craig.topper added reviewers: rnk, echristo, RKSimon, spatel. Herald added subscribers: cfe-commits, hiraditya. Herald added projects: clang, LLVM. This removes the Y0, Yi, Yt, Y2, Ym, and Y constraints. Repository: rG LLVM Github Monorepo https://reviews.l

[PATCH] D62368: Add vendor identity check for Hygon Dhyana processor in Scudo

craig.topper added a comment. I noticed when I pulled this morning that this seems to have been pushed as a branch to the repo From https://github.com/llvm/llvm-project eb7d32e..63a4fdd master -> origin/master - [new branch] arcpatch-D62368 -> origin/arcpatch-D62368 Repository:

[PATCH] D62368: Add vendor identity check for Hygon Dhyana processor in Scudo

craig.topper added a comment. In D62368#2029870 , @cryptoad wrote: > In D62368#2029752 , @craig.topper > wrote: > > > I noticed when I pulled this morning that this seems to have been pushed as > > a branch to the

[PATCH] D75936: Add a Pass to X86 that builds a Condensed CFG for Load Value Injection (LVI) Gadgets [4/6]

This revision was automatically updated to reflect the committed changes. Closed by commit rGe97a3e5d9d42: [X86] Add a Pass that builds a Condensed CFG for Load Value Injection (LVI)… (authored by sconstab, committed by craig.topper). Changed prior to commit: https://reviews.llvm.org/D75936?vs

[PATCH] D75936: Add a Pass to X86 that builds a Condensed CFG for Load Value Injection (LVI) Gadgets [4/6]

craig.topper added a comment. In D75936#2032078 , @sconstab wrote: > In D75936#2032027 , @nikic wrote: > > > This change causes a 0.8% compile-time regression for unoptimized builds > >

[PATCH] D75936: Add a Pass to X86 that builds a Condensed CFG for Load Value Injection (LVI) Gadgets [4/6]

craig.topper added inline comments. Comment at: llvm/test/CodeGen/X86/O3-pipeline.ll:147 +; CHECK-NEXT: X86 Load Value Injection (LVI) Load Hardening ; CHECK-NEXT: Fixup Statepoint Caller Saved ; CHECK-NEXT: PostRA Machine Sink I'm curious wha

[PATCH] D79804: [x86] prevent 64b operands to "r" constrained inline asm for -m32

craig.topper added a comment. I'm trying to catch up here. It looks like gcc has only started complaining about this from maybe version 7 on? And only as a warning? The LLVM X86 backend used a 32-bit register for 'r' or 'R' on -m32 for 64-bit values. But the backend would fail for 'q' or 'Q' if

[PATCH] D79910: [x86][seses] Add clang flag; Use lvi-cfi with seses

craig.topper added inline comments. Comment at: clang/docs/ClangCommandLineReference.rst:2632 +.. option:: -mseses, -mno-seses + This file is in alphabetical order and is normally generated by a running clang-tblgen. See comment at the top of the file. Repos

[PATCH] D79743: [clang][asm goto][slh] Warn if asm goto + SLH

craig.topper added a comment. In D79743#2035575 , @mattdr wrote: > Not sure we want to move this into the Parser -- SLH is a property of code > generation, and I think it's possible (through LTO?) to mismatch the flags > between parse and codegen. This

[PATCH] D79322: [FEnv] Small fixes to implementation of flt.rounds

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/flt-rounds.ll:23 +; RV64I-NEXT:sd ra, 8(sp) +; RV64I-NEXT:call __flt_rounds +; RV64I-NEXT:ld ra, 8(sp) sepavloff wrote: > lenary wrote: > > I'm interested to understand how this f

[PATCH] D40224: [X86] Control-Flow Enforcement Technology - Shadow Stack and Indirect Branch Tracking support (Clang side)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D40224 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm

[PATCH] D40819: Implement Attribute Target MultiVersioning (Improved edition!)

craig.topper added inline comments. Comment at: include/clang/Basic/X86Target.def:148 /// Cannonlake client microarchitecture based processors. PROC(Cannonlake, "cannonlake", PROC_64_BIT) Cannonlake can prioritize off of VBMI or IFMA. Comme

[PATCH] D40478: Added Instrument Control Flow Flag

craig.topper added a comment. -mibt isn't required for inline assembly, There's no AssemblePredicate defined with HasIBT in X86InstrInfo.td. We don't normally do fine grained assembler feature enabling so I believe we should always support it. Repository: rL LLVM https://reviews.llvm.org/D4

[PATCH] D40478: Added Instrument Control Flow Flag

craig.topper added inline comments. Comment at: include/clang/Driver/Options.td:1035 HelpText<"Instrument function entry only, after inlining, without arguments to the instrumentation call">; - +def finstrument_control_flow : Flag<["-"], "finstrument-control-flow">, + Group,

[PATCH] D41168: [X86][avx512] Lowering X86 avx512 sqrt intrinsics to IR

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:8145 + case X86::BI__builtin_ia32_sqrtpd512_mask_nr: + case X86::BI__builtin_ia32_sqrtps512_mask_nr: { +Function *F = CGM.getIntrinsic(Intrinsic::sqrt, Ops[0]->getType()); I would sug

[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:19 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, - HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, - HasStd

[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:4359 -return Diag(TheCall->getCallee()->getBeginLoc(), -diag::err_32_bit_builtin_64_bit_tgt); - luismarques wrote: > That tablegen def is still being used for X86.

[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

This revision was automatically updated to reflect the committed changes. Closed by commit rG7440e2274fbd: [RISCV] Add '32bit' feature to rv32 only builtins. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D132192/new/ https

[PATCH] D133444: [RISCV] Update error message to not call 'RV32' and 'RV64' an extension.

craig.topper created this revision. craig.topper added reviewers: reames, luismarques, asb, kito-cheng. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinM

[PATCH] D133444: [RISCV] Update error message to not call 'RV32' and 'RV64' an extension.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG6106a6d7fe48: [RISCV] Update error message to not call 'RV32' and 'RV64' an extension. (authored by craig.topper). Repository: rG LLVM Github Mono

[PATCH] D133634: [clang] Allow vector of BitInt

craig.topper added subscribers: efriedma, craig.topper. craig.topper added a comment. I'm a little nervous about non-byte-sized non-power of 2 elements. The memory layout handling gets a little weird in the backend. @efriedma what do you think? Repository: rG LLVM Github Monorepo CHANGES SIN

[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2509 // Attempt to parse token as a register. - if (parseRegister(Operands, true).isSuccess()) + if (parseRegister(Operands, true).isSuccess()) { +// Parse memory base regi

[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 ___

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 ___ cfe-commits mailing list cfe-commits@l

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:229 +collectNonISAExtFeature(const std::vector &FeaturesVec, int XLen) { + auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride"); + auto FeatureNeedOveride = std::vector(FeaturesVec.

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151730/new/ https://reviews.llvm.org/D151730 ___

[PATCH] D155688: [PATCH] [llvm] [InstCombine] Canonicalise ADD+GEP

craig.topper added a comment. After this patch, I'm seeing a lot of `invariant.gep` created by LICM. For example, in `LBM_performStreamCollide` in 470.lbm there are 65 of them. On RISC-V, these all get created in registers outside the loop and get spilled. Is ARM seeing anything like this or do

[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

craig.topper added a comment. Need to update the table here https://clang.llvm.org/docs/LanguageExtensions.html#vector-operations to include RVV Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158259/new/ https://reviews.llvm.org/D158259 _

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:229 +resolveTargetAttrOverride(const std::vector &FeaturesVec) { + if (!llvm::is_contained(FeaturesVec, "__RISCV_TargetAttrNeedOverride")) +return FeaturesVec; Can we use somet

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:370 + std::vector &Features) { + Features.push_back("__RISCV_TargetAttrNeedOverride"); + auto RII = llvm::RISCVISAInfo::parseArchString( Why do we

[PATCH] D128612: RISC-V big-endian support implementation

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.h:111 SizeType = UnsignedInt; -resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128"); } Instead of creating new classes, could we have a branch on the Arch or isLittleEndian por

[PATCH] D128613: Add explicit index type for llvm.vector.extract

craig.topper added a comment. Can we just add the missing zext to the RISC-V vget implementation? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128613/new/ https://reviews.llvm.org/D128613 ___ cfe-commit

[PATCH] D128624: [RISCV] Zero immediate for vget/vset builtins to match vector.insert/extract intrinsics.

craig.topper created this revision. craig.topper added reviewers: liaolucy, kito-cheng, fakepaper56, frasercrmck, rogfer01. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o

[PATCH] D128624: [RISCV] Zero extend immediate for vget/vset builtins to match vector.insert/extract intrinsics.

This revision was automatically updated to reflect the committed changes. Closed by commit rG17a36c7c40e9: [RISCV] Zero extend immediate for vget/vset builtins to match vector. (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D128624?vs=440112&id=440459#toc Reposit

[PATCH] D128604: [RISCV] Support Zbpbo extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:21 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit") -TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb") +TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/TokenKinds.def:911 +// Annotation for the riscv pragma directives - #pragma clang riscv intrinsic .. +PRAGMA_ANNOTATION(pragma_riscv) Why only 2 periods at the end. Should be 3 like on l

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

craig.topper added inline comments. Comment at: clang/test/Sema/riscv-bad-intrnisic-pragma.c:1 +// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -emit-llvm -o - \ +// RUN:2>&1 | FileCheck %s this test file name is misspelled

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:17 #include "llvm/ADT/StringRef.h" +#include "llvm/Support/raw_ostream.h" #include Do we need the header or is a forward declaration enough? Repository: rG L

[PATCH] D122564: [RISCV] [NFC] add some tests for overloaded intrinsics of FP16

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122564/new/ https://reviews.llvm.org/D122564 ___

[PATCH] D122713: [RISCV] [NFC] Add tests for vector load/store overloaded intrinsics of FP16

craig.topper added a comment. These tests files are already too long and have been timing out in phabricator. @4vtomat has a patch D122370 to split them up. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122713/ne

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

craig.topper added a comment. In D130311#3691029 , @reames wrote: > I'm not fluent on strict FP, so let me summarize my understanding. This is > mostly so you can easily correct me if one my assumptions is wrong. > > - Under strict FP, clang will emit c

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

craig.topper added a comment. In D126745#3691528 , @khchen wrote: > In D126745#3678776 , @nlopes wrote: > >> While at it, could you switch those UndefValue with PoisonValue if possible? >> Thank you! > > I'm not

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:286 + // StrictFP support for vectors is incomplete. + if (ISAInfo->hasExtension("zve32x")) +HasStrictFP = false; reames wrote: > craig.topper wrote: > > reames wrote: > > > a

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:286 + // StrictFP support for vectors is incomplete. + if (ISAInfo->hasExtension("zve32x")) +HasStrictFP = false; reames wrote: > craig.topper wrote: > > reames wrote: > > > c

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

craig.topper updated this revision to Diff 449150. craig.topper added a comment. Add hasVInstructions to RISCVISAInfo Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D130311/new/ https://reviews.llvm.org/D130311 Files: clang/lib/Basic/Targets/RISCV

[PATCH] D131134: [X86] Report error if the amx enabled on the non-64-bits target

craig.topper added a comment. How does this interact with `-march=native -m32`. Won't that pick up the amx flag from CPUID? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131134/new/ https://reviews.llvm.org/D131134 ___

[PATCH] D131134: [X86] Report error if the amx enabled on the non-64-bits target

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/X86.cpp:133 +for (auto &F : HostFeatures) { + if (F.first().startswith("amx") && F.second && !Is64bitTarget) +D.Diag(diag::err_feature_unsupported_on_target)

[PATCH] D131134: [X86] Report error if the amx enabled on the non-64-bits target

craig.topper added a comment. What problem are we trying to solve here? CPUID reports AMX as supported even in 32-bit mode. Why can't the user pass it to the compiler? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131134/new/ https://reviews.llvm.

[PATCH] D131635: [RISCV] Remove sifive-7-rv32/rv64 CPU names.

craig.topper created this revision. craig.topper added reviewers: kito-cheng, arcbbb, asb, luismarques. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinM

[PATCH] D131635: [RISCV] Remove sifive-7-rv32/rv64 CPU names.

craig.topper abandoned this revision. craig.topper added a comment. I'm going to rethink this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131635/new/ https://reviews.llvm.org/D131635 ___ cfe-commits m

[PATCH] D131134: [X86] Report error if the amx enabled on the non-64-bits target

craig.topper added a comment. Yes AMX is only supported in 64-bit mode but I doubt CPUID checks which mode the program is running in. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131134/new/ https://reviews.llvm.org/D131134 _

[PATCH] D106044: [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c:1182 +void test_vsm_v_b1(uint8_t *base, vbool1_t value, size_t vl) { return vse1(base, value, vl); } Was the call supposed to be renamed or just the test

[PATCH] D103796: [Clang][RISCV] Implement vlsseg.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:955 + clang::CharUnits Align = + CGM.getNaturalTypeAlignment(getContext().getSizeType()); + llvm::Value *V; I don't think this alignment is correct. A vin

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:512 +Str += "_Float16"; + assert((ElementBitwidth == 16 || ElementBitwidth == 32 || + ElementBitwidth == 64) && Can we use an else and an llvm_unreach

[PATCH] D106210: [MS] Preserve base register %esi around movs[bwl]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106210/new/ https://reviews.llvm.org/D106210 ___

[PATCH] D106210: [MS] Preserve base register %esi around movs[bwl]

craig.topper added a comment. In D106210#2885538 , @namazso wrote: > I don't have commit access, could someone commit this for me? Thanks in > advance. I can commit it. How would you like your name to appear in the author line of the git log? Reposit

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105001/new/ https://reviews.llvm.org/D105001 ___

[PATCH] D106255: [Clang][RISCV] Correct the alignment of stores generated by vlseg/vlsegff.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106255/new/ https://reviews.llvm.org/D106255 ___

[PATCH] D106340: [Clang][RISCV] Add half-precision FP for vle16/vse16.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106340/new/ https://reviews.llvm.org/D106340 ___

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:159 + // Enable CRC32 if SSE4.2 is enabled. + // NOTE: In conformance with GCC behavior, CRC32 is still available even if + // it's explicitly disabled. This doesn't seem to be tru

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:159 + // Enable CRC32 if SSE4.2 is enabled. + // NOTE: In conformance with GCC behavior, CRC32 is still available even if + // it's explicitly disabled. hjl.tools wrote: > tianqing

[PATCH] D103872: [Clang][RISCV] Implement vssseg.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103872/new/ https://reviews.llvm.org/D103872 ___

[PATCH] D103796: [Clang][RISCV] Implement vlsseg.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103796/new/ https://reviews.llvm.org/D103796 ___

[PATCH] D103809: [Clang][RISCV] Implement vloxseg and vluxseg.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103809/new/ https://reviews.llvm.org/D103809 ___

[PATCH] D103871: [Clang][RISCV] Implement vsseg.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103871/new/ https://reviews.llvm.org/D103871 ___

<    1   2   3   4   5   6   7   8   9   10   >