craig.topper added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:19 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, - HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, - HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, - HasVInstructions]; + HasStdExtZcb, HasStdExtZknd, HasStdExtZkne, + HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, ---------------- VincentWu wrote: > craig.topper wrote: > > If we put the write Sched information to match the uncompressed forms, is > > this still needed? > Sorry, could you explain what is "uncompressed forms"? and where it is? Every compressed instruction in Zcb has an equivalent instruction with a 32-bit encoding. Both instructions should have the same scheduling information. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131141/new/ https://reviews.llvm.org/D131141 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
