[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper added a comment. @void, @jyknight given that looks like a LLVM issue rather than a clang issue, can we file a bugzilla to track separately from this clang frontend patch? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56571/new/ https://reviews.llvm.org/D56571 _

[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake

craig.topper added a comment. We seem to be missing test cases in test/Driver/x86-target-feature.c to test the command line options work. And test/Preprocessor/x86_target_features.c to make sure -mavx512bf16 enables avx512vl and avx512bw. Also need tests to make sure "-mavx512bf16 -mno-avx512bw

[PATCH] D44387: [x86] Introduce the pconfig/encl[u|s|v] intrinsics

craig.topper added a comment. The main reason that we used inline assembly is due to the fixed register allocation for these instructions. We would have had to write out the register rules in the backend as a special case as seen in the getInstrWFourImplicitOps in https://reviews.llvm.org/D4438

[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:667 if (Name == "avx512bw" && !Enabled) Features["avx512vbmi"] = Features["avx512vbmi2"] = Features["avx512bitalg"] = false; craig.topper wrote: > Need to also disable av

[PATCH] D44387: [x86] Introduce the pconfig/encl[u|s|v] intrinsics

craig.topper added a comment. Your understanding is correct. As far as testing I think the existing testing in the original patches is sufficient. I'm not sure I understand how a target specific intrinsic that only works on x86 in the bitcode is substantially better than inline assembly. Do y

[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60552/new/ https://reviews.llvm.org/D60552 ___ cfe-commits mailing list c

[PATCH] D61472: [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

craig.topper updated this revision to Diff 198220. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61472/new/ https://reviews.llvm.org/D61472

[PATCH] D61472: [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

craig.topper added a comment. Not sure. I'll fix it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61472/new/ https://reviews.llvm.org/D61472 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[PATCH] D61472: [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

craig.topper updated this revision to Diff 198303. craig.topper added a comment. Get rid of clang stuff. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61472/new/ https://reviews.llvm.org/D61472 Files: llvm/lib/Target/X86/X86FixupLEAs.cpp llvm/test/CodeGen/X86/GlobalISel/add-ext.ll

[PATCH] D52392: [X86] For lzcnt/tzcnt intrinsics use cttz/ctlz intrinsics with zero_undef flag set to false.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. Herald added a subscriber: cfe-commits. Previously we used a select and the zero_undef=true intrinsic. In -O2 this pattern will get optimized to zero_undef=false. But in -O0 this optimization won't happen. This re

[PATCH] D52392: [X86] For lzcnt/tzcnt intrinsics use cttz/ctlz intrinsics with zero_undef flag set to false.

craig.topper added a comment. The only other header that uses the existing builtins is arm_acle.h. But ARM returns false in isCLZForZeroUndef. So they should be creating the cttz/ctlz intrinsics with false for the second argument from __builtin_clz/ctz. The sanitizer code in CodeGenFunction::EmitC

[PATCH] D52586: [X86] Add the movbe instruction intrinsics from icc.

craig.topper created this revision. craig.topper added reviewers: spatel, RKSimon. These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we

[PATCH] D52586: [X86] Add the movbe instruction intrinsics from icc.

craig.topper updated this revision to Diff 167416. craig.topper added a comment. Add comment. Fix typo. Add preprocessor define checks to the various CPUs that have MOVBE https://reviews.llvm.org/D52586 Files: lib/Basic/Targets/X86.cpp lib/Headers/immintrin.h test/CodeGen/movbe-builtins.

[PATCH] D52665: [X86] Add more of the icc unaligned load/store to/from 128 bit vector intrinsics

craig.topper created this revision. craig.topper added reviewers: spatel, RKSimon. This patch adds _mm_loadu_si32 _mm_loadu_si16 _mm_storeu_si64 _mm_storeu_si32 _mm_storeu_si16 We already had _mm_load_si64. https://reviews.llvm.org/D52665 Files: lib/Headers/emmintrin.h test/CodeGen/sse2-bu

[PATCH] D52665: [X86] Add more of the icc unaligned load/store to/from 128 bit vector intrinsics

craig.topper added a comment. Looks like the load and store 64 are supported in 32-bit mode in icc https://godbolt.org/z/Wpezeu https://reviews.llvm.org/D52665 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/ma

[PATCH] D52441: [CodeGen] Update min-legal-vector width based on function argument and return types

craig.topper added a comment. Herald added a subscriber: arphaman. Ping https://reviews.llvm.org/D52441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D52835: [Diagnostics] Check integer to floating point number implicit conversions

craig.topper added inline comments. Comment at: lib/Sema/SemaChecking.cpp:110 +/// are usually useless +static unsigned AdjustPrecision(unsigned precision) { + return (precision * 59 + 195) / 196; scanon wrote: > erichkeane wrote: > > Hmm I don't terribly un

[PATCH] D52852: [WebAssembly] __builtin_wasm_extract_lane_* builtins

craig.topper added inline comments. Comment at: include/clang/Basic/BuiltinsWebAssembly.def:46 +BUILTIN(__builtin_wasm_extract_lane_s_i16x8, "iV8sIi", "ncV:128:") +BUILTIN(__builtin_wasm_extract_lane_u_i16x8, "iV8sIi", "ncV:128:") +BUILTIN(__builtin_wasm_extract_lane_i32x4, "iV4i

[PATCH] D52856: [WebAssembly] __builtin_wasm_replace_lane_* builtins

craig.topper added inline comments. Comment at: include/clang/Basic/BuiltinsWebAssembly.def:55 +BUILTIN(__builtin_wasm_replace_lane_i32x4, "V4iV4iIii", "ncV:128:") +BUILTIN(__builtin_wasm_replace_lane_i64x2, "V2WiV2WiIiWi", "ncV:128:") +BUILTIN(__builtin_wasm_replace_lane_f32x4,

[PATCH] D52858: [WebAssembly] saturating arithmetic builtins

craig.topper added inline comments. Comment at: include/clang/Basic/BuiltinsWebAssembly.def:59 +BUILTIN(__builtin_wasm_add_saturate_s_i8x16, "V16cV16cV16c", "ncV:128:") +BUILTIN(__builtin_wasm_add_saturate_u_i8x16, "V16cV16cV16c", "ncV:128:") Don't copy the "V:

[PATCH] D52856: [WebAssembly] __builtin_wasm_replace_lane_* builtins

craig.topper added inline comments. Comment at: include/clang/Basic/BuiltinsWebAssembly.def:55 +BUILTIN(__builtin_wasm_replace_lane_i32x4, "V4iV4iIii", "ncV:128:") +BUILTIN(__builtin_wasm_replace_lane_i64x2, "V2WiV2WiIiWi", "ncV:128:") +BUILTIN(__builtin_wasm_replace_lane_f32x4,

[PATCH] D57642: [X86] Update clobber list in a test after D57641. Remove filter for 'fpsw' in MS inline asm clobber list generation since the backend now uses 'fpsr'.

craig.topper created this revision. craig.topper added a reviewer: rnk. Herald added subscribers: cfe-commits, eraman. Herald added a project: clang. The backend used to print the x87 FPSW register as 'fpsw', but gcc inline asm uses 'fpsr'. After D57641 , the back

[PATCH] D57642: [X86] Update clobber list in a test after D57641. Remove filter for 'fpsw' in MS inline asm clobber list generation since the backend now uses 'fpsr'.

craig.topper marked an inline comment as done. craig.topper added inline comments. Comment at: test/CodeGen/ms-inline-asm.c:574 // CHECK: fistp dword ptr $0 -// CHECK: "=*m,*m,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, float* %{{.*}}) +// CHECK: "=*m,*m,~{fpsr},~{dirflag},~{fpsr

[PATCH] D57642: [X86] Update clobber list in a test after D57641. Remove filter for 'fpsw' in MS inline asm clobber list generation since the backend now uses 'fpsr'.

craig.topper updated this revision to Diff 185201. craig.topper added a comment. Keep the filter on fpsw, but change the string to fpsr Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57642/new/ https://reviews.llvm.org/D57642 Files: lib/Parse/ParseStmtAsm.cpp

[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper added a subscriber: jyknight. craig.topper added inline comments. Comment at: lib/CodeGen/CGStmt.cpp:2236 +llvm::CallBrInst *Result = +Builder.CreateCallBr(FTy, IA, Fallthrough, Transfer, Args); +UpdateAsmCallInst(cast(*Result), HasSideEffect, ReadOnl

[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper added inline comments. Comment at: lib/AST/Stmt.cpp:628 + DiagOffs = CurPtr-StrStart-1; + return diag::err_asm_invalid_operand_for_goto_labels; +} efriedma wrote: > jyu2 wrote: > > rsmith wrote: > > > jyu2 wrote: > > > > rsm

[PATCH] D57961: [X86] Add explicit alignment to __m128/__m128i/__m128d/etc. to allow matching of MSVC behavior with #pragma pack.

craig.topper created this revision. craig.topper added reviewers: rnk, erichkeane, spatel, RKSimon. Herald added a project: clang. With MSVC, #pragma pack is ignored when there is explicit alignment. This differs from gcc. Clang emulates this difference when compiling for Windows. It appears tha

[PATCH] D57961: [X86] Add explicit alignment to __m128/__m128i/__m128d/etc. to allow matching of MSVC behavior with #pragma pack.

craig.topper updated this revision to Diff 185996. craig.topper added a comment. Forgot to do MMX's __m64 type Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57961/new/ https://reviews.llvm.org/D57961 Files: lib/Headers/avx512bwintrin.h lib/Headers/avx512fint

[PATCH] D57961: [X86] Add explicit alignment to __m128/__m128i/__m128d/etc. to allow matching of MSVC behavior with #pragma pack.

craig.topper added a comment. Thanks for the fix @rnk, I've added some MSVC command lines to some of the other test files too. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57961/new/ https://reviews.llvm.org/D57961 ___

[PATCH] D58344: Enablement for AMD znver2 architecture - skeleton

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58344/new/ https://reviews.llvm.org/D58344 ___ cf

[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch

craig.topper added a comment. I think you uploaded the clang patch into the llvm review? Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/ https://reviews.llvm.org/D58343 ___ cfe-commits mailing list cfe-commi

[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/ https://reviews.llvm.org/D58343 ___ cfe

[PATCH] D37287: [X86] Implement broadcastf32x2 and broadcasti32x2 intrinsics using __builtin_shufflevector instead builtins

craig.topper created this revision. This patch implements the broadcastf32x2/broadcasti32x2 intrinsics using __builtin_shufflevector. https://reviews.llvm.org/D37287 Files: include/clang/Basic/BuiltinsX86.def lib/Headers/avx512dqintrin.h lib/Headers/avx512vldqintrin.h test/CodeGen/avx5

[PATCH] D37287: [X86] Implement broadcastf32x2 and broadcasti32x2 intrinsics using __builtin_shufflevector instead builtins

craig.topper added a comment. Yes I did. With the other bug fixed they all produced the correct instruction. https://reviews.llvm.org/D37287 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-c

[PATCH] D36707: [CodeGen]Refactor CpuSupports/CPUIs Builtin Code Gen to better work with "target" implementation

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:7414 + StringRef FeatureStr = cast(FeatureExpr)->getString(); + return EmitX86CpuSupports({FeatureStr}); +} You shouldn't need curly braces here. ArrayRef has a conversion constructor th

[PATCH] D36707: [CodeGen]Refactor CpuSupports/CPUIs Builtin Code Gen to better work with "target" implementation

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D36707 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D37562: [X86] Lower _mm[256|512]_[mask[z]]_avg_epu[8|16] intrinsics to native llvm IR

craig.topper added a comment. You need to remove the bultins from include/clang/Basic/BuiltinsX86.def too. https://reviews.llvm.org/D37562 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-com

[PATCH] D37668: [X86][intrinsics] lower _mm[256|512]_mask[z]_set1_epi[8|16|32|64] intrinsic to IR

craig.topper added a comment. I think when you uploaded the changes to remove it from BuiltinsX86.def you lost your earlier changes to the header files https://reviews.llvm.org/D37668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://l

[PATCH] D37562: [X86] Lower _mm[256|512]_[mask[z]]_avg_epu[8|16] intrinsics to native llvm IR

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D37562 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D37694: [X86] [PATCH] [intrinsics] Lowering X86 ABS intrinsics to IR. (clang)

craig.topper added a comment. Remove the builtins from BuiltinsX86.def https://reviews.llvm.org/D37694 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D37694: [X86] [PATCH] [intrinsics] Lowering X86 ABS intrinsics to IR. (clang)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. Oops you are correct. Sorry. LGTM https://reviews.llvm.org/D37694 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lis

[PATCH] D37668: [X86][intrinsics] lower _mm[256|512]_mask[z]_set1_epi[8|16|32|64] intrinsic to IR

craig.topper added inline comments. Comment at: include/clang/Basic/BuiltinsX86.def:981 -TARGET_BUILTIN(__builtin_ia32_pbroadcastd512_gpr_mask, "V16iiV16iUs", "", "avx512f") TARGET_BUILTIN(__builtin_ia32_pbroadcastq512_mem_mask, "V8LLiLLiV8LLiUc", "", "avx512f") TARGET_BUILTI

[PATCH] D37892: [X86] Use native shuffle vector for the perm2f128 intrinsics

craig.topper updated this revision to Diff 115427. craig.topper added a comment. Convert the AVX2 integer intrinsic as well. https://reviews.llvm.org/D37892 Files: lib/CodeGen/CGBuiltin.cpp test/CodeGen/avx-builtins.c test/CodeGen/avx2-builtins.c Index: test/CodeGen/avx2-builtins.c

[PATCH] D37668: [X86][intrinsics] lower _mm[256|512]_mask[z]_set1_epi[8|16|32|64] intrinsic to IR

craig.topper added a comment. I'm going to go ahead and remove __builtin_ia32_pbroadcastq512_mem_mask from clang and change _mm512_maskz_set1_epi64 to be disabled in 32-bit mode. I want to nominate this for 5.0.1 because using it in 32-bit mode causes the compile to throw a cannot select error.

[PATCH] D37938: [X86] Remove unnecessary extra encodings from the CPU name enum in clang

craig.topper created this revision. For a lot of older CPUs we have a 1:1 mapping between CPU name and enum name. But many of them are effectively aliases of each other and as a result are always repeated together at every usage This patch removes most of the duplication. It also uses StringSwi

[PATCH] D37941: [X86] Move even more of our CPU to feature mapping switch to use fallthroughs

craig.topper created this revision. This arranges more of the Intel and AMD CPUs into fallthrough positions based on their features. We may be able to merge this new AMD set with the BTVER or BDVER sets but I didn't look that closely. https://reviews.llvm.org/D37941 Files: lib/Basic/Targets

[PATCH] D37668: [X86][intrinsics] lower _mm[256|512]_mask[z]_set1_epi[8|16|32|64] intrinsic to IR

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D37668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D37562: [X86] Lower _mm[256|512]_[mask[z]]_avg_epu[8|16] intrinsics to native llvm IR

craig.topper added a comment. Was the code not using emmintrin.h and instead copied code from it that used the builtins? Repository: rL LLVM https://reviews.llvm.org/D37562 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D62367: [X86] VP2INTERSECT clang

craig.topper added inline comments. Comment at: lib/Headers/avx512vlvp2intersectintrin.h:39 + +/// This instruction writes an even/odd pair of mask registers. The mask +/// register destination indicated in the MODRM.REG field is used to form This doesn't really

[PATCH] D62367: [X86] VP2INTERSECT clang

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62367/new/ https://reviews.llvm.org/D62367 ___ cf

[PATCH] D62282: [X86] Add ENQCMD intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62282/new/ https://reviews.llvm.org/D62282 ___ cfe-commits mailing list c

[PATCH] D62850: [X86] Fix builtins-x86.c test where it wasn't using immediates. NFC

craig.topper added a comment. We support non immediate on these because gcc does. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62850/new/ https://reviews.llvm.org/D62850 ___ cfe-commits mailing list c

[PATCH] D62363: [X86] Enable intrinsics that convert float and bf16 data to each other

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62363/new/ https://reviews.llvm.org/D62363 ___ cfe-commits mailing list c

[PATCH] D62835: [X86] -march=cooperlake (clang)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62835/new/ https://reviews.llvm.org/D62835 ___ cfe-commits mailing list c

[PATCH] D62850: [X86] Fix builtins-x86.c test where it wasn't using immediates. NFC

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62850/new/ https://reviews.llvm.org/D62850 ___ cfe-commits mailing list c

[PATCH] D63018: [X86] Attempt to make the Intel core CPU inheritance a little more readable and maintainable

craig.topper updated this revision to Diff 203597. craig.topper added a comment. Fix mistake in a comment CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63018/new/ https://reviews.llvm.org/D63018 Files: clang/lib/Basic/Targets/X86.cpp Index: clang/lib/Basic/Targets/X86.cpp =

[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper added a comment. There's still something weird in the backend, but things seem to generally work if you pass -fno-integrated-as to clang which the linux kernel does. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56571/new/ https://reviews.llvm.org/D56571 ___

[PATCH] D62363: [X86] Enable intrinsics that convert float and bf16 data to each other

craig.topper accepted this revision. craig.topper added a comment. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62363/new/ https://reviews.llvm.org/D62363 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D59744: Fix i386 ABI "__m64" type bug

craig.topper added a comment. -O0 always inline isn't working because the frontend is emitting a store of vector type to memory then a load of x86_mmx to do the type coercion. The caller does the opposite to coerce back from mmx. This -O0 pipeline isn't capable of getting rid of these redundant

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper created this revision. craig.topper added reviewers: eli.friedman, RKSimon, spatel, rnk. As far as I can tell, gcc passes 256/512 bit vectors __int128 in memory. And passes a vector of 1 _int128 in an xmm register. The backend considers as an illegal type and will scalarize any argu

[PATCH] D64676: Support __seg_fs and __seg_gs on x86

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64676/new/ https://reviews.llvm.org/D64676 ___

[PATCH] D63638: [clang][NewPM] Add new pass manager RUN lines to avx512f-builtins.c

craig.topper added a comment. In D63638#1581973 , @chandlerc wrote: > Just to make sure we're on the same page (and sorry I didn't jump in > sooner)... > > With the old PM, *anything* that is `always_inline` *gets* `instsimplify` run > on it, even at -O0

[PATCH] D65110: [NewPM] Run avx*-builtins.c tests under the new pass manager only

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65110/new/ https://reviews.llvm.org/D65110 ___

[PATCH] D65978: [clang] Fixed x86 cpuid NSC signature

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65978/new/ https://reviews.llvm.org/D65978 ___ cf

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper updated this revision to Diff 214539. craig.topper edited the summary of this revision. craig.topper added a comment. Herald added a project: clang. Add test cases. Change the type to vXi64 instead of vXf64. Add abi compatibility flag. Restrict to linux and freebsd. Repository: r

[PATCH] D64672: [X86] Prevent passing vectors of __int128 as in llvm IR

craig.topper updated this revision to Diff 214540. craig.topper added a comment. More test check lines. Test the compatibility flag. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64672/new/ https://reviews.llvm.org/D64672 Files: clang/docs/Relea

[PATCH] D63174: [clang][NewPM] Add RUNS for tests that produce slightly different IR under new PM

craig.topper added a comment. I'm going to try to work on the X86 tests. Can we hold off on committing those? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63174/new/ https://reviews.llvm.org/D63174 __

[PATCH] D60709: [ARM] Support inline assembler constraints for MVE.

craig.topper added inline comments. Comment at: cfe/trunk/lib/Basic/Targets/ARM.cpp:912 + return true; +} case 'U': // a memory reference... Is this supposed to fallthrough from 'T' to 'U'? If so can you add an LLVM_FALLTHROUGH Repository: rL LLV

[PATCH] D60709: [ARM] Support inline assembler constraints for MVE.

craig.topper added inline comments. Comment at: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp:14098 } + + case 2: Is this supposed to fallthrough from case 1 to case 2? Comment at: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp:14113 +

[PATCH] D63774: android: enable double-word CAS on x86_64

craig.topper added inline comments. Comment at: test/Driver/android-default-x86_64.c:1 +// RUN: %clang -### -target x86_64-unknown-linux-android -c %s 2>&1 | FileCheck %s +// CHECK: "-mcx16" should we just update the android 64 case in clang-translation.c instea

[PATCH] D63774: android: enable double-word CAS on x86_64

craig.topper added a comment. Another odd feature that's missing from early x86-64 CPUs is sahf. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63774/new/ https://reviews.llvm.org/D63774 ___ cfe-commits mailing list c

[PATCH] D63774: android: enable double-word CAS on x86_64

craig.topper added a comment. Yeah LAHF/SAHF just improves codegen. Lack of it won't result in any library calls. This patch LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63774/new/ https://reviews.llvm.org/D63774 ___

[PATCH] D63638: [clang][NewPM] Add new pass manager RUN lines to avx512f-builtins.c

craig.topper added a comment. @chandlerc ping CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63638/new/ https://reviews.llvm.org/D63638 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/c

[PATCH] D63638: [clang][NewPM] Add new pass manager RUN lines to avx512f-builtins.c

craig.topper added a comment. In D63638#1560846 , @spatel wrote: > I skimmed D63174 but haven't applied either > of these patches to test locally, so I may not have the full picture. > > IMO, we do not want clang regressi

[PATCH] D63638: [clang][NewPM] Add new pass manager RUN lines to avx512f-builtins.c

craig.topper added a comment. There's some inliner running because the intrinsics are implemented as always_inline functions and they are clearly being inlined in -O0. In a previous post, Chandler said the new PM has a special inliner for always_inline in -O0 and the old pass manager just used

[PATCH] D63638: [clang][NewPM] Add new pass manager RUN lines to avx512f-builtins.c

craig.topper added a comment. In D63638#1574740 , @leonardchan wrote: > In D63638#1574373 , @craig.topper > wrote: > > > There's some inliner running because the intrinsics are implemented as > > always_inline fun

[PATCH] D63638: [clang][NewPM] Add new pass manager RUN lines to avx512f-builtins.c

craig.topper added a comment. What if we just only check the output from the new pass manager. I don't think I care about the differences between the two. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D63638/new/ https://reviews.llvm.org/D63638 ___

[PATCH] D62019: [clang] Handle lrint/llrint builtins

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D62019/new/ https://reviews.llvm.org/D62019 ___ cfe-commits mailing list c

[PATCH] D62115: fix a issue that clang is incompatible with gcc with -H option.

craig.topper added inline comments. Comment at: lib/Frontend/HeaderIncludeGen.cpp:55 + // Simplify Filename that starts with "./" + if (Filename.startswith("./")); +Filename=Filename.substr(2); skan wrote: > lebedev.ri wrote: > > xiangzhangllvm wrote: > > >

[PATCH] D62367: [X86] VP2INTERSECT clang

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:518 case AVX512F: Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = This patch needs

[PATCH] D61472: [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

craig.topper added a comment. Ping CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61472/new/ https://reviews.llvm.org/D61472 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D61472: [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

craig.topper added a comment. In D61472#1515994 , @spatel wrote: > I haven't looked closely at the series of transforms that gets us here, so > let me ask: would it be more efficient to produce the add/inc/dec machine > instructions directly rather than

[PATCH] D62363: [X86] Enable intrinsics that convert float and bf16 data to each other

craig.topper added inline comments. Comment at: lib/Headers/avx512bf16intrin.h:37 +/// +/// This intrinsic corresponds to the EmitX86CvtBF16ToFloatExpr +/// function. This needs to be a comment that's useful to user's of the compiler not compiler developers. I

[PATCH] D62363: [X86] Enable intrinsics that convert float and bf16 data to each other

craig.topper added inline comments. Comment at: lib/Headers/avx512bf16intrin.h:37 +/// +/// This intrinsic corresponds to the EmitX86CvtBF16ToFloatExpr +/// function. skan wrote: > craig.topper wrote: > > This needs to be a comment that's useful to user's of th

[PATCH] D62367: [X86] VP2INTERSECT clang

craig.topper added inline comments. Comment at: lib/Headers/avx512vlvp2intersectintrin.h:39 + +static __inline__ void __DEFAULT_FN_ATTRS256 +_mm256_2intersect_epi32(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 *__m1) { Can you add doxygen comments for the

[PATCH] D62367: [X86] VP2INTERSECT clang

craig.topper added inline comments. Comment at: lib/Headers/avx512vlvp2intersectintrin.h:39 + +static __inline__ void __DEFAULT_FN_ATTRS256 +_mm256_2intersect_epi32(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 *__m1) { xiangzhangllvm wrote: > craig.topper

[PATCH] D62580: [OpenCL] Use long instead of long long in x86 builtins

craig.topper added inline comments. Comment at: clang/lib/AST/ASTContext.cpp:9308 case 'L': assert(!IsSpecial && "Can't use 'L' with 'W', 'N' or 'Z' modifiers"); assert(HowLong <= 2 && "Can't have modifier"); O should be mentioned here =

[PATCH] D62580: [OpenCL] Use long instead of long long in x86 builtins

craig.topper added a comment. In D62580#1521277 , @erichkeane wrote: > A different (perhaps silly) question is why 'W' isn't sufficient? It > represents int64_t, which I wonder if is sufficient. I had asked in a separate conversation not to change the

[PATCH] D55677: [Builltins][X86] Provide implementations of __lzcnt16, __lzcnt, __lzcnt64 for MS compatibility. Remove declarations from intrin.h and implementations from lzcntintrin.h

craig.topper created this revision. craig.topper added a reviewer: rnk. intrin.h had forward declarations for these and lzcntintrin.h had implementations that were only available with -mlzcnt or a -march that supported the lzcnt feature. But the 32-bit version was misnamed in lzcntrin.h This pa

[PATCH] D55677: [Builltins][X86] Provide implementations of __lzcnt16, __lzcnt, __lzcnt64 for MS compatibility. Remove declarations from intrin.h and implementations from lzcntintrin.h

craig.topper added a comment. yeah I'm now realizing that gcc does implement __lzcnt16 and __lzcnt64. How do I make this work? I tried guarding them with _MSC_VER, but I got redefinition errors on a couple tests from that. Does -ms-extensions not define _MSC_VER? CHANGES SINCE LAST ACTION ht

[PATCH] D55677: [Builltins][X86] Provide implementations of __lzcnt16, __lzcnt, __lzcnt64 for MS compatibility. Remove declarations from intrin.h and implementations from lzcntintrin.h

craig.topper updated this revision to Diff 178155. craig.topper added a comment. Replace the versions in lzcntintrin.h with macros that are only defined when _MSC_VER is not defined. This avoids a redefinition error when -ms-extensions is enabled which appears to not set _MSC_VER. I forgot to m

[PATCH] D55890: [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (clang)

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:9492 static Value *EmitX86AddSubSatExpr(CodeGenFunction &CGF, - SmallVectorImpl &Ops, + SmallVectorImpl &Ops, bool IsSigned,

[PATCH] D55890: [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (clang)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D55890/new/ https://reviews.llvm.org/D55890 ___ cfe

[PATCH] D55937: [X86] Auto upgrade XOP/AVX512 rotation intrinsics to generic funnel shift intrinsics (clang)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D55937/new/ https://reviews.llvm.org/D55937 ___ cfe

[PATCH] D56365: [X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd intrinsics.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. Herald added a subscriber: cfe-commits. Repository: rC Clang https://reviews.llvm.org/D56365 Files: lib/CodeGen/CGBuiltin.cpp test/CodeGen/avx512vbmi2-builtins.c test/CodeGen/avx512vlvbmi2-builtins.c Inde

[PATCH] D56365: [X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd intrinsics.

craig.topper updated this revision to Diff 180429. craig.topper added a comment. Add select checks. Move masking for variable vpshld/vpshrd to the intrinsic header. So now we don't need different builtins for mask and maskz. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D56365: [X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd builtins.

craig.topper updated this revision to Diff 180441. craig.topper added a comment. Rebase after fixing immediates to be in range without a modulo Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56365/new/ https://reviews.llvm.org/D56365 Files: include/clang/Basic/

[PATCH] D56529: [X86] Add versions of the avx512 gather intrinsics that take the mask as a vXi1 vector instead of a scalar (clang side)

craig.topper abandoned this revision. craig.topper added a comment. Abandoning because i sent it to llvm-commits instead of cfe-commits. Will redo to get the right mailing list CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56529/new/ https://reviews.llvm.org/D56529 _

[PATCH] D56530: [X86] Add versions of the avx512 gather intrinsics that take the mask as a vXi1 vector instead of a scalar (clang side)

craig.topper created this revision. craig.topper added reviewers: spatel, RKSimon. This is the clang equivalent of D56527 https://reviews.llvm.org/D56530 Files: include/clang/Basic/BuiltinsX86.def lib/CodeGen/CGBuiltin.cpp test/CodeGen/avx512f-builtins.c

[PATCH] D56530: [X86] Add versions of the avx512 gather intrinsics that take the mask as a vXi1 vector instead of a scalar (clang side)

craig.topper marked an inline comment as done. craig.topper added inline comments. Comment at: include/clang/Basic/BuiltinsX86.def:988 TARGET_BUILTIN(__builtin_ia32_gathersiv8df, "V8dV8dvC*V8iUcIi", "nV:512:", "avx512f") -TARGET_BUILTIN(__builtin_ia32_gathersiv16sf, "V16fV16fvC

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