[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to S11

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:58 const auto *RVFI = MF.getInfo(); if (RVFI->useSaveRestoreLibCalls(MF)) { paulkirth wrote: > craig.topper wrote: > > Can you add a FIXME here? Using x27 should

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to S11

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/shadowcallstack.ll:184 + +; RUN: llc -mtriple=riscv32 -mattr=+reserve-x27 < %s | FileCheck %s -check-prefix=RV32I +; RUN: llc -mtriple=riscv64 -mattr=+reserve-x27 < %s | FileCheck %s -check-prefix=RV64I ---

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141672/new/ https://reviews.llvm.org/D141672 ___

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

craig.topper added inline comments. Comment at: clang/tools/driver/cc1_main.cpp:189 + std::string Error; + const llvm::Target *TheTarget = + llvm::TargetRegistry::lookupTarget(TargetStr, Error); Why do we need to lookup the TargetRegistry? Repository:

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

craig.topper added inline comments. Comment at: clang/include/clang/Driver/Options.td:4346 MarshallingInfoFlag>; +def print_supported_marchs : Flag<["-", "--"], "print-supported-marchs">, + Group, Flags<[CC1Option, CoreOption]>, Maybe this should be -print-su

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146946/new/ https://reviews.llvm.org/D146946 ___

[PATCH] D146451: [RISCV] Replace RISCV->RISC-V in strings.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG0f4c9c016caf: [RISCV] Replace RISCV->RISC-V in strings. (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D146451?vs=5

[PATCH] D146449: [RISCV] Replace RISCV -> RISC-V in comments. NFC

This revision was automatically updated to reflect the committed changes. Closed by commit rG29463612d21b: [RISCV] Replace RISCV -> RISC-V in comments. NFC (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D146449?vs=506670&id=508710#toc Repository: rG LLVM Github

[PATCH] D144772: [Sema] Use isSVESizelessBuiltinType instead of isSizelessBuiltinType to prevent crashing on RISC-V.

craig.topper created this revision. craig.topper added reviewers: reames, asb, kito-cheng, eopXD, c-rhodes, frasercrmck, rogfer01. Herald added subscribers: luke, VincentWu, ctetreau, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edwa

[PATCH] D144772: [Sema] Use isSVESizelessBuiltinType instead of isSizelessBuiltinType to prevent crashing on RISC-V.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2e7311170201: [Sema] Use isSVESizelessBuiltinType instead of isSizelessBuiltinType to prevent… (authored by craig.topper). Repository: rG LLVM Git

[PATCH] D144853: [Clang][RISCV] Add CMake options to configure default CPU

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:324 - return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32"; + std::string DefaultCPU = Triple.isRISCV64() ? CLANG_RISCV64_DEFAULT_CPU +

[PATCH] D144990: [Sema] Add missing entries to the arrays in GetImplicitConversionName and GetConversionRank.

craig.topper created this revision. craig.topper added reviewers: aaron.ballman, erichkeane. Herald added a project: All. craig.topper requested review of this revision. Herald added a project: clang. It appears that ICK_Zero_Queue_Conversion was inserted into the ICK enum without updating this ta

[PATCH] D144990: [Sema] Add missing entries to the arrays in GetImplicitConversionName and GetConversionRank.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8ce68969b902: [Sema] Add missing entries to the arrays in GetImplicitConversionName and… (authored by craig.topper). Repository: rG LLVM Github Mo

[PATCH] D145125: [RISCV] Make D extension imply F extension.

craig.topper created this revision. craig.topper added reviewers: reames, asb, luismarques, kito-cheng. Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-j

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. In D145088#4165180 , @tschuett wrote: > Any binary that uses this feature is not forward portable to hardware > with a larger vector size. That's true for SVE as well. > > I did not understood this sentence. AFAIK, SVE us

[PATCH] D145125: [RISCV] Make D extension imply F extension.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG90f6a4cc73d5: [RISCV] Make D extension imply F extension. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTI

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added a comment. @reames and I recently talked and we agreed that vector crypto is far enough along that we'd like to get something committed to LLVM in experimental state. We can do iterative refinement if the spec continues to change. I guess the question is whether we should upd

[PATCH] D145809: [RISCV] Error if F and Zfinx extensions are specified together.

craig.topper created this revision. craig.topper added reviewers: reames, jrtc27, kito-cheng, asb. Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,

[PATCH] D145809: [RISCV] Error if F and Zfinx extensions are specified together.

craig.topper added a comment. In D145809#4185320 , @asb wrote: > The change itself looks good to me, but we have the same issue for D and > Zdinx as well. D implies F and Zdinx implies Zfinx so it should still trigger this error. I can add a test? Re

[PATCH] D145809: [RISCV] Error if F and Zfinx extensions are specified together.

craig.topper updated this revision to Diff 504203. craig.topper added a comment. Add test for D and Zdinx which will produce the same error as F and Zfinx. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145809/new/ https://reviews.llvm.org/D145809

[PATCH] D145817: [RISCV] Consistently place single quotes around extension names in erro messages.

craig.topper created this revision. craig.topper added reviewers: asb, luismarques, reames, kito-cheng. Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-j

[PATCH] D145809: [RISCV] Error if F and Zfinx extensions are specified together.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2800d57e124a: [RISCV] Error if F and Zfinx extensions are specified together. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHA

[PATCH] D145817: [RISCV] Consistently place single quotes around extension names in error messages.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGde76c016f722: [RISCV] Consistently place single quotes around extension names in error… (authored by craig.topper). Repository: rG LLVM Github Mon

[PATCH] D145857: [X86] Make triple ArchName override OS for i686 and i786

craig.topper added a comment. Did you test this? I kind of expected the triple would be normalized before this. I’m not at a computer to check. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145857/new/ https://reviews.llvm.org/D145857 ___

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Herald added a subscriber: jobnoorman. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:820 +errc::invalid_argument, +"zvk* requires v or zve* extension to also be specified"); + Put single quotes around extension

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. Herald added a subscriber: jobnoorman. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145088/new/ https://reviews.llvm.org/D145088 ___ cfe-commits mailing list cfe-commi

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:22 +TARGET_BUILTIN(__builtin_riscv_clz_32, "iUi", "nc", "zbb|xtheadbb") +TARGET_BUILTIN(__builtin_riscv_clz_64, "iULi", "nc", "zbb|xtheadbb,64bit") +TARGET_BUILTIN(__builtin_riscv_ctz_32,

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153235/new/ https://reviews.llvm.org/D153235 ___

[PATCH] D153161: [RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status.

craig.topper added inline comments. Comment at: clang/test/Driver/riscv-arch.c:376 -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izca -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1586 +/** +\brief Peeks next after next token I don't think this style of comment is common in llvm. Comment at: llvm/lib/Target/RISCV/AsmParse

[PATCH] D153403: [RISCV] Use unsigned types for orc_b builtins.

craig.topper created this revision. craig.topper added reviewers: Jim, asb. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrt

[PATCH] D153462: [Headers][doc] Add various arith/logical intrinsic descriptions to avx2intrin.h

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153462/new/ https://reviews.llvm.org/D153462 ___ cfe-commits mailing list c

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:135 {"xventanacondops", RISCVExtensionVersion{1, 0}}, +{"xsfcie", RISCVExtensionVersion{1, 0}}, }; Put this with xsfvcp Comment at: llvm/lib/Target/RISC

[PATCH] D153510: [Clang] Check type support for local variable declaration

craig.topper added a comment. @aaron.ballman The backend crashes at -O0 when scalable vector variables are declared because the stack frame code doesn't expect to see them when the vector extension isn't enabled. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://review

[PATCH] D153510: [Clang] Check type support for local variable declaration

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaDecl.cpp:8773 + + checkTypeSupport(T, NewVD->getLocation(), cast(CurContext)); } This feels heavy handed for not RISC-V vector types. Can we put the RISC-V code from checkTypeSupport in a funct

[PATCH] D153161: [RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG08f1aa87281f: [RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status. (authored by craig.topper). Changed prior to commit: https://revi

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

craig.topper added a comment. In D153170#4441462 , @jrtc27 wrote: > Can we have an expensive check that the table is sorted? Yeah. I was going to do it when I made use of the sorted property, but it makes more sense to be in this patch. I'll probably do

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

craig.topper updated this revision to Diff 533678. craig.topper added a comment. Verify the table is sorted. This uses the same pattern we use to check sorted tables in other places like X86InstrFMA3Info.cpp. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llv

[PATCH] D153576: [Headers] Fix up some conditionals

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153576/new/ https://reviews.llvm.org/D153576 ___ cfe-commits mailing list c

[PATCH] D153576: [Headers] Fix up some conditionals

craig.topper added a comment. The mulx function being 32-bit mode only is also true in gcc. It probably won't generate a mulx instruction on x86-64. Maybe that's why it was 32-bit only? But it should still be functionally correct. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153576/ne

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGe4a93d80f425: [RISCV] Sort the extensions in SupportedExtensions and… (authored by craig.topper). Changed prior to commit: https://reviews.llvm.or

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:123 {"xsfvcp", RISCVExtensionVersion{1, 0}}, +{"xsfcie", RISCVExtensionVersion{1, 0}}, {"xtheadba", RISCVExtensionVersion{1, 0}}, Alphabetize. Comme

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

craig.topper accepted this revision. craig.topper added inline comments. This revision is now accepted and ready to land. Comment at: llvm/docs/ReleaseNotes.rst:209 disassembler/assembler. +* Added support for the vendor-defined Xsfcie (SiFive SCIE) extension + disassembler/a

[PATCH] D153659: [RISCV] Fix name mangling for LMUL!=1 vector types with attribute(rvv_vector_bits)

craig.topper created this revision. craig.topper added reviewers: aaron.ballman, reames, eopXD, kito-cheng, frasercrmck, rogfer01. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Ma

[PATCH] D153510: [Clang] Check type support for local variable declaration

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaDecl.cpp:8780 } + if (T->isRVVType()) +checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext)); Add a blank line before this to separate it from SVE Repository: rG LLVM Github M

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper added inline comments. Herald added a subscriber: wangpc. Comment at: clang/lib/Basic/Targets/RISCV.cpp:369 +Feature = Feature.trim(); +StringRef Attrstring = Feature.split("=").second.trim(); + Attrstring -> AttrString Com

[PATCH] D153510: [Clang][RISCV] Check type support for local variable declaration of RVV type

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:4968 +void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { + const TargetInfo &TI = Context.getTargetInfo(); + if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) &&

[PATCH] D153510: [Clang][RISCV] Check type support for local variable declaration of RVV type

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:4968 +void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { + const TargetInfo &TI = Context.getTargetInfo(); + if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) &&

[PATCH] D153510: [Clang][RISCV] Check type support for local variable declaration of RVV type

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:4967 +void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { + const TargetInfo &TI = Context.getTargetInfo(); What about the bool types? Is it sufficient

[PATCH] D153510: [Clang][RISCV] Check type support for local variable declaration of RVV type

craig.topper added a comment. Does the code do the right FP checks for tuples? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153510/new/ https://reviews.llvm.org/D153510 ___ cfe-commits mailing list cfe-

[PATCH] D153510: [Clang][RISCV] Check type support for local variable declaration of RVV type

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:4967 +void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { + const TargetInfo &TI = Context.getTargetInfo(); craig.topper wrote: > What about the bool ty

[PATCH] D153403: [RISCV] Use unsigned types for orc_b builtins.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf67dfb3cdb4b: [RISCV] Use unsigned types for orc_b builtins. (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D153403

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

craig.topper added a comment. In D153370#4447817 , @garvitgupta08 wrote: > Addressed the changes. I do not have commit access, could you please commit > this differential on my behalf? Thanks. Yes. Can you provide the name and email address for the git

[PATCH] D153510: [Clang][RISCV] Check type support for local variable declaration of RVV type

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:4969 + const TargetInfo &TI = Context.getTargetInfo(); + if ((Ty->isRVVBoolType() || + Ty->isRVVType(/* Bitwidth */ 8, /* IsFloat */ false) || We don't to check exactly what t

[PATCH] D153510: [Clang][RISCV] Check type support for local variable declaration of RVV type

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153510/new/ https://reviews.llvm.org/D153510 ___

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

This revision was automatically updated to reflect the committed changes. Closed by commit rG4c37d30e22ae: [RISCV] Add support for custom instructions for Sifive S76. (authored by garvitgupta08, committed by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:/

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:105 +.addImm(FRMImm); +MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, +/*IsImp*/ true)); ---

[PATCH] D152628: [RISCV] Add __builtin_riscv_zip/unzip for Zbkb to match gcc.

craig.topper added a comment. Herald added a subscriber: wangpc. In D152628#4416794 , @asb wrote: > I'm not super familiar with these builtins so this might be a silly question > why are the new builtins added in this patch LiLi (long int) rather than Zi

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:385 + StringRef ExtName = Ext.substr(1); + if (llvm::RISCVISAInfo::isSupportedExtensionWithVersion(ExtName) || + llvm::RISCVISAInfo::isSupportedExtension(ExtName)) ---

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:78 +// The value '7' is a hint to this pass to not alter the frm value. +if (FRMImm == 7) + continue; Use `RISCVFPRndMode::DYN`? =

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:21 #include "llvm/ADT/StringSwitch.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/MC/MCInstrDesc.h" We can't include a CodeGen header in MCTargetDesc

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:78 + +// The value '7' is a hint to this pass to not alter the frm value. +if (FRMImm == RISCVFPRndMode::DYN) Don't write 7 here Repository: rG L

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152996/new/ https://reviews.llvm.org/D152996 ___

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:385 + StringRef ExtName = Ext.substr(1); + if (llvm::RISCVISAInfo::isSupportedExtensionWithVersion(ExtName) || + llvm::RISCVISAInfo::isSupportedExtension(ExtName)) ---

[PATCH] D154171: [RISCV] Mark zvkn* and zvks* extensions as enabled when all their subextensions are.

craig.topper created this revision. craig.topper added reviewers: 4vtomat, ego, kito-cheng, eopXD. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer0

[PATCH] D154171: [RISCV] Mark zvkn* and zvks* extensions as enabled when all their subextensions are.

craig.topper added a comment. In D154171#4462182 , @eopXD wrote: > ~~Do we need to do the same for v extension?~~ > > I didn't understand the problem fully, we don't need to care about v > extension here because 'v' itself adds something new to the archi

[PATCH] D154171: [RISCV] Mark zvkn* and zvks* extensions as enabled when all their subextensions are.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb4609b4106f3: [RISCV] Mark zvkn* and zvks* extensions as enabled when all their subextensions… (authored by craig.topper). Repository: rG LLVM Git

[PATCH] D154181: [x86] Add missing FeatureCMOV in frontend targets.

craig.topper added inline comments. Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:325 + { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B }, + { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B }, { {"pentium2"}, CK

[PATCH] D154181: [x86] Add missing FeatureCMOV in frontend targets.

craig.topper added inline comments. Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:325 + { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B }, + { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B }, { {"pentium2"}, CK

[PATCH] D154181: [x86] Add missing FeatureCMOV in frontend targets.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154181/new/ https://reviews.llvm.org/D154181 ___

[PATCH] D154209: [X86] Add missing features for ivybridge, sandybridge and knl in X86TargetParser.def.

craig.topper added inline comments. Comment at: llvm/include/llvm/TargetParser/X86TargetParser.def:275 CPU_SPECIFIC("core_5th_gen_avx_tsx", "broadwell", 'Y', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx") -CPU_SPECIFI

[PATCH] D153659: [RISCV] Fix name mangling for LMUL!=1 vector types with attribute(rvv_vector_bits)

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153659/new/ https://reviews.llvm.org/D153659 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.llvm.org/D146054 ___ cfe-commits mailing list cfe-commits

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

craig.topper created this revision. craig.topper added reviewers: reames, asb, jrtc27, kito-cheng, philipp.tomsich. Herald added subscribers: jobnoorman, luke, VincentWu, ormris, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, Pk

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

craig.topper updated this revision to Diff 509481. craig.topper added a comment. Zve32x needs to imply Zicsr too Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147179/new/ https://reviews.llvm.org/D147179 Files: clang/test/CodeGen/RISCV/rvv-intri

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

craig.topper added a comment. Does the kernel populate the initial value of the register for the shadow stack or is that done by a runtime inside the application? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146463/new/ https://reviews.llvm.org/D

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

craig.topper added a comment. In D146463#4232221 , @mcgrathr wrote: > In D146463#4232214 , @craig.topper > wrote: > >> Does the kernel populate the initial value of the register for the shadow >> stack or is tha

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

craig.topper updated this revision to Diff 509707. craig.topper added a comment. Address review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147179/new/ https://reviews.llvm.org/D147179 Files: clang/test/CodeGen/RISCV/rvv-intrinsics-ha

[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

craig.topper created this revision. craig.topper added reviewers: reames, asb, kito-cheng, jrtc27, philipp.tomsich, dnpetrov-sc. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, t

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

craig.topper updated this revision to Diff 509812. craig.topper added a comment. Updated release notes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147179/new/ https://reviews.llvm.org/D147179 Files: clang/test/CodeGen/RISCV/rvv-intrinsics-hand

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGdc90af501f00: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version (authored by craig.topper). Repository: rG LLVM Github Monor

[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG96a7e057567d: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANG

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145088/new/ https://reviews.llvm.org/D145088 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

craig.topper added a comment. There no backend tests in this patch. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:19625 if ((ICEArguments & (1 << i)) == 0) { Ops.push_back(EmitScalarExpr(E->getArg(i))); continue; Need to force ICEArguments for

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaType.cpp:8234 + ParsedAttr &Attr, Sema &S) { + // Target must have SVE. + if (!S.Context.getTargetInfo().hasFeature("zve32x")) { I need to fix this co

[PATCH] D147497: [AArch64] Use fneg instead of fsub -0.0, X Cin IR expansion of __builtin_neon_vfmsh_f16.

craig.topper created this revision. craig.topper added reviewers: efriedma, dmgreen, SjoerdMeijer, john.brawn. Herald added a subscriber: kristof.beyls. Herald added a project: All. craig.topper requested review of this revision. Herald added a project: clang. Addresses the FIXME and removes the o

[PATCH] D147497: [AArch64] Use fneg instead of fsub -0.0, X Cin IR expansion of __builtin_neon_vfmsh_f16.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG0109f8d1e3bf: [AArch64] Use fneg instead of fsub -0.0, X Cin IR expansion of… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHA

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

craig.topper accepted this revision. craig.topper added a comment. LGTM other than that one comment. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:86 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { - if (RISCV::isX18ReservedByDefault(TT)) -UserRes

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

craig.topper added a comment. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147610/new/ https://reviews.llvm.org/D147610 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147612/new/ https://reviews.llvm.org/D147612 ___ cfe-commits mailing list c

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/ https://reviews.llvm.org/D147611 ___ cfe-commits mailing list c

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

craig.topper added inline comments. Comment at: clang/lib/Driver/Driver.cpp:4236 + +// Use the -march=help flag as the dummy input to cc1. +Actions.clear(); MaskRay wrote: > Why is the code needed? Can --print-supported-extensions reuse the approach > of

[PATCH] D147978: [RISCV] Remove getCPUFeaturesExceptStdExt.

craig.topper created this revision. craig.topper added reviewers: asb, reames, kito-cheng, khchen, jrtc27, luismarques. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Mart

[PATCH] D147986: [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice versa.

craig.topper created this revision. craig.topper added reviewers: asb, reames, luismarques, kito-cheng. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer

[PATCH] D147986: [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice versa.

craig.topper updated this revision to Diff 512312. craig.topper added a comment. Upload the whole patch Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147986/new/ https://reviews.llvm.org/D147986 Files: clang/include/clang/Basic/DiagnosticDriverK

[PATCH] D147986: [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice versa.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG88d631198255: [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice… (authored by craig.topper). Repository: rG LLVM Githu

[PATCH] D147978: [RISCV] Remove getCPUFeaturesExceptStdExt.

This revision was automatically updated to reflect the committed changes. Closed by commit rG5e2d8a352888: [RISCV] Remove getCPUFeaturesExceptStdExt. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147978/new/ https://revie

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145088/new/ https://reviews.llvm.org/D145088 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:19975 +llvm::Type *ResTy = ConvertType(E->getType()); +ConstantInt *Mode = llvm::cast(Ops[1]); + Is `llvm::` needed on the `cast`? I think cast is imported into the clang nam

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

craig.topper added a comment. Code like `llvm::combineMetadataForCSE` assumes that the !nontemporal metadata can be copied from one node if both nodes have it. If the 2 nodes have different values we need a rule of which one to pick. We can't just pick arbitrarily. Repository: rG LLVM Githu

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