[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.

LGTM other than that one comment.



================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:86
       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
-  if (RISCV::isX18ReservedByDefault(TT))
-    UserReservedRegister.set(RISCV::X18);
 
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
----------------
Drop the blank line here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146463/new/

https://reviews.llvm.org/D146463

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