[PATCH] D50168: [Builtins] Implement __builtin_clrsb to be compatible with gcc

craig.topper added a comment. Ping https://reviews.llvm.org/D50168 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50168: [Builtins] Implement __builtin_clrsb to be compatible with gcc

craig.topper updated this revision to Diff 159627. craig.topper added a comment. Add the test case that I failed to pick up in the original diff. https://reviews.llvm.org/D50168 Files: include/clang/Basic/Builtins.def lib/CodeGen/CGBuiltin.cpp test/CodeGen/builtin_clrsb.c Index: test/Co

[PATCH] D50168: [Builtins] Implement __builtin_clrsb to be compatible with gcc

craig.topper updated this revision to Diff 159753. craig.topper added a comment. Use ctlz(zero_undef=false) and sub https://reviews.llvm.org/D50168 Files: include/clang/Basic/Builtins.def lib/CodeGen/CGBuiltin.cpp test/CodeGen/builtin_clrsb.c Index: test/CodeGen/builtin_clrsb.c

[PATCH] D45619: [Time-report] (1) Use special new Clang flag 'FrontendTimesIsEnabled' instead of 'llvm::TimePassesIsEnabled' inside -ftime-report feature

craig.topper added a comment. Correct me if I'm wrong, but after this change llvm no longer enables the timing of individual passes when -ftime-report is passed? Was that intentional? Repository: rL LLVM https://reviews.llvm.org/D45619 ___ cfe-c

[PATCH] D45619: [Time-report] (1) Use special new Clang flag 'FrontendTimesIsEnabled' instead of 'llvm::TimePassesIsEnabled' inside -ftime-report feature

craig.topper added a comment. Ok I'll add that back. I'm unclear why the we would want to assign clang's FrontendTimesIsEnabled from inside CodeGenAction. If I'm understanding the intentions here, the goal was to add more timing infrastructure to clang. But if the enabling is tied to CodeGenAc

[PATCH] D45619: [Time-report] (1) Use special new Clang flag 'FrontendTimesIsEnabled' instead of 'llvm::TimePassesIsEnabled' inside -ftime-report feature

craig.topper added a comment. Assignment restored in r339281. I'll file a bug to merge to 7.0 Repository: rL LLVM https://reviews.llvm.org/D45619 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listin

[PATCH] D50471: [Builtins] Add __bulitin_clrsb support to IntExprEvaluator::VisitBuiltinCallExpr

craig.topper created this revision. craig.topper added reviewers: bkramer, erichkeane. Now that __builtin_clrsb is supported by clang, this patch adds constant evaluation of it to address the FIXME. https://reviews.llvm.org/D50471 Files: lib/AST/ExprConstant.cpp test/Sema/constant-builtins

[PATCH] D50471: [Builtins] Add __bulitin_clrsb support to IntExprEvaluator::VisitBuiltinCallExpr

craig.topper updated this revision to Diff 159777. craig.topper added a comment. Fix duplicate variable name in the test. Not sure why that didn't complain https://reviews.llvm.org/D50471 Files: lib/AST/ExprConstant.cpp test/Sema/constant-builtins-2.c Index: test/Sema/constant-builtins-2.

[PATCH] D50678: [InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly

craig.topper created this revision. craig.topper added reviewers: chandlerc, rsmith, rnk. Herald added a subscriber: eraman. Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits ty

[PATCH] D46892: [X86] Lowering addus/subus intrinsics to native IR (Clang part)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D46892 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D50815: Establish the header

craig.topper added inline comments. Comment at: include/bit:145 + static_assert(sizeof(unsigned) == 4, ""); + return __popcnt(__x); +#endif How does this work on pre-Haswell X86 CPUs? Doesn't MSVC just blindly emit the popcnt instruction when it sees this? h

[PATCH] D50815: Establish the header

craig.topper added inline comments. Comment at: include/bit:163 + static_assert(sizeof(unsigned long long) == 8, ""); + return __popcnt64(__x); +#endif I don't think __popcnt64 exists in MSVC when targeting 32-bit mode. https://reviews.llvm.org/D50815

[PATCH] D50907: Make __shiftleft128 / __shiftright128 real compiler built-ins.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D50907 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D50876: Clean up newly created header

craig.topper added inline comments. Comment at: include/bit:140 static_assert(sizeof(unsigned) == 4, ""); return __popcnt(__x); } MSVC blindly uses the popcnt instruction whenever it sees this intrinsic. So this only works on Nehalem and newer Intel CPUs.

[PATCH] D46540: [X86] ptwrite intrinsic

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D46540 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper added inline comments. Comment at: lib/CodeGen/CodeGenFunction.cpp:2346 + return Feat.substr(1) == F.getKey(); + })) +ReqFeatures.insert(ReqFeatures.begin(), F.getKey()); This and the next line a

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper added inline comments. Comment at: lib/CodeGen/CodeGenFunction.cpp:2342 // Only positive features are "required". - if (F.getValue()) + if (F.getValue()) { +if (std::any_of(ParsedAttr.Features.begin(), ParsedAttr.Features.end(), -

[PATCH] D46349: [X86] Mark builtins 'const' where possible

craig.topper added a comment. Ping https://reviews.llvm.org/D46349 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper added a comment. This looks pretty good to me. @echristo what do you think? https://reviews.llvm.org/D46541 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D46656: [Builtins] Improve the IR emitted for MSVC compatible rotr/rotl builtins to match what the middle and backends understand

craig.topper created this revision. craig.topper added a reviewer: spatel. Currently we emit something like rotl(x, n) { n &= bitwidth -1; return n != 0 ? ((x << n) | (x >> (bitwidth - n)) : x; } We use a select to avoid the undefined behavior on the (bitwidth - n) shift. The middle and backend

[PATCH] D46683: [X86] Assume alignment of movdir64b dst argument

craig.topper added a comment. What effect does this have? Repository: rC Clang https://reviews.llvm.org/D46683 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D46683: [X86] Assume alignment of movdir64b dst argument

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D46683 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D46742: [X86] Use __builtin_convertvector to replace some of the avx512 truncate builtins.

craig.topper created this revision. craig.topper added reviewers: RKSimon, GBuella, tkrupa. As long as the destination type is a 256 or 128 bit vector we can use __builtin_convertvector to directly generate trunc IR instruction which will be handled natively by the backend. Repository: rC Cl

[PATCH] D46742: [X86] Use __builtin_convertvector to replace some of the avx512 truncate builtins.

craig.topper added a comment. Yeah the others will need codegen work. So I'm starting with the easy cases. Repository: rC Clang https://reviews.llvm.org/D46742 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/

[PATCH] D46863: [X86] Use __builtin_convertvector to implement some of the packed integer to packed flow conversion intrinsics.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. I believe this is safe assuming default rounding mode. The conversion might be inexact, but it can never overflow the FP type so this shouldn't be undefined behavior for the uitofp/sitofp instructions. We already

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper added a comment. Ping @echristo https://reviews.llvm.org/D46541 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D46881: [X86][CET] Changing -fcf-protection behavior to comply with gcc (clang part)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D46881 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D46881: [X86][CET] Changing -fcf-protection behavior to comply with gcc (clang part)

craig.topper added a comment. LGTM https://reviews.llvm.org/D46881 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47029: [X86] Remove some preprocessor feature checks from intrinsic headers

craig.topper created this revision. craig.topper added reviewers: echristo, RKSimon, spatel. These look to be a couple things that weren't remvoed when we switched to target attribute. The popcnt makes including just smmintrin.h also include popcntintrin.h. The popcnt file itself already contai

[PATCH] D47125: [X86] Remove masking from pternlog llvm intrinsics and use a select instruction instead.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel, GBuella. Because the intrinsics in the headers are implemented as macros, we can't just use a select builtin and pternlog builtin. This would require one of the macro arguments to be used twice. Depending on what

[PATCH] D47125: [X86] Remove masking from pternlog llvm intrinsics and use a select instruction instead.

craig.topper added a comment. Because the builtins take one of the arguments as an immediate, they must be implemented as macros. This was the frontend can verify that it's an imediate or a constant expression. Repository: rC Clang https://reviews.llvm.org/D47125

[PATCH] D47142: [x86] invpcid intrinsic

craig.topper added inline comments. Comment at: lib/Headers/cpuid.h:158 #define bit_BMI20x0100 +#define bit_INVCPID 0x0400 #define bit_ENH_MOVSB 0x0200 this should be below ENH_MOVSB to keep the bits in order Comment

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper added a comment. I think you can pass StringRef(F).substr(1). That won't create a temporary string. It will just create a StringRef pointing into the middle of an existing std::string stored in the parsed attributes. https://reviews.llvm.org/D46541 _

[PATCH] D46863: [X86] Use __builtin_convertvector to implement some of the packed integer to packed float conversion intrinsics.

craig.topper added a comment. So I think we've covered the whether this is ok to do questions. If someone can double check signed/unsigned and vector element sizes are all correct and approve this that would be great. Repository: rC Clang https://reviews.llvm.org/D46863 _

[PATCH] D47174: [X86] Move 128-bit f16c intrinsics to __emmintrin_f16c.h include from emmintrin.h. Move 256-bit f16c intrinsics back to f16cintrin.h

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel, echristo, DavidKreitzer. Intel documents the 128-bit versions as being in emmintrin.h and the 256-bit version as being in immintrin.h. This patch makes a new __emmtrin_f16c.h to hold the 128-bit versions to be in

[PATCH] D47174: [X86] Move 128-bit f16c intrinsics to __emmintrin_f16c.h include from emmintrin.h. Move 256-bit f16c intrinsics back to f16cintrin.h

craig.topper added inline comments. Comment at: lib/Headers/immintrin.h:72 -/* The 256-bit versions of functions in f16cintrin.h. - Intel documents these as being in immintrin.h, and Interesting this to note here, the 256-bit f16c intrinsics were being guarde

[PATCH] D47182: [X86] Move all Intel defined intrinsic includes into immintrin.h

craig.topper created this revision. craig.topper added reviewers: DavidKreitzer, echristo, RKSimon, rnk. This matches the Intel documentation which shows them available by importing immintrin.h. x86intrin.h also includes immintrin.h so anyone including x86intrin.h will still get them. This is d

[PATCH] D47182: [X86] Move all Intel defined intrinsic includes into immintrin.h

craig.topper added a comment. First there was mmintrin.h which covered MMX instructions. Then xmmintrin.h came along to support SSE1 and implicitly included mmintrin.h. The emmintrin.h to support SSE2 and implicitly included xmmintrin.h. This repeated for each new version of SSE. With each head

[PATCH] D47202: [CodeGen] use nsw negation for abs

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. This seems right to me. GCC believes believes that __bultin_abs always returns a positive number. https://reviews.llvm.org/D47202 __

[PATCH] D47174: [X86] Move 128-bit f16c intrinsics to __emmintrin_f16c.h include from emmintrin.h. Move 256-bit f16c intrinsics back to f16cintrin.h

craig.topper added a comment. It is odd, but they really are split in the icc include files. So they got split a while back in clang to match the Intel Intrinsic Guide documentation. Repository: rC Clang https://reviews.llvm.org/D47174 ___ cfe-c

[PATCH] D47174: [X86] Move 128-bit f16c intrinsics to __emmintrin_f16c.h include from emmintrin.h. Move 256-bit f16c intrinsics back to f16cintrin.h

craig.topper added a comment. Implemented @DavidKreitzer's suggestion in r333033 Repository: rL LLVM https://reviews.llvm.org/D47174 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commit

[PATCH] D47182: [X86] Move all Intel defined intrinsic includes into immintrin.h

craig.topper updated this revision to Diff 148115. craig.topper added a comment. Leave the message still saying x86intrin.h. Change the error checks to look for either x86intrin.h or immintrin.h to have been included. Really only the immintrin.h check is necessary since that's the header that do

[PATCH] D47182: [X86] Move all Intel defined intrinsic includes into immintrin.h

craig.topper updated this revision to Diff 148252. craig.topper added a comment. Add back popcntintrin.h https://reviews.llvm.org/D47182 Files: lib/Headers/cldemoteintrin.h lib/Headers/clzerointrin.h lib/Headers/immintrin.h lib/Headers/movdirintrin.h lib/Headers/pconfigintrin.h lib/

[PATCH] D46863: [X86] Use __builtin_convertvector to implement some of the packed integer to packed float conversion intrinsics.

craig.topper added a comment. Hi @aemerson, I'm not opposed to adding it back. But the clang policy for vector builtins has always been that we won't support all the builtins that gcc does and to encourage the use of the _mm_* wrappers which are guaranteed to work in both compilers. It possible

[PATCH] D47277: [modules] Mark __wmmintrin_pclmul.h/__wmmintrin_aes.h as textual

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D47277 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D47142: [x86] invpcid intrinsic

craig.topper added a comment. LGTM, if you fix the ordering in cpuid.h. https://reviews.llvm.org/D47142 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47401: [X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.

craig.topper added inline comments. Comment at: cfe/trunk/lib/Headers/avx512fintrin.h:9855 + __v8di __t6 = (__v8di)_mm512_##op(__t4, __t5); \ + return __t6[0]; RKSimon wrote: > Would it be dumb to allow VLX capable CPUs to use 128/256 variants of the > VPMAX

[PATCH] D47444: [X86] Lowering FMA intrinsics to native IR (Clang part)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/CodeGen/CGBuiltin.cpp:8416 +static Value *EmitX86FMAExpr(CodeGenFunction &CGF, ArrayRef Ops, + unsigned BuiltinID) { + -

[PATCH] D47474: Implement cpu_dispatch/cpu_specific Multiversioning

craig.topper added inline comments. Comment at: include/clang/Basic/X86Target.def:295 +CPU_SPECIFIC("pentium_iii", 'H', + (1ULL << FEATURE_CMOV | 1ULL << FEATURE_MMX | 1ULL << FEATURE_SSE)) +CPU_SPECIFIC("pentium_iii_no_xmm_regs", 'H', Could we just

[PATCH] D38824: [X86] Synchronize the CPU predefined macros with gcc

craig.topper created this revision. Herald added a subscriber: krytarowski. We were using corei7 for a large swatch of Intel CPUs. gcc has a different defines that more closely match the march flags. This updates to match. It also fixes skylake-avx512 and adds silvermont in addition to slm. h

[PATCH] D38824: [X86] Synchronize the CPU predefined macros with gcc

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:844-845 -// FIXME: Historically, we defined this legacy name, it would be nice to -// remove it at some point. We've never exposed fine-grained names for -// recent primary x86 CPUs, and we shou

[PATCH] D38781: [X86] Add CLWB intrinsic. clang part

craig.topper updated this revision to Diff 118816. craig.topper added a comment. Address review feedback https://reviews.llvm.org/D38781 Files: include/clang/Basic/BuiltinsX86.def lib/Headers/CMakeLists.txt lib/Headers/clwbintrin.h lib/Headers/immintrin.h test/CodeGen/builtin-clwb.c

[PATCH] D38824: [X86] Synchronize the CPU predefined macros with gcc

craig.topper updated this revision to Diff 118973. craig.topper added a comment. Only define "corei7" on nehalem/westmere to match gcc. Don't define anything for the CPUs newer than that. Add comments to the CPUs where gcc has two sets of defines and we have only one. https://reviews.llvm.org/

[PATCH] D38737: [X86] test/testn intrinsics lowering to IR. clang side

craig.topper added inline comments. Comment at: lib/Headers/avx512bwintrin.h:2109 + return _mm512_cmp_epi8_mask(_mm512_and_epi32(__A, __B), +_mm512_setzero_qi(), 4); } Can you align this with the opening paren on the line above? Same with all th

[PATCH] D51510: Move AESNI generation to Skylake and Goldmont

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM. Can you update lib/Target/X86/X86.td in LLVM repo as well? Repository: rC Clang https://reviews.llvm.org/D51510 ___ cfe-comm

[PATCH] D51510: Move AESNI generation to Skylake and Goldmont

craig.topper added a comment. Do you have commit access, or do you need someone to commit this for you? Repository: rC Clang https://reviews.llvm.org/D51510 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mai

[PATCH] D51771: [X86] Modify addcarry/subborrow builtins to emit an 2 result and intrinsic and an store instruction.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. Herald added subscribers: cfe-commits, kristina. This is the clang side of https://reviews.llvm.org/D51769. The llvm intrinsics now return two results instead of using an out parameter. Repository: rC Clang ht

[PATCH] D51805: [X86] Custom emit __builtin_rdtscp so we can emit an explicit store for the out parameter

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. This is the clang side of https://reviews.llvm.org/D51803. The llvm intrinsic now returns two results. So we need to emit an explicit store in IR for the out parameter. This is similar to addcarry/subborrow/rdrand

[PATCH] D49606: [ms] Add __shiftleft128 / __shiftright128 intrinsics

craig.topper added a comment. @spatel, should this ultimately use funnel shift? https://reviews.llvm.org/D49606 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49606: [ms] Add __shiftleft128 / __shiftright128 intrinsics

craig.topper added a comment. Here are the IR patterns for this that work. Not sure if we can do this directly in C, we need a 128 bit type, but maybe we can emit it from CGBuiltin.cpp? define i64 @__shiftleft128(i64 %x, i64 %y, i8 %amt) { %a = zext i64 %x to i128 %b = zext i64 %y to

[PATCH] D49606: [ms] Add __shiftleft128 / __shiftright128 intrinsics

craig.topper added a comment. I'd prefer the pattern over inline assembly. It'll give us more flexibility in the backend if we should be using some other instruction on different targets. https://reviews.llvm.org/D49606 ___ cfe-commits mailing list

[PATCH] D49606: [ms] Add __shiftleft128 / __shiftright128 intrinsics

craig.topper added a comment. @spatel, yes its exactly funnel shift. I wasn't sure if we were ready for clang to create it yet or not. Can we let this go as is and change it to funnel shift once we have the variable case fixed in the backend? https://reviews.llvm.org/D49606

[PATCH] D49606: [ms] Add __shiftleft128 / __shiftright128 intrinsics

craig.topper added a comment. The only weird thing that I can really think of with the C version is that the 'and' on the shift amount might get hoisted out of a loop and not get dropped during isel. https://reviews.llvm.org/D49606 ___ cfe-commits

[PATCH] D49606: [ms] Add __shiftleft128 / __shiftright128 intrinsics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM. I'm inclined to let this go in now since we have a requested use for it. We can change it to funnel shift once we're confident in the backend. https://reviews.llvm.org/D4960

[PATCH] D50168: [Builtins] Implement __builtin_clrsb to be compatible with gcc

craig.topper created this revision. craig.topper added reviewers: bkramer, efriedma, spatel. Herald added a reviewer: javed.absar. Herald added a subscriber: kristof.beyls. gcc defines an intrinsic called __builtin_clrsb which counts the number of extra sign bits on a number. This is equivalent t

[PATCH] D43041: Add X86 Support to ValidCPUList (enabling march notes)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D43041 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D41880: Adding nocf_check attribute for cf-protection fine tuning

craig.topper added inline comments. Comment at: lib/Sema/SemaDeclAttr.cpp:2007 + +bool Sema::CheckAttrNoArgs(const AttributeList &Attr) { + if (!checkAttributeNumArgs(*this, Attr, 0)) { Wy did this get renamed? Comment at: lib/Sema/SemaDeclAtt

[PATCH] D43394: [X86] Add 'sahf' CPU feature, and emit __LAHFSAHF__ for it

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:295 setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "movbe", true); break; KNM and KNL should both have sahf Comment at: li

[PATCH] D43394: [X86] Add 'sahf' CPU feature, and emit __LAHFSAHF__ for it

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:1049 + if (HasLAHFSAHF) +Builder.defineMacro("__LAHFSAHF__"); dim wrote: > craig.topper wrote: > > Does gcc define this? It's such a low level instruction I have a hard time > > bel

[PATCH] D43394: [X86] Add 'sahf' CPU feature to frontend

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D43394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D43459: [X86] Disable CLWB in Cannon Lake

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D43459 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D33356: [Nios2] Changes in frontend to support Nios2 LLVM target

craig.topper added a comment. Is there enough functional here that there should be tests for? i.e. make sure march/mcpu switches are recognized, that the target is recognized, etc. https://reviews.llvm.org/D33356 ___ cfe-commits mailing list cfe-co

[PATCH] D33356: [Nios2] Changes in frontend to support Nios2 LLVM target

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/Basic/Targets.cpp:7678 +for (const char *feature : allFeatures) { +Features[feature] = isFeatureSupportedByCPU(feature, CPU); +

[PATCH] D40478: Added control flow architecture protection Flag

craig.topper added inline comments. Comment at: lib/CodeGen/CGCall.cpp:1737 llvm::toStringRef(CodeGenOpts.NoSignedZeros)); +FuncAttrs.addAttribute("shstk-compatible", + llvm::toStringRef(CodeGenOpts.ShstkCompatible));

[PATCH] D40478: Added control flow architecture protection Flag

craig.topper added a comment. Are we sure we want a different command line option name from gcc? From our internal conversations with the gcc folks I thought they were suggesting that -fcf-protection could imply a software mechanism if a hardware mechanism was not available thorugh -mibt or -ma

[PATCH] D41517: mmintrin.h documentation fixes and updates

craig.topper added inline comments. Comment at: lib/Headers/mmintrin.h:88 /// -/// This intrinsic corresponds to the VMOVQ / MOVD instruction. +/// This intrinsic corresponds to the MOVD instruction. /// Shouldn't this be MOVQ? Comment at

[PATCH] D41523: xmmintrin.h documentation fixes and updates

craig.topper added inline comments. Comment at: lib/Headers/xmmintrin.h:1706 /// -/// This intrinsic corresponds to the VMOVSS / MOVSS + shuffling +/// This intrinsic corresponds to the VBROADCASTSS / BROADCASTSS ///instruction. There is no BROADCASTSS

[PATCH] D41516: emmintrin.h documentation fixes and updates

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D41516 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D41557: [x86][icelake][vbmi2]

craig.topper added a comment. Update the ICL macros in test/Preprocessor/predefined-arch-macros.c Comment at: include/clang/Basic/BuiltinsX86.def:1254 +TARGET_BUILTIN(__builtin_ia32_vpshldd512_mask, "V16iV16iV16iiV16iUs", "", "avx512vbmi2") +TARGET_BUILTIN(__builtin_ia32_vpshl

[PATCH] D41557: [x86][icelake][vbmi2]

craig.topper added a comment. Add tests for -mavx512vbmi2 and -mno-avx512vbmi2 to test/Driver/x86-target-features.c Add a test for -mno-avx512bw also disabling avx512vbmi2 to test/Preprocessor/x86_target_features.c. Look for AVX512VBMINOAVX512BW for the existing test for avx512vbmi. Also add t

[PATCH] D41558: [x86][icelake][vnni]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D41558 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D41564: [x86][icelake][bitalg]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D41564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D41573: [x86][icelake][vpclmulqdq]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D41573 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D41557: [x86][icelake][vbmi2]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D41557 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D41582: [x86][icelake][gfni]

craig.topper added inline comments. Comment at: test/CodeGen/gfni-builtins.c:45 + +#ifdef AVX512 +__m512i test_mm512_gf2p8affineinv_epi64_epi8(__m512i A, __m512i B) { Doesn't the define have underscores around it? Repository: rC Clang https://reviews.llvm.or

[PATCH] D41582: [x86][icelake][gfni]

craig.topper added inline comments. Comment at: test/CodeGen/gfni-builtins.c:45 + +#ifdef AVX512 +__m512i test_mm512_gf2p8affineinv_epi64_epi8(__m512i A, __m512i B) { craig.topper wrote: > Doesn't the define have underscores around it? Oh its your own define. You

[PATCH] D41583: [x86][icelake][vaes]

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:573 setMMXLevel(Features, AMD3DNowAthlon, Enabled); } else if (Name == "aes") { if (Enabled) Shouldn't -aes imply -vaes? Repository: rC Clang https://reviews.llvm.org/D415

[PATCH] D41573: [x86][icelake][vpclmulqdq]

craig.topper requested changes to this revision. craig.topper added inline comments. This revision now requires changes to proceed. Comment at: lib/Basic/Targets/X86.cpp:577 } else if (Name == "pclmul") { if (Enabled) setSSELevel(Features, SSE2, Enabled); -

[PATCH] D41573: [x86][icelake][vpclmulqdq]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D41573 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D41583: [x86][icelake][vaes]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D41583 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D41582: [x86][icelake][gfni]

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D41582 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D40478: Added control flow architecture protection Flag

craig.topper added inline comments. Comment at: lib/CodeGen/CodeGenModule.cpp:501 + if (CodeGenOpts.CFProtectionReturn) { +Target.checkCFProtectionReturnSupported(getDiags()); +// Indicate that we want to instrument return control flow protection. Should

[PATCH] D41517: mmintrin.h documentation fixes and updates

craig.topper added inline comments. Comment at: lib/Headers/mmintrin.h:1292 /// -/// This intrinsic corresponds to the VXORPS / XORPS instruction. +/// This intrinsic corresponds to the XOR instruction. /// kromanova wrote: > craig.topper wrote: > > PXOR? >

[PATCH] D40478: Added control flow architecture protection Flag

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D40478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm

[PATCH] D41357: WIP: Fix Diagnostic layering, moving diagnostics out of Basic

craig.topper added inline comments. Comment at: lib/Basic/DiagnosticIDs.cpp:58 /// GetDiagInfo - Return the StaticDiagInfoRec entry for the specified DiagID, /// or null if the ID is invalid. This comment is out of date with the struct being renamed. ==

[PATCH] D41517: mmintrin.h documentation fixes and updates

craig.topper added inline comments. Comment at: lib/Headers/mmintrin.h:55 /// -/// This intrinsic corresponds to the VMOVD / MOVD instruction. +/// This intrinsic corresponds to the MOVD instruction. /// kromanova wrote: > I tried clang on Linux, x86_64, an

[PATCH] D41523: xmmintrin.h documentation fixes and updates

craig.topper added inline comments. Comment at: lib/Headers/xmmintrin.h:2199 /// -/// This intrinsic corresponds to the VPINSRW / PINSRW instruction. +/// This intrinsic corresponds to the PINSRW instruction. /// kromanova wrote: > craig.topper wrote: > > W

[PATCH] D41523: xmmintrin.h documentation fixes and updates

craig.topper added a comment. The builtins are tested in tests like test/CodeGen/sse-builtins.c https://reviews.llvm.org/D41523 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41517: mmintrin.h documentation fixes and updates

craig.topper added inline comments. Comment at: lib/Headers/mmintrin.h:1402 /// -/// This intrinsic corresponds to the VPSHUFLW / PSHUFLW instruction. +/// This intrinsic corresponds to the PSHUFLW instruction. /// dyung wrote: > craig.topper wrote: > > Thi

[PATCH] D43817: [x86] wbnoinvd intrinsic

craig.topper added inline comments. Comment at: docs/ClangCommandLineReference.rst:2359 +.. option:: -mwbnoinvd, -mno-wbnoinvd + Did you manually add these? This file is normally generated by a tool and should be in alphabetical order. Comme

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