[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/7] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

4vtomat wrote: > Thanks everyone! 😄 Is there anything still blocking us from merging this? Actually no, let me merge it later today, thanks! https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/106914 >From be771da74a7663d56cdf850c10b4daa47c087bcc Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 1 Sep 2024 09:35:34 -0700 Subject: [PATCH 1/2] [RISCV][VCIX] Precommit test --- llvm/test/CodeGen/RISCV/inlin

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/106914 >From aff3876f0d983413d5538929e11885111079e566 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 1 Sep 2024 09:35:34 -0700 Subject: [PATCH] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set R

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -317,38 +323,60 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( // Fixed-length RVV vectors are represented as scalable vectors in function // args/return and must be coerced from fixed vectors. -ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {

[clang] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (PR #115269)

https://github.com/4vtomat approved this pull request. LGTM, thanks! https://github.com/llvm/llvm-project/pull/115269 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/116597 >From 5addb1d33fc195b084a4869217d763abb1eef1af Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 18 Nov 2024 02:02:34 -0800 Subject: [PATCH 1/2] [clang][RISCV] Bump RVV intrinsic to version 1.0 The spec: ht

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

@@ -158,6 +158,7 @@ on support follow. ``Svinval`` Assembly Support ``Svnapot`` Assembly Support ``Svpbmt``Supported + ``Svukte``Supported 4vtomat wrote: I thought it's frozen, hasn't it? https://github.com/llvm/

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

4vtomat wrote: > Add ReleaseNote to Clang? Updated! https://github.com/llvm/llvm-project/pull/116597 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/115657 >From 0c95051b617be8fd242e317c442a1881d5f28034 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 5 Aug 2024 11:59:52 +0800 Subject: [PATCH 1/2] [RISCV] Support `svukte` extension This is the extension for "A

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

4vtomat wrote: > RISCVUsage.rst Updated! https://github.com/llvm/llvm-project/pull/115657 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

@@ -330,6 +329,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smctr``, ``experimental-ssctr`` LLVM implements the `1.0-rc3 specification `__.

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/116597 The spec: https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4 Also remove __riscv_v_intrinsic_overloading since it's no longer in spec, the overloading intrinsics should be also enabled wh

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/115657 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support `svukte` extension (PR #115657)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/115657 >From 0c95051b617be8fd242e317c442a1881d5f28034 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 5 Aug 2024 11:59:52 +0800 Subject: [PATCH 1/4] [RISCV] Support `svukte` extension This is the extension for "A

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -32,3 +36,39 @@ vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) { __riscv_vse32_v_i32m1(base, val, vl); return ret; } + +// CHECK-LLVM: define dso_local void @test_vls_no_cc(i128 noundef %arg.coerce) +// CHECK-LLVM-ABI-VLEN: define dso_loca

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

4vtomat wrote: > Is there discussion somewhere of why you need a command-line flag? > ABI-modifying flags tend to be dangerous to work with. It's hard to ensure > that all code is compiled with the same flags, and if the user messes up, the > compiler silently generates broken code. Yeah, it'

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -8031,6 +8034,28 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, CallingConv CCOld = fn->getCallConv(); Attr *CCAttr = getCCTypeAttr(S.Context, attr); + if (attr.getKind() == ParsedAttr::AT_RISCVVLSCC) { +// If the riscv_abi_vle

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From 1c8201daa6925cac510ff8751ffd79a6b95f2315 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/4] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [clang][RISCV] Remove unneeded RISCV tuple code (PR #121024)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/121024 These code are no longer needed because we've modeled tuple type using target extension type rather than structure of scalable vectors. >From 72401387483dd5839d09f508c1bc988325c5e456 Mon Sep 17 00:00:00 2001 Fr

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

4vtomat wrote: Update: 1. Handle struct of fixed-length vectors 2. Remove `-mriscv-abi-vlen=N` option https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listin

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -3013,6 +3013,7 @@ enum CXCallingConv { CXCallingConv_M68kRTD = 19, CXCallingConv_PreserveNone = 20, CXCallingConv_RISCVVectorCall = 21, + CXCallingConv_RISCVVLSCall = 22, 4vtomat wrote: Let me clarify this, do you mean using different calling conven

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -3013,6 +3013,7 @@ enum CXCallingConv { CXCallingConv_M68kRTD = 19, CXCallingConv_PreserveNone = 20, CXCallingConv_RISCVVectorCall = 21, + CXCallingConv_RISCVVLSCall = 22, 4vtomat wrote: I see, let me change it to this approach~ https://github.com/l

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, 4vtomat wrote: I see, let me change the case https://github.com/llvm/llvm-project/pull/126064

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, +unsigned LMULOffset) -> bool { +const FunctionDecl *FD = SemaRef.getCurFunctionDecl(); +

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/126064 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

https://github.com/4vtomat deleted https://github.com/llvm/llvm-project/pull/126064 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, 4vtomat wrote: wait I have a question, is lambda treated as a function or a variabl, the reason I make first character

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, +unsigned LMULOffset) -> bool { 4vtomat wrote: I think it's not lol https://gi

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, +unsigned LMULOffset) -> bool { +const FunctionDecl *FD = SemaRef.getCurFunctionDecl(); +

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, 4vtomat wrote: Agree, let me change it~ https://github.com/llvm/llvm-project/pull/126064 _

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, +unsigned LMULOffset) -> bool { +const FunctionDecl *FD = SemaRef.getCurFunctionDecl(); +

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

4vtomat wrote: > Is there a downside if we just recommend people > `__attribute__((riscv_vls_cc(MY_LIBRARY_VLEN)))`, then put > `-DMY_LIBRARY_VLEN=128` on the command-line? It's about the same complexity > as -mriscv-abi-vlen, and it's much more obvious that what you're doing is > fragile. A

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

4vtomat wrote: > Considering the define is guarded behind `if > (ISAInfo->hasExtension("zve32x"))`, this doesn't seem to implement: > [riscv-non-isa/rvv-intrinsic-doc#382](https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/382) I'll post another patch for this, thanks! https://github.com

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/116597 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] __riscv_v_intrinsic macro doesn't need zve32x (PR #117356)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/117356 This macro is used to check if compiler supports RVV intrinsics, so it should be defined no matter vector is enabled or not. Resolved https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/376 >From a29150c5

[clang] [clang][RISCV] Remove unneeded RISCV tuple code (PR #121024)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/121024 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -111,9 +115,51 @@ void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr, } void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { + unsigned ABIVLen; + switch (FI.getExtInfo().getCC()) { + default: +ABIVLen = 1; 4vtomat wrote: I see, ori

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -1953,7 +1953,7 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase { /// Extra information which affects how the function is called, like /// regparm and the calling convention. LLVM_PREFERRED_TYPE(CallingConv) -unsigned ExtInfo : 13; +

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -385,23 +580,50 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const { NumElts *= 8; break; default: -assert(VT->getVectorKind() == VectorKind::RVVFixedLengthData && +assert((VT->getVectorKind() == VectorKind::Generic || +VT->getVecto

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -385,23 +580,50 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const { NumElts *= 8; break; default: -assert(VT->getVectorKind() == VectorKind::RVVFixedLengthData && +assert((VT->getVectorKind() == VectorKind::Generic || +VT->getVecto

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -111,9 +115,51 @@ void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr, } void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { + unsigned ABIVLen; + switch (FI.getExtInfo().getCC()) { + default: +ABIVLen = 0; +break; + case CallingConv::CC_RISCVVL

[clang] [clang][RISCV] Rename variable name in SemaRISCV. NFC (PR #131261)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/131261 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

4vtomat wrote: Ping~ https://github.com/llvm/llvm-project/pull/126064 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Rename variable name in SemaRISCV. NFC (PR #131261)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/131261 None >From 9aa7f5bfd6afed1059cc53806b29d544105a8f8a Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Thu, 13 Mar 2025 19:57:29 -0700 Subject: [PATCH] [clang][RISCV] Rename variable name in SemaRISCV. NFC --- c

[clang] [clang][RISCV] Fix RUN line and rename test name for pr129995 (PR #132676)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/132676 ninja check-clang can not detect .cc suffix, so the typo is not detected. >From e7b0b4feae891046553a04ddbf17e550742db54c Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 23 Mar 2025 23:29:27 -0700 Subject:

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