https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/106914
>From be771da74a7663d56cdf850c10b4daa47c087bcc Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon...@sifive.com>
Date: Sun, 1 Sep 2024 09:35:34 -0700
Subject: [PATCH 1/2] [RISCV][VCIX] Precommit test
---
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 22 ++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
new file mode 100644
index 00000000000000..4ceb189ab6a46f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+; VCIX instructions can not reorder between each other.
+define void @test_reorder(<vscale x 1 x i64> %vreg) {
+; CHECK-LABEL: test_reorder:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: sf.vc.vv 3, 0, v8, v8
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT: sf.vc.iv 0, 0, v8, 0
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, <vscale x 1 x i64> %vreg, iXLen 0, iXLen 0)
+ call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{vcix_state}"(<vscale x 1 x i64> %vreg)
+ ret void
+}
>From 87bbba759587af6d9629317d40442070465bc841 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon...@sifive.com>
Date: Sun, 1 Sep 2024 09:39:44 -0700
Subject: [PATCH 2/2] [RISCV][VCIX] Add vcix_state to GNU inline assembly
register set
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 6 ++++++
llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 2 ++
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 4 ++++
llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll | 6 +++---
5 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index b89109e7725d44..235a9a092bed1d 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -44,7 +44,7 @@ ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf.vcix_state"
};
// clang-format on
return llvm::ArrayRef(GCCRegNames);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 701594c0fb05dc..690a4dcefb04b5 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -715,6 +715,12 @@ Register RISCVRegisterInfo::getFrameRegister(const
MachineFunction &MF) const {
return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
}
+StringRef RISCVRegisterInfo::getRegAsmName(MCRegister Reg) const {
+ if (Reg == RISCV::SF_VCIX_STATE)
+ return "sf.vcix_state";
+ return TargetRegisterInfo::getRegAsmName(Reg);
+}
+
const uint32_t *
RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
CallingConv::ID CC) const {
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 7e04e9154b524e..6186b3863fa589 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -102,6 +102,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
Register getFrameRegister(const MachineFunction &MF) const override;
+ StringRef getRegAsmName(MCRegister Reg) const override;
+
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 5725d8eda88ced..d9e02f640893d9 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -666,3 +666,7 @@ def SSP : RISCVReg<0, "ssp">;
// Dummy SiFive VCIX state register
def SF_VCIX_STATE : RISCVReg<0, "sf.vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add SF_VCIX_STATE)> {
+ let RegInfos = XLenRI;
+ let isAllocatable = 0;
+}
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
index 4ceb189ab6a46f..015b1bb2e6c5a7 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll
@@ -8,15 +8,15 @@
define void @test_reorder(<vscale x 1 x i64> %vreg) {
; CHECK-LABEL: test_reorder:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT: sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT: #APP
; CHECK-NEXT: sf.vc.vv 3, 0, v8, v8
; CHECK-EMPTY:
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma
-; CHECK-NEXT: sf.vc.iv 0, 0, v8, 0
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen
0, <vscale x 1 x i64> %vreg, iXLen 0, iXLen 0)
- call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{vcix_state}"(<vscale x 1 x i64> %vreg)
+ call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;",
"=r,^vr,~{memory},~{vl},~{sf.vcix_state}"(<vscale x 1 x i64> %vreg)
ret void
}
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