[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( OverloadedName += "_" + OverloadedSuffixStr.str(); // clang built-in function name, e.g. __builtin_rvv_vadd. - std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name); + std::string B

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

https://github.com/4vtomat deleted https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR, bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -416,8 +416,10 @@ class RVVIntrinsic { RVVTypePtr getOutputType() const { return OutputType; } const RVVTypes &getInputTypes() const { return InputTypes; } llvm::StringRef getBuiltinName() const { return BuiltinName; } - llvm::StringRef getName() const { return Name;

[clang] [Clang][RISCV][RVV Intrinsic] Fix codegen redundant intrinsic names (PR #77889)

4vtomat wrote: Since it only reduces about 160 of 54100 intrinsics generated, I have no opinion on this, just left the final decision to others~ But if this PR is finally decided to be merged, please add some comments around the code you added to explain, thanks! https://github.com/llvm/llvm-p

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -558,6 +558,12 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, "XTHeadVdot custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, "SiFive VCIX custo

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -476,6 +524,31 @@ class GetFTypeInfo { !eq(Scalar, f64) : "FPR64"); } +multiclass VPatVMACC info_pairs, ValueType vec_m1> { + foreach pair = info_pairs in { +defvar VdInfo = pair.Wti; +defvar Vs2Info = pair.Vti; +let Predicates = [

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/68295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Convert all floating point vector type operands to integer vector type (PR #69559)

@@ -450,6 +474,18 @@ multiclass VPatVC_XVV; + // Add another patterns for float type return value. + if !ne(wti.SEW, 8) then { +defvar wfti = !cast("VF"#wti.SEW#wti.LMul.MX); 4vtomat wrote: Yes, I'll add some tests for it~ https://github.com/llvm/llvm-proj

[clang] [RISCV] Convert all floating point vector type operands to integer vector type (PR #69559)

@@ -450,6 +474,18 @@ multiclass VPatVC_XVV; + // Add another patterns for float type return value. + if !ne(wti.SEW, 8) then { +defvar wfti = !cast("VF"#wti.SEW#wti.LMul.MX); 4vtomat wrote: Do you think test cases all of combination of vector type arguments

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

4vtomat wrote: ping https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

4vtomat wrote: ping https://github.com/llvm/llvm-project/pull/68296 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvfnrclipxfqf extensions (PR #68297)

4vtomat wrote: ping https://github.com/llvm/llvm-project/pull/68297 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

@@ -623,6 +623,11 @@ install( EXCLUDE_FROM_ALL COMPONENT riscv-resource-headers) +install( 4vtomat wrote: Yes, we are missing from add_header_target("riscv-resource-headers" "${riscv_files};${riscv_generated_files}"). I think we can just put sifive_vecto

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/66330 >From 8eb805beb037ba824fdf01dd8528b797a80de7ad Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Wed, 13 Sep 2023 22:59:30 -0700 Subject: [PATCH 1/3] [RISCV] Install sifive_vector.h to riscv-resource-headers --- cla

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat resolved https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/66860 None >From 041da389550eeb7865a91b8b0e723a04ed2f84e1 Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Tue, 19 Sep 2023 23:06:01 -0700 Subject: [PATCH] [RISCV] Fix wrong implication for zvknhb. --- clang/include/cla

[clang] [RISCV] Move sifive_files to riscv_files (PR #66872)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/66872 None >From 8de8e701d06f7c0e77d743a45db6f58f8bef9a0d Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Wed, 20 Sep 2023 01:23:54 -0700 Subject: [PATCH] [RISCV] Move sifive_files to riscv_files --- clang/lib/Headers/

[clang] [RISCV] Add missing V extensions for zvk-invalid-features.c (PR #66875)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/66875 If we don't include riscv_vector.h, even we add the target-feature, it still can't find the intrinsic interface. >From fdf29e4b484d6d0d01e772464052a4f26376ff98 Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Wed,

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb

[clang] [RISCV] Add missing V extensions for zvk-invalid-features.c (PR #66875)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/66875 >From f2321c370a71272b179ee596918205a226008bec Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Wed, 20 Sep 2023 01:44:33 -0700 Subject: [PATCH] [RISCV] Add missing V extensions for zvk-invalid-features.c If we don'

[clang] [RISCV] Add missing V extensions for zvk-invalid-features.c (PR #66875)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/66875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/66860 >From 3c28f7bace91dc4edd5e87b9f1a36d100cf38318 Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Tue, 19 Sep 2023 23:06:01 -0700 Subject: [PATCH] [RISCV] Fix wrong implication for zvknhb. --- clang/include/clang/Bas

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

4vtomat wrote: no change, just to re-trigger checks. https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/4vtomat resolved https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/4vtomat unresolved https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/66860 >From 3c28f7bace91dc4edd5e87b9f1a36d100cf38318 Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Tue, 19 Sep 2023 23:06:01 -0700 Subject: [PATCH 1/2] [RISCV] Fix wrong implication for zvknhb. --- clang/include/clang

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/4vtomat resolved https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Move sifive_files to riscv_files (PR #66872)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/66872 >From 531304c6d63183f28f836668d7116cb43ae60644 Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Wed, 20 Sep 2023 01:23:54 -0700 Subject: [PATCH] [RISCV] Move sifive_files to riscv_files --- clang/lib/Headers/CMakeL

[clang] [RISCV] Move sifive_files to riscv_files (PR #66872)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/66872 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb

[clang] [RISCV] Support floating point VCIX (PR #67094)

@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd, ; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0 ; CHECK-NEXT:ret entry: - tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1, %vd, %vs2, half %fs1, iXLen %vl) + tail call void @llvm.ris

[clang] [RISCV] Support floating point VCIX (PR #67094)

4vtomat wrote: > The target is support LLVM IR part only, we would like to prevent expose that > on the C intrinsic level if possible, because that's intentionally to expose > vector with unsigned integer only. Sure~ https://github.com/llvm/llvm-project/pull/67094

[clang] [RISCV][NFC] Move some common class/multiclass from riscv_vector.td to riscv_vector_common.td (PR #67587)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/67587 Since there are more vendor extensions that needs to implement custom intrinsics, it's useful to move some common usages to riscv_vector_common.td. >From 6f3575b70438a0529bd2505ccf55a87cca3eeefd Mon Sep 17 00:00

[clang] [RISCV][NFC] Move some common class/multiclass from riscv_vector.td to riscv_vector_common.td (PR #67587)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/67587 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/68296 Bfloat16 Matrix Multiply Accumulate Instruction https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf >From fc484770303cf50819e09dafd0f4f00760e67e3c Mon Sep 17 00:00:00

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/68296 >From fc484770303cf50819e09dafd0f4f00760e67e3c Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Wed, 4 Oct 2023 10:23:52 -0700 Subject: [PATCH 1/2] [RISCV] Support Xsfvfwmaccqqq extensions Bfloat16 Matrix Multipl

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

4vtomat wrote: ping https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -318,6 +345,16 @@ multiclass VPseudoVC_XVW { + def "Pseudo" # NAME # "_VV_" # mx : VPseudoTernaryNoMaskWithPolicy; 4vtomat wrote: Got it, I agree that td files should also follow the rule of 80 characters. https://github.com/llvm/llvm-project/pull/68295

[clang] [RISCV] Support Xsfvfnrclipxfqf extensions (PR #68297)

@@ -630,7 +630,7 @@ TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) { TEST(RiscvExtensionsHelp, CheckExtensions) { std::string ExpectedOutput = -R"(All available -march extensions for RISC-V + R"(All available -march extensions for RISC-V --

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/68296 >From e5a746541509727210e5e561ecb85607939ec0f4 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Wed, 4 Oct 2023 10:23:52 -0700 Subject: [PATCH 1/3] [RISCV] Support Xsfvfwmaccqqq extensions Bfloat16 Matrix Multipl

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

@@ -1013,7 +1013,6 @@ static const char *ImpliedExtsZvfhmin[] = {"zve32f"}; static const char *ImpliedExtsZvkn[] = {"zvkb", "zvkned", "zvknhb", "zvkt"}; static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"}; static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"}; -static c

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/66860 >From 3c28f7bace91dc4edd5e87b9f1a36d100cf38318 Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Tue, 19 Sep 2023 23:06:01 -0700 Subject: [PATCH 1/3] [RISCV] Fix wrong implication for zvknhb. --- clang/include/clang

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -103,3 +103,27 @@ let SupportOverloading = false in { defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3], UseGPR=0>; } } + +multiclass RVVVQMACCBuiltinSet> suffixes_prototypes> { + let OverloadedName = NAME, + Name = NAME, + HasMasked

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -178,6 +178,19 @@ multiclass CustomSiFiveVCIX; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr> +: RVInstVCCustom2 { + let vm = 1; + let funct6_lo2 = funct6{1-0}; +} +} + +multiclass CustomSi

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \ +# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN:| FileCheck %s --check-

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/68295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/68296 >From e5a746541509727210e5e561ecb85607939ec0f4 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Wed, 4 Oct 2023 10:23:52 -0700 Subject: [PATCH 1/4] [RISCV] Support Xsfvfwmaccqqq extensions Bfloat16 Matrix Multipl

[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)

@@ -178,6 +178,19 @@ multiclass CustomSiFiveVCIX; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr> +: RVInstVCCustom2 { + let vm = 1; + let funct6_lo2 = funct6{1-0}; +} +} + +multiclass CustomSi

[clang] Remove experimental from Vector Crypto extensions (PR #69000)

4vtomat wrote: > Thanks for the patch, some very quick feedback and I'd highlight the first > bullet as the most important, as this is potentially a blocker for graduating > these extensions from experimental. > > * My big concern with this would be the intrinsics - could you please comment >

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat review_requested https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/66330: None >From 8eb805beb037ba824fdf01dd8528b797a80de7ad Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Wed, 13 Sep 2023 22:59:30 -0700 Subject: [PATCH] [RISCV] Install sifive_vector.h to riscv-resource-headers ---

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat unlabeled https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat labeled https://github.com/llvm/llvm-project/pull/66330 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/66330: >From 8eb805beb037ba824fdf01dd8528b797a80de7ad Mon Sep 17 00:00:00 2001 From: 4vtomat Date: Wed, 13 Sep 2023 22:59:30 -0700 Subject: [PATCH 1/2] [RISCV] Install sifive_vector.h to riscv-resource-headers --- cl

[clang] [RISCV] Install sifive_vector.h to riscv-resource-headers (PR #66330)

@@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s +// REQUIRES: riscv-registered-target + +// expected-no-diagnostics + +#include 4vtomat wrote: Lit test is run before install, how can we check it's properly installed? https://github.com

[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

4vtomat wrote: Rebase https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Fix typo of vector crypto in SemaRISCV.cpp. NFC (PR #106485)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/106485 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -317,38 +323,45 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( // Fixed-length RVV vectors are represented as scalable vectors in function // args/return and must be coerced from fixed vectors. -ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames() const { "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", // CSRs - "fflags", "frm", "vtype", "vl", "vxsat", "vxrm" + "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Add missing `zvfbfmin` to `vget_v` intrinsic (PR #102149)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/102149 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][clang] Remove bfloat base type in non-zvfbfmin vcreate (PR #102146)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/102146 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -754,6 +754,17 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; +def FeatureStdExtZvbc32e +: RISCVExperimentalExtensio

[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

4vtomat wrote: > FYI, the example code you shown doesn't compile anymore: > https://godbolt.org/z/ooTWEGejf > > This feature is quite important, without it we can't compile in RVV by > default in a lot of libraries, e.g. simdutf, flac, ... I guess it should be `__attribute__((target("arch=+zv

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

4vtomat wrote: > Could you give few more word on the description to mention we missed that in > the vector crpyto intrinsic proposal, and it's fixing but rather than > incompatible/breaking change for the intrinsic API? Updated description. We are missing `vcpop.v` in the rvv_intrinsic_doc, so

[clang] [clang][RISCV] Remove unneeded overloaded suffix for vcreate (PR #89241)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/89241 Since `vcreate` doesn't support overload, we can remove it. >From a29cda00de03552529b510eda427804f822278e6 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Thu, 18 Apr 2024 07:29:42 -0700 Subject: [PATCH] [clang

[clang] [clang][RISCV] Remove unneeded overloaded suffix for vcreate (PR #89241)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/89241 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)

4vtomat wrote: Oh, I forgot to remove them. Or do you think they should be moved to bfloat folder to make them consistent? https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[clang] [ASTContext] Make the end of the switch case unreachable in `encodeTypeForFunctionPointerAuth` (PR #99763)

https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/99763 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/100346 This patch adds a function attribute `riscv_vls_cc` for RISCV VLS calling convention which takes 0 or 1 argument, the argument is the `ABI_VLEN` which is the `VLEN` for passing the fixed-vector arguments, it wrap

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/100346 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From dc4d11d0e9665f42b27de4bfb73c9756b007518d Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/2] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -2281,6 +2282,9 @@ bool LLParser::parseOptionalCallingConv(unsigned &CC) { case lltok::kw_riscv_vector_cc: CC = CallingConv::RISCV_VectorCall; break; + case lltok::kw_riscv_vls_cc: +CC = CallingConv::RISCV_VLSCall; 4vtomat wrote: Done! https

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From dc4d11d0e9665f42b27de4bfb73c9756b007518d Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/3] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -608,6 +608,9 @@ class CGFunctionInfo final /// Log 2 of the maximum vector width. unsigned MaxVectorWidth : 4; + /// Log2 of ABI_VLEN used in RISCV VLS calling convention. + unsigned Log2RISCVABIVLen : 4; 4vtomat wrote: Yes, we need 5 bits, thanks f

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -1333,6 +1333,15 @@ def Experimental : SubtargetFeature<"experimental", "HasExperimental", "true", "Experimental intrinsics">; +def FeatureABIVLen32B 4vtomat wrote: Yeah, that's a good idea since the backend doesn't use them~ http

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/100346 >From 15161b0b7637d52b6285624a4bf9f52a6664082c Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Sun, 21 Jul 2024 09:49:11 -0700 Subject: [PATCH 1/4] [RISCV][VLS] Support RISCV VLS calling convention This patch a

[clang] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs (PR #101046)

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/101046 None >From 1d756559b956f24d144c6819d264df062ec7d2cb Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 29 Jul 2024 10:44:05 -0700 Subject: [PATCH] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs

[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)

@@ -4768,6 +4768,15 @@ static void handleCallConvAttr(Sema &S, Decl *D, const ParsedAttr &AL) { case ParsedAttr::AT_RISCVVectorCC: D->addAttr(::new (S.Context) RISCVVectorCCAttr(S.Context, AL)); return; + case ParsedAttr::AT_RISCVVLSCC: { +// If the riscv_abi_vl

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