================
@@ -476,6 +524,31 @@ class GetFTypeInfo<int Sew> {
!eq(Scalar, f64) : "FPR64");
}
+multiclass VPatVMACC<string intrinsic, string instruction, string kind,
+ list<VTypeInfoToWide> info_pairs, ValueType vec_m1> {
+ foreach pair = info_pairs in {
+ defvar VdInfo = pair.Wti;
+ defvar Vs2Info = pair.Vti;
+ let Predicates = [HasVInstructions] in
+ def : VPatTernaryNoMaskWithPolicy<"int_riscv_sf_" # intrinsic,
+ "Pseudo" # instruction, kind,
VdInfo.Vector,
+ vec_m1, Vs2Info.Vector,
+ Vs2Info.Log2SEW, Vs2Info.LMul,
+ VdInfo.RegClass, VR, Vs2Info.RegClass>;
+ }
+}
+
+defset list<VTypeInfoToWide> VQMACCInfoPairs = {
+ def : VTypeInfoToWide<VI8M1, VI32M1>;
+ def : VTypeInfoToWide<VI8M2, VI32M2>;
+ def : VTypeInfoToWide<VI8M4, VI32M4>;
+ def : VTypeInfoToWide<VI8M8, VI32M8>;
+}
+
+multiclass VPatVQMACC<string intrinsic, string instruction, string kind> {
+ defm : VPatVMACC<intrinsic, instruction, kind, VQMACCInfoPairs, vint8m1_t>;
----------------
4vtomat wrote:
Sure~
https://github.com/llvm/llvm-project/pull/68295
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