@@ -19108,6 +19108,21 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
/*ReturnType=*/Op0->getType(), CGM.getHLSLRuntime().getStepIntrinsic(),
ArrayRef{Op0, Op1}, nullptr, "hlsl.step");
}
+ case Builtin::BI__builtin_hlsl_wave_active_any_true: {
+Int
https://github.com/V-FEXrt created
https://github.com/llvm/llvm-project/pull/115902
Resolves https://github.com/llvm/llvm-project/issues/99160
- [x] Implement `WaveActiveAnyTrue` clang builtin,
- [x] Link `WaveActiveAnyTrue` clang builtin with `hlsl_intrinsics.h`
- [x] Add sema checks for `W
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/3] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o
- | FileCheck %s
V-FEXrt wrote:
do you mean `-mtriple=spirv32v1.5-unknown-unknown`? I couldn't get any other
variant of the `spirv` part to work
https://github.com
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/4] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify
+
+bool test_too_few_arg() {
+ return __builtin_hlsl_wave_active_any_true();
+ // expected-error@-1 {{too few arguments to functi
https://github.com/V-FEXrt edited
https://github.com/llvm/llvm-project/pull/115902
___
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@@ -93,6 +93,7 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/5] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/6] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
@@ -17,12 +17,10 @@ double test_int_builtin(double p0) {
double2 test_int_builtin_2(double2 p0) {
return __builtin_hlsl_elementwise_firstbithigh(p0);
- // expected-error@-1 {{1st argument must be a vector of integers
- // (was 'double2' (aka 'vector'))}}
+ // expected-err
@@ -1949,24 +1949,36 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
+const SPIRVType *ResType,
+
https://github.com/V-FEXrt edited
https://github.com/llvm/llvm-project/pull/115902
___
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https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -2826,6 +2843,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
+ case Intrin
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/15] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/18] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -2206,6 +2206,15 @@ float4 trunc(float4);
// Wave* builtins
//===--===//
+/// \brief Returns true if the expression is true in any active lane in the
+/// current wave.
+///
+/// \param Val The boolean exp
@@ -1949,6 +1952,23 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
+ const SPIRVType
*ResType,
+
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/16] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -1949,24 +1955,48 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -2826,6 +2843,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
+ case Intrin
https://github.com/V-FEXrt created
https://github.com/llvm/llvm-project/pull/116858
Closes https://github.com/llvm/llvm-project/issues/99116
- [x] Implement firstbitlow clang builtin,
- [x] Link firstbitlow clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for firstbitlow to CheckHL
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -finclude-default-header -fnative-half-type -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -finclude-default-header
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/12] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/11] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/9] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/11] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/8] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 1/8] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/in
@@ -93,6 +93,7 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32
@@ -2848,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
case Intrinsic::spv_wave_active_countbits:
return selectWaveActiveCountBits(ResVReg, ResType, I);
case Intrinsic::spv_wave_any:
-return selectWaveActiveAnyTrue(ResVReg, ResType,
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/13] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/117245
>From 1156d98a0ba25a92b4edbacb7c17e5ad6bb2b522 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 21 Nov 2024 08:42:31 -0700
Subject: [PATCH 1/2] [HLSL] Implement WaveActiveAllTrue Intrinsic
---
clang/in
@@ -0,0 +1,21 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
@@ -0,0 +1,219 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: [[glsl_450_ext:%.+]] = OpExtInstImport "GLSL.std.4
https://github.com/V-FEXrt edited
https://github.com/llvm/llvm-project/pull/116858
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@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/117245
>From 1156d98a0ba25a92b4edbacb7c17e5ad6bb2b522 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 21 Nov 2024 08:42:31 -0700
Subject: [PATCH 1/2] [HLSL] Implement WaveActiveAllTrue Intrinsic
---
clang/in
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From a63e05d2e090edf7834fb62296bccd071a8e38b8 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/7] [HLSL] Implement elementwise firstbitlow builtin
---
clan
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/18] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/115902
>From 845256b2ed971a4e42f7f871e8b51e711486261a Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Mon, 11 Nov 2024 16:34:23 -0700
Subject: [PATCH 01/19] [HLSL] Implement WaveActiveAnyTrue intrinsic
---
clang/
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From eeb864972c48625fa56b96e6b018affe04d84e00 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/4] [HLSL] Implement elementwise firstbitlow builtin
---
clan
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From eeb864972c48625fa56b96e6b018affe04d84e00 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/5] [HLSL] Implement elementwise firstbitlow builtin
---
clan
https://github.com/V-FEXrt created
https://github.com/llvm/llvm-project/pull/117245
Resolves https://github.com/llvm/llvm-project/issues/99161
- [x] Implement `WaveActiveAllTrue` clang builtin,
- [x] Link `WaveActiveAllTrue` clang builtin with `hlsl_intrinsics.h`
- [x] Add sema checks for `W
@@ -861,6 +861,14 @@ def CreateHandleFromBinding : DXILOp<217,
createHandleFromBinding> {
let stages = [Stages];
}
+def WaveActiveAllTrue : DXILOp<334, waveAllTrue> {
V-FEXrt wrote:
Crossed wires with SPIRV. This should be 114 not 334
https://github.com/
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From eeb864972c48625fa56b96e6b018affe04d84e00 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/6] [HLSL] Implement elementwise firstbitlow builtin
---
clan
@@ -0,0 +1,168 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: [[glsl_450_ext:%.+]] = OpExtInstImport "GLSL.std.4
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
https://github.com/V-FEXrt edited
https://github.com/llvm/llvm-project/pull/122981
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@@ -0,0 +1,46 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-defaul
@@ -0,0 +1,46 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-defaul
@@ -0,0 +1,133 @@
+//=== ParseHLSLRootSignatureTest.cpp - Parse Root Signature tests
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,153 @@
+#include "clang/Parse/ParseHLSLRootSignature.h"
+
+namespace llvm {
+namespace hlsl {
+namespace root_signature {
+
+// Lexer Definitions
+
+static bool IsNumberChar(char C) {
+ // TODO: extend for float support with or without hexadecimal/exponent
@@ -0,0 +1,133 @@
+//=== ParseHLSLRootSignatureTest.cpp - Parse Root Signature tests
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,133 @@
+//=== ParseHLSLRootSignatureTest.cpp - Parse Root Signature tests
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/V-FEXrt approved this pull request.
Personally happy with the code at a high level, though it would be best to have
someone with domain knowledge also approve
https://github.com/llvm/llvm-project/pull/122981
___
cfe-commits mailing
@@ -0,0 +1,153 @@
+#include "clang/Parse/ParseHLSLRootSignature.h"
+
+namespace llvm {
+namespace hlsl {
+namespace root_signature {
+
+// Lexer Definitions
+
+static bool IsNumberChar(char C) {
+ // TODO: extend for float support with or without hexadecimal/exponent
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -0,0 +1,130 @@
+//=== ParseHLSLRootSignatureTest.cpp - Parse Root Signature tests
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,152 @@
+#include "clang/Parse/ParseHLSLRootSignature.h"
+
+namespace llvm {
+namespace hlsl {
+namespace root_signature {
+
+// Lexer Definitions
+
+static bool IsPreprocessorNumberChar(char C) {
+ // TODO: extend for float support with or without hexadecimal/exponent
@@ -0,0 +1,152 @@
+#include "clang/Parse/ParseHLSLRootSignature.h"
+
+namespace llvm {
+namespace hlsl {
+namespace root_signature {
+
+// Lexer Definitions
+
+static bool IsPreprocessorNumberChar(char C) {
+ // TODO: extend for float support with or without hexadecimal/exponent
@@ -0,0 +1,152 @@
+#include "clang/Parse/ParseHLSLRootSignature.h"
+
+namespace llvm {
+namespace hlsl {
+namespace root_signature {
+
+// Lexer Definitions
+
+static bool IsPreprocessorNumberChar(char C) {
+ // TODO: extend for float support with or without hexadecimal/exponent
@@ -0,0 +1,152 @@
+#include "clang/Parse/ParseHLSLRootSignature.h"
+
+namespace llvm {
+namespace hlsl {
+namespace root_signature {
+
+// Lexer Definitions
+
+static bool IsPreprocessorNumberChar(char C) {
+ // TODO: extend for float support with or without hexadecimal/exponent
https://github.com/V-FEXrt edited
https://github.com/llvm/llvm-project/pull/122981
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@@ -0,0 +1,152 @@
+#include "clang/Parse/ParseHLSLRootSignature.h"
+
+namespace llvm {
+namespace hlsl {
+namespace root_signature {
+
+// Lexer Definitions
+
+static bool IsPreprocessorNumberChar(char C) {
+ // TODO: extend for float support with or without hexadecimal/exponent
@@ -0,0 +1,130 @@
+//=== ParseHLSLRootSignatureTest.cpp - Parse Root Signature tests
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
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@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
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@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -6358,3 +6359,89 @@ RValue CodeGenFunction::EmitPseudoObjectRValue(const
PseudoObjectExpr *E,
LValue CodeGenFunction::EmitPseudoObjectLValue(const PseudoObjectExpr *E) {
return emitPseudoObjectExpr(*this, E, true, AggValueSlot::ignored()).LV;
}
+
+void CodeGenFunction::Fl
@@ -2412,6 +2412,102 @@ bool SemaHLSL::CheckCompatibleParameterABI(FunctionDecl
*New,
return HadError;
}
+// Generally follows PerformScalarCast, with cases reordered for
+// clarity of what types are supported
+bool SemaHLSL::CanPerformScalarCast(QualType SrcTy, QualType D
https://github.com/V-FEXrt approved this pull request.
https://github.com/llvm/llvm-project/pull/122977
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V-FEXrt wrote:
Yeah I figured they weren't broken by me but I had assumed I needed all green
before merging so was waiting for the fix to make it into main but happy to
merge as is if that's acceptable
https://github.com/llvm/llvm-project/pull/116858
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https://github.com/llvm/llvm-project/pull/123141
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@@ -1730,6 +1731,16 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr(
}
#endif
+ // HLSL initialization lists in the AST are an expansion which can contain
+ // side-effecting expressions wrapped in opaque value expressions. To
properly
+ // emit these we need to
@@ -3173,9 +3173,18 @@ bool SemaHLSL::TransformInitList(const InitializedEntity
&Entity,
BuildFlattenedTypeList(InitTy, DestTypes);
llvm::SmallVector ArgExprs;
- for (Expr *Arg : Init->inits())
-if (!BuildInitializerList(SemaRef, Ctx, Arg, ArgExprs, DestTypes))
+ fo
https://github.com/V-FEXrt approved this pull request.
https://github.com/llvm/llvm-project/pull/118992
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