[PATCH] D60539: Add -std=c++14 language standard option to tests that require C++14 default

amyk created this revision. amyk added reviewers: ilya-biryukov, sammccall, ioeric, hokein, akyrtzi, yvvan. amyk added projects: clang, LLVM. Herald added subscribers: kadircet, arphaman, dexonsmith, jkorous. On one of the platforms that we build on, we build with the CMake macro, `CLANG_DEFAULT_

[PATCH] D80294: Add support for vmsumudm

amyk added a comment. I think this overall looks good, but just curious, why was the builtin support removed? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80294/new/ https://reviews.llvm.org/D80294 ___ cfe-commits mailing list cfe-commits

[PATCH] D80294: Add support for vmsumudm

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1365 +// Vector Multiply-Sum +def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm, Maybe we can put this definition near the other VMSUM instructions? Since it's

[PATCH] D80294: Add support for vmsumudm

amyk accepted this revision. amyk added a comment. Thanks for explaining. This LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80294/new/ https://reviews.llvm.org/D80294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://li

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp:653 // On P7, P8 or P9 we have a cache line size of 128. unsigned Directive = ST->getCPUDirective(); Should this comment be updated to include P10 as well? Reposi

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

amyk accepted this revision. amyk added a comment. I think this looks good aside from the comments I had. Comment at: llvm/lib/Target/PowerPC/PPCSubtarget.h:142 bool IsISA3_0; + bool IsISA3_1; bool UseLongCalls; Missing `IsISA3_1 = false;` in PPCSubtarge

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

amyk accepted this revision. amyk added a comment. This LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D80020 ___ cfe-commits mailing list cfe-commits@lists.llv

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

amyk accepted this revision. amyk added a comment. This revision is now accepted and ready to land. This LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80758/new/ https://reviews.llvm.org/D80758 _

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: lei, stefanp, nemanjai, saghir, power-llvm-team. Herald added subscribers: llvm-commits, cfe-commits, shchenz, hiraditya. Herald added projects: clang, LLVM. amyk updated this revision to Diff 267648. amyk added a comment. Updated a typo within the

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

amyk updated this revision to Diff 267648. amyk added a comment. Updated a typo within the comment in `llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80935/new/ https://reviews.llvm.org/D80935 Files

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: nemanjai, lei, stefanp, saghir, power-llvm-team, hfinkel. amyk added a project: LLVM. Herald added subscribers: shchenz, hiraditya. Herald added a project: clang. This patch implements builtins for the following prototypes: unsigned long long __

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: nemanjai, lei, stefanp, saghir, power-llvm-team. amyk added a project: LLVM. Herald added subscribers: shchenz, hiraditya. Herald added a project: clang. This patch implements builtins for the following prototypes: unsigned long long __builtin_c

[PATCH] D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.

This revision was automatically updated to reflect the committed changes. Closed by commit rGfc5530862870: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to… (authored by amyk). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests

amyk marked an inline comment as done. amyk added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:28 + return vec_mul(vulla, vullb); +} + bsaleil wrote: > Are the tests for `vec_mul` with `v4i32` missing ? I should probably reword the de

[PATCH] D83955: [PowerPC][Power10] Implementation of 128-bit Binary Vector Multiply builtins

amyk requested changes to this revision. amyk added inline comments. This revision now requires changes to proceed. Comment at: clang/lib/Headers/altivec.h:5472 + +#ifdef _ARCH_PWR10 +static __inline__ vector unsigned __int128 __ATTRS_o_ai Please use `__POWER10_V

[PATCH] D83516: [PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests

This revision was automatically updated to reflect the committed changes. Closed by commit rGc2735635523d: [PowerPC][Power10] Add 128-bit Binary Integer Operation instruction definitions… (authored by Conanap, committed by amyk). Changed prior to commit: https://reviews.llvm.org/D83516?vs=27744

[PATCH] D81442: [PowerPC] Add clang options to control MMA support

amyk accepted this revision. amyk added a comment. I think overall it LGTM. Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:44 // Do not support QPX (Quad Processing eXtension), SPE (Signal Processing // Engine), prefixed instructions on Power 9, PC relative mem ops,

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added a comment. Please also change the function names. Comment at: clang/lib/Headers/altivec.h:17151 + +/* vs[l | r | raq] */ +static __inline__ vector unsigned __int128 __ATTRS_o_ai Actually, sorry, I think this comment should be the following instead: `

[PATCH] D83722: [PowerPC] Add options to control paired vector memops support

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPC.td:243 + "32Byte load and store instructions", + [FeatureISA3_0]>; Is this supposed to be `FeatureISA3_1`? Comment at: llvm/lib/Target/Pow

[PATCH] D84277: [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments.

amyk created this revision. amyk added reviewers: power-llvm-team, nemanjai, PowerPC, rzurob. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. Previously, the vins*vlx instructions were incorrectly defined with i64 as the second argument. This patches fixe

[PATCH] D84291: [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins Implementation

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, nemanjai, rzurob. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. The implementation of the `xvtlsbb` builtins/intrinsics were not correct as the intrinsics previously used `i1` as

[PATCH] D84291: [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins Implementation

This revision was automatically updated to reflect the committed changes. Closed by commit rG08b4a50e39d8: [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins Implementation (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D84291?vs=279698&id=279897#toc Reposito

[PATCH] D84277: [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments.

This revision was automatically updated to reflect the committed changes. Closed by commit rG5f110273954a: [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments. (authored by amyk). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84277/new

[PATCH] D84382: [PowerPC][Power10] Cleanup p10vector clang test

amyk accepted this revision. amyk added a comment. LGTM as well. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84382/new/ https://reviews.llvm.org/D84382 ___ cfe-commits mailing list cfe-commits@lists.

[PATCH] D83955: [PowerPC][Power10] Implementation of 128-bit Binary Vector Multiply builtins

amyk accepted this revision as: amyk. amyk added a comment. I think this LGTM now. The file is already upstream, so your tests will need to be added to that file. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83955/new/ https://reviews.llvm.org/D8

[PATCH] D84197: [PowerPC][Power10] 128-bit Vector String Isolate instruction definitions and MC Tests

amyk requested changes to this revision. amyk added a comment. This revision now requires changes to proceed. Could you please add back the MC tests for the rightmost load/store instructions, and then add the vector string isolate tests to the end of the file? Repository: rG LLVM Github Mono

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added a comment. I realize it may be possible to open code these, as these functions already exist in altivec.h. Could you look into if this is the case? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk added a comment. The `llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll` file actually exists, and there is a BE RUN line in it. I realized I didn't rebase this diff to my previous patch that introduced it. Thus on the commit, I will append my tests to that file. Repository: rG LLVM Git

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

This revision was automatically updated to reflect the committed changes. Closed by commit rG74790a5dde9a: [PowerPC] Implement Truncate and Store VSX Vector Builtins (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D82467?vs=276881&id=280634#toc Repository: rG LLVM Githu

[PATCH] D83722: [PowerPC] Add options to control paired vector memops support

amyk accepted this revision as: amyk. amyk added a comment. This revision is now accepted and ready to land. This LGTM. Thanks for addressing the comments Baptiste. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83722/new/ https://reviews.llvm.org/D

[PATCH] D82726: [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

amyk added a comment. I will need to update this patch to remove the instruction definition and MC tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82726/new/ https://reviews.llvm.org/D82726 ___ c

[PATCH] D82725: [PowerPC][Power10] Implement Move to VSR Mask builtins in LLVM/Clang

amyk added a comment. I will need to update this patch to remove the instruction definition and MC tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82725/new/ https://reviews.llvm.org/D82725 ___ c

[PATCH] D82675: [PowerPC][Power10] Implement Vector Extract Mask builtins in LLVM/Clang

amyk added a comment. I will need to update this patch to remove the instruction definition and MC tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82675/new/ https://reviews.llvm.org/D82675 ___ c

[PATCH] D82727: [PowerPC][Power10] Implement Vector Expand Mask builtins in LLVM/Clang

amyk added a comment. I will need to update this patch to remove the instruction definition and MC tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 ___ c

[PATCH] D82609: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk updated this revision to Diff 281080. amyk added a comment. Addressed the following comments: - updated CHECK lines to check for the full intrinsic call - updated indentation Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82609/new/ https://re

[PATCH] D82675: [PowerPC] Implement Vector Extract Mask builtins in LLVM/Clang

amyk updated this revision to Diff 281107. amyk added a comment. - Rebased patch - Updated patch to remove instruction definitions and MC tests Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82675/new/ https://reviews.llvm.org/D82675 Files: clang

[PATCH] D84197: [PowerPC][Power10] 128-bit Vector String Isolate instruction definitions and MC Tests

amyk accepted this revision. amyk added a comment. This revision is now accepted and ready to land. Thanks for recovering the tests. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84197/new/ https://reviews.llvm.org/D84197 ___

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. Could we also elaborate in the description on how we are utilizing the new load instructions for zero extend case but not the sign extend case? Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14197 + + SDValue LoadOps[] = {LD->getChain(), LD->getB

[PATCH] D77542: [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint

amyk added inline comments. Comment at: clang/lib/Basic/Targets/PPC.h:277 break; case 'Q': // Memory operand that is an offset from a register (it is // usually better to use `m' or `es' in asm statements) Just curious, but does this ca

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang

amyk updated this revision to Diff 268331. amyk retitled this revision from "[PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins in LLVM/Clang" to "[PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang". amyk added a comment. Addressed r

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang

amyk updated this revision to Diff 268470. amyk added a comment. Revert back to the initial implementation of the patch. Thanks Nemanja for clarifying. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80941/new/ https://reviews.llvm.org/D80941 Files

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

amyk added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80970/new/ https://reviews.llvm.org/D80970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-b

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

amyk added a comment. Ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80935/new/ https://reviews.llvm.org/D80935 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-b

[PATCH] D81707: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: saghir, nemanjai, power-llvm-team, PowerPC, hfinkel. amyk added projects: clang, LLVM, PowerPC. Herald added subscribers: shchenz, hiraditya. This patch implements builtins for the following prototypes: vector signed char vec_clrl (vector signed

[PATCH] D81774: [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang

amyk created this revision. amyk added reviewers: nemanjai, saghir, power-llvm-team, PowerPC, hfinkel. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. This patch implements builtins for the following prototypes for the VSX Permute Control Vector Generate w

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

amyk added inline comments. Comment at: clang/test/Parser/p10-vector-bool-128.c:1 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feat

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

amyk accepted this revision as: amyk. amyk added a comment. This revision is now accepted and ready to land. This LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83364/new/ https://reviews.llvm.org/D83364

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk marked 2 inline comments as done. amyk added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:79 +vector signed int test_vec_dive_si(void) { + // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32> + // CHECK-NEXT: ret <4 x i32> lei wrote: >

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk created this revision. amyk added reviewers: PowerPC, power-llvm-team, nemanjai, lei. amyk added projects: LLVM, PowerPC, clang. Herald added a subscriber: shchenz. This patch implements custom codegen for the `vec_replace_elt` and `vec_replace_unaligned` builtins. These builtins map to the

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk marked 2 inline comments as done. amyk added inline comments. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:339 +BUILTIN(__builtin_altivec_vec_replace_elt, "V4UiV4UiULLiIi", "t") +BUILTIN(__builtin_altivec_vec_replace_unaligned, "V4UiV4UiULLiIi", "t") -

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 276804. amyk added a comment. Updated for clang format changes. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/H

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk marked 3 inline comments as done. amyk added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14273 +// The third argument to vec_replace_elt will be emitted to either +// the vinsw or vinsd instruction. It must be a compile time constant. +ConstantIn

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 276844. amyk added a comment. Address review comments - update comments - pull out common code Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 Files: clang/include/clan

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

This revision was automatically updated to reflect the committed changes. Closed by commit rG5ffec4672028: [PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost… (authored by Conanap, committed by amyk). Changed prior to commit: https://reviews.llvm.org/D83364?vs=2765

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 276853. amyk added a comment. Fix assignment of variable. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Co

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk requested changes to this revision. amyk added a comment. This revision now requires changes to proceed. This will need to be rebased against your 2608 instruction definitions patch. But yes, I believe you are missing the clang and llc test case for this patch. Requesting changes due to mis

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk updated this revision to Diff 276881. amyk added a comment. Rebased patch, and addressed review comments of having a single `CHECK`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82467/new/ https://reviews.llvm.org/D82467 Files: clang/lib/H

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. Please update this patch to remove the instruction defs and MC tests. Also, you can update the patch to put your backend llc tests in the file I've introduced in: https://reviews.llvm.org/D82467 Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:14

[PATCH] D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.

amyk updated this revision to Diff 277153. amyk retitled this revision from "[PowerPC][Power10] Fix the VINSW instruction to have an i32 argument." to "[PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.". amyk edited the summary of this revision. amyk

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG62f5ba624bfb: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D82431?vs=274667&id=277646#toc Repository: rG

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: clang/lib/Headers/altivec.h:17151 + +/* vector shifts for quadwords */ +/* vs[l | r | raq] */ I think we can remove `/* vector shifts for quadwords */`. Then, we can add a new line after `/* vs[l | r | raq] */` for consist

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk added a comment. I think the patterns for the load instructions may have accidentally been deleted. Please add them back to the patch. Thank you. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: clang/lib/Headers/altivec.h:17153 +/* vs[l | r | raq] */ +static __inline__ vector unsigned __int128 __ATTRS_o_ai +vec_slq(vector unsigned __int128 __a, vector unsigned __int128 __b) { I believe there are supposed to be `si

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

amyk updated this revision to Diff 278019. amyk edited the summary of this revision. amyk added a parent revision: D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.. amyk added a comment. Corrected the patch as it previously caused errors to t

[PATCH] D83516: [PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests

amyk accepted this revision. amyk added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83516/new/ https://reviews.llvm.org/D83516 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

amyk marked an inline comment as done. amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:47 + let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops, + IsISA3_1]; lei wrote: > Are `P

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rGc45c1611303b: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in… (authored by amyk). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80935

[PATCH] D81707: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rGcc95635b1bf2: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in… (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D81707?vs=270283&id=272281#toc Repository

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

amyk accepted this revision as: amyk. amyk added a comment. Other than Lei's concerns, personally I think this looks good to me. Comment at: clang/test/Parser/p10-vector-bool-128.c:6 +// RUN:-target-feature +power10-vector -fsyntax-only -verify %s +// expected-no-di

[PATCH] D81774: [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG19df9e2959cf: [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D81774?vs=270535&id=272589#toc Repository: r

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: nemanjai, lei, saghir, hfinkel, power-llvm-team, PowerPC. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. This patch implements builtins for the following prototypes: int vec_test_lsbb_all_ones (vector un

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, saghir, nemanjai, hfinkel. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. This patch implements the following function prototypes for the truncate and store VSX Vector instruction

[PATCH] D80941: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rGd82f26cc4bc7: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit… (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D80941?vs=268470&id=273156#toc Reposit

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

amyk requested changes to this revision. amyk added a comment. This revision now requires changes to proceed. I have a few comments from the last time we looked at this together. Just also FYI that the backend tests will be apart of the `p10-vsx-builtins.ll` file introduced in https://reviews.ll

[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, Conanap, saghir, nemanjai, lei. amyk added projects: LLVM, clang, PowerPC. Herald added a subscriber: shchenz. This patch aims to add the following function prototypes: vector signed int vec_mod (vector signed int a, ve

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

amyk added a comment. Talked to Anil, and will address his nit comments on the commit and disregard the comment about the test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80970/new/ https://reviews.llvm.org/D80970 ___

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, nemanjai, lei, saghir. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. This patch implements the following function prototypes to utilize the `vmulh[s|u][w|d]` and `vdive[s|u][w|d]

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk marked 2 inline comments as done. amyk added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:18 + // CHECK-NEXT: ret <4 x i32> + return vec_dive(vsia, vsib); +} anil9 wrote: > I may be wrong but where are the variables declared ? I

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk updated this revision to Diff 273578. amyk added a comment. Addressed Anil's comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82609/new/ https://reviews.llvm.org/D82609 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Headers/altivec.h clang/test/CodeGen/bui

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rGe0c02dc9800e: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector… (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D80970?vs=267775&id=273581#toc Reposito

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk updated this revision to Diff 273745. amyk added a comment. Updated to the correct indentation for the functions in `altivec.h`. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/

[PATCH] D82675: [PowerPC][Power10] Implement Vector Extract Mask builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, nemanjai, lei, saghir, kamaub. amyk added projects: LLVM, clang, PowerPC. Herald added subscribers: shchenz, hiraditya. This patch adds the implementation for the following function prototypes: unsigned int vec_extractm

[PATCH] D82725: [PowerPC][Power10] Implement Move to VSR Mask builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, lei, stefanp. amyk added projects: PowerPC, LLVM, clang. Herald added subscribers: shchenz, hiraditya, nemanjai. This patch implements the following function prototypes: vector unsigned char vec_genbm (unsigned long lon

[PATCH] D82726: [PowerPC][Power10] Implement Vector Count Mask Bits builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: PowerPC, power-llvm-team, kamaub, stefanp. amyk added projects: LLVM, clang. Herald added subscribers: shchenz, hiraditya, nemanjai. This patch adds the following function prototypes: unsigned long long vec_cntm (vector unsigned char a, const un

[PATCH] D82727: [PowerPC][Power10] Implement Vector Expand Mask builtins in LLVM/Clang

amyk created this revision. amyk added reviewers: power-llvm-team, PowerPC, saghir, bsaleil. amyk added projects: LLVM, clang. Herald added subscribers: shchenz, hiraditya, nemanjai. This patch implements the following function prototypes: vector unsigned char vec_expandm (vector unsigned char

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk updated this revision to Diff 274260. amyk added a comment. Updated the patch to move the MC/llc tests into the appropriate files. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82467/new/ https://reviews.llvm.org/D82467 Files: clang/lib/Hea

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk added a comment. @lei Could you please take another look at this to see if this change is OK? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___ cfe-commi

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk updated this revision to Diff 274239. amyk added a comment. Updated revision to: - add the MC test cases into `vsx.s` and `vsx.txt`. - create a test file called `builtins-ppc-p10vsx.ll` to place all Power10 VSX builtins tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTI

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

amyk updated this revision to Diff 274667. amyk added a comment. Update patch to: - place MC tests in correct files Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 Files: clang/include/clang/Basic/Builti

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk updated this revision to Diff 274672. amyk added a comment. Update the patch to place MC tests into appropriate files. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82467/new/ https://reviews.llvm.org/D82467 Files: clang/lib/Headers/altivec

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

amyk marked an inline comment as done. amyk added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:108 + signed char *__c) { + // CHECK-BE: store i8 %{{.+}}, i8* %{{.+}}, align 1 + // CHECK-LE: store i8 %{{.+}}, i8* %{{.+}}, ali

[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests

amyk updated this revision to Diff 274679. amyk edited the summary of this revision. amyk added a parent revision: D82584: [PowerPC][Power10] Exploit the High Order Vector Multiply Instructions on Power10. amyk added a comment. Rebased patch. Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

amyk updated this revision to Diff 274680. amyk edited the summary of this revision. amyk added a parent revision: D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests. amyk added a comment. Rebase patch, remove MC tests fro

[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc4e574323210: [PowerPC] Implement low-order Vector Modulus Builtins, and add Vector… (authored by amyk). Changed prior to commit: https://reviews.

[PATCH] D84197: [PowerPC][Power10] Vector String Isolate instruction definitions and MC Tests

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG93fd8dbdc250: [PowerPC] Add Vector String Isolate instruction definitions and MC Tests (authored by Conanap, committed by amyk). Repository: rG LL

[PATCH] D84622: [PowerPC] Implement Vector Extract Low/High Order Builtins in LLVM/Clang

amyk accepted this revision. amyk added a comment. I think overall it LGTM and the indentation can be addressed when committing. Comment at: clang/lib/Headers/altivec.h:17082 +/* vec_extractl */ +static __inline__ vector unsigned long long __ATTRS_o_ai vec_extractl( -

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

amyk added inline comments. Comment at: clang/lib/Headers/altivec.h:17217 + +/* vs[l | r | ra] */ +static __inline__ vector unsigned __int128 __ATTRS_o_ai Add a space after this comment. Comment at: clang/lib/Headers/altivec.h:17227 +vec_sl(vec

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

amyk updated this revision to Diff 283065. amyk added a comment. Rebased the patch and removed MC tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:881 + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs

[PATCH] D82726: [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

amyk updated this revision to Diff 283109. amyk added a comment. Rebased patch and removed MC tests from the patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82726/new/ https://reviews.llvm.org/D82726 Files: clang/include/clang/Basic/Builtin

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