@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTr
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTr
@@ -309,7 +309,45 @@ StringRef AMDGPU::getCanonicalArchName(const Triple &T,
StringRef Arch) {
void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T,
StringMap &Features) {
// XXX - What does the member GPU mean if device name str
@@ -54,3 +56,76 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
&Opts,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {});
+
+ArrayRef S
@@ -309,7 +309,45 @@ StringRef AMDGPU::getCanonicalArchName(const Triple &T,
StringRef Arch) {
void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T,
StringMap &Features) {
// XXX - What does the member GPU mean if device name str
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/
@@ -0,0 +1,288 @@
+// RUN: %clang_cc1 %s -triple=spirv64-unknown-unknown -fsycl-is-device
-std=c++11 -emit-llvm -o %t.ll -O1 -disable-llvm-passes -fms-extensions
-fstrict-vtable-pointers
+// FIXME: Assume load should not require -fstrict-vtable-pointers
+
+// RUN: FileCheck --ch
@@ -1370,7 +1370,7 @@ let IntrProperties = [IntrNoMem, IntrSpeculatable,
IntrWillReturn] in {
// The result of eh.typeid.for depends on the enclosing function, but inside a
// given function it is 'const' and may be CSE'd etc.
-def int_eh_typeid_for : Intrinsic<[llvm_i32_ty],
https://github.com/AlexVlx commented:
> Would be good to fold
> clang/test/CodeGenCXX/vtable-assume-load-nonzero-default-address-space.cpp
> into one of the files it was copied from, otherwise LGTM.
Apologies for the delay, I was away; should be sorted now.
https://github.com/llvm/llvm-proje
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/88182
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@@ -1,14 +1,17 @@
// RUN: %clang_cc1 %s -triple=amdgcn-amd-amdhsa -std=c++11 -emit-llvm -o %t.ll
-O1 -disable-llvm-passes -fms-extensions -fstrict-vtable-pointers
+// RUN: %clang_cc1 %s -triple i686-pc-win32 -emit-llvm -o %t.ms.ll -O1
-disable-llvm-passes -fms-extensions -fstri
@@ -23,8 +26,8 @@ struct B : A {
void g(A *a) { a->foo(); }
// CHECK1-LABEL: define{{.*}} void @_ZN5test14fooAEv()
-// CHECK1: call void @_ZN5test11AC1Ev(ptr
-// CHECK1: %[[VTABLE:.*]] = load ptr addrspace(1), ptr %{{.*}}
+// CHECK1: call{{.*}} void @_ZN5test11AC1Ev(ptr {{((ad
https://github.com/AlexVlx approved this pull request.
This looks fine to me (I do hate that macro being defined on the host though,
so I am biased). Thanks!
https://github.com/llvm/llvm-project/pull/91478
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@@ -0,0 +1,111 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -fsyntax-only -verify %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+
+kernel void test () {
+
+ int sgpr = 0, vgpr = 0, imm = 0;
+
+ // sgpr constraints
+ __asm__ ("s_
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/
@@ -0,0 +1,111 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -fsyntax-only -verify %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+
+kernel void test () {
+
+ int sgpr = 0, vgpr = 0, imm = 0;
+
+ // sgpr constraints
+ __asm__ ("s_
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
clang/lib/
https://github.com/AlexVlx commented:
> Please fix the commit message before you merge; otherwise LGTM
For the commit message I was thinking something along the following lines: `At
the moment, Clang is rather liberal in assuming that 0 (and by extension
unqualified) is always a safe default.
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/88182
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https://github.com/AlexVlx commented:
> @AlexVlx, do you think it's worth promoting
> [SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc)
> and
> [SPV_INTEL_function_pointers](https://github.com/intel/llvm/blo
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTr
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+getTarget().getTr
@@ -23,8 +26,8 @@ struct B : A {
void g(A *a) { a->foo(); }
// CHECK1-LABEL: define{{.*}} void @_ZN5test14fooAEv()
-// CHECK1: call void @_ZN5test11AC1Ev(ptr
-// CHECK1: %[[VTABLE:.*]] = load ptr addrspace(1), ptr %{{.*}}
+// CHECK1: call{{.*}} void @_ZN5test11AC1Ev(ptr {{((ad
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/88182
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AlexVlx wrote:
@bader @asudarsa @michalpaszkowski any opinions from the SPIRV side? I would
like to merge this so as to be able to progress some related work, but I'd
rather not squat on SPIRV real-estate without an ACK from the landlords:)
https://github.com/llvm/llvm-project/pull/89796
_
@@ -368,7 +368,8 @@ CodeGenModule::CodeGenModule(ASTContext &C,
IntTy = llvm::IntegerType::get(LLVMContext, C.getTargetInfo().getIntWidth());
IntPtrTy = llvm::IntegerType::get(LLVMContext,
C.getTargetInfo().getMaxPointerWidth());
- Int8PtrTy = llvm::PointerType::get(LL
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/88182
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/102776
>From d41faf6da8a9eed8c32f6a62fa9ebf38d5824c2c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 11 Aug 2024 01:39:46 +0300
Subject: [PATCH 1/2] Tweak AMDGCNSPIRV ABI to allow for the correct handling
of agg
https://github.com/AlexVlx commented:
Gentle ping.
https://github.com/llvm/llvm-project/pull/102776
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/102776
>From d41faf6da8a9eed8c32f6a62fa9ebf38d5824c2c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 11 Aug 2024 01:39:46 +0300
Subject: [PATCH 1/2] Tweak AMDGCNSPIRV ABI to allow for the correct handling
of agg
@@ -64,6 +66,27 @@ void CommonSPIRABIInfo::setCCs() {
RuntimeCC = llvm::CallingConv::SPIR_FUNC;
}
+ABIArgInfo SPIRVABIInfo::classifyReturnType(QualType RetTy) const {
+ if (getTarget().getTriple().getVendor() != llvm::Triple::AMD)
+return DefaultABIInfo::classifyReturnT
@@ -78,18 +101,52 @@ ABIArgInfo
SPIRVABIInfo::classifyKernelArgumentType(QualType Ty) const {
return ABIArgInfo::getDirect(LTy, 0, nullptr, false);
}
-// Force copying aggregate type in kernel arguments by value when
-// compiling CUDA targeting SPIR-V. This
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/102776
>From d41faf6da8a9eed8c32f6a62fa9ebf38d5824c2c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 11 Aug 2024 01:39:46 +0300
Subject: [PATCH 1/3] Tweak AMDGCNSPIRV ABI to allow for the correct handling
of agg
@@ -78,18 +101,52 @@ ABIArgInfo
SPIRVABIInfo::classifyKernelArgumentType(QualType Ty) const {
return ABIArgInfo::getDirect(LTy, 0, nullptr, false);
}
-// Force copying aggregate type in kernel arguments by value when
-// compiling CUDA targeting SPIR-V. This
@@ -64,6 +66,27 @@ void CommonSPIRABIInfo::setCCs() {
RuntimeCC = llvm::CallingConv::SPIR_FUNC;
}
+ABIArgInfo SPIRVABIInfo::classifyReturnType(QualType RetTy) const {
+ if (getTarget().getTriple().getVendor() != llvm::Triple::AMD)
+return DefaultABIInfo::classifyReturnT
@@ -64,6 +66,27 @@ void CommonSPIRABIInfo::setCCs() {
RuntimeCC = llvm::CallingConv::SPIR_FUNC;
}
+ABIArgInfo SPIRVABIInfo::classifyReturnType(QualType RetTy) const {
+ if (getTarget().getTriple().getVendor() != llvm::Triple::AMD)
+return DefaultABIInfo::classifyReturnT
AlexVlx wrote:
@VyacheslavLevytskyy @michalpaszkowski any objections / thoughts on this?
https://github.com/llvm/llvm-project/pull/102776
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/102776
>From d41faf6da8a9eed8c32f6a62fa9ebf38d5824c2c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 11 Aug 2024 01:39:46 +0300
Subject: [PATCH 1/3] Tweak AMDGCNSPIRV ABI to allow for the correct handling
of agg
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/102776
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https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/95061
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@@ -147,6 +147,14 @@ getNVIDIAOffloadTargetTriple(const Driver &D, const
ArgList &Args,
static std::optional
getHIPOffloadTargetTriple(const Driver &D, const ArgList &Args) {
if (!Args.hasArg(options::OPT_offload_EQ)) {
+auto OffloadArchs = Args.getAllArgValues(options::
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/95061
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https://github.com/AlexVlx commented:
> I'll need to play with this with my driver code. I'm guessing it's because it
> needs to generate an entirely separate toolchain? The OpenMP path basically
> does that by inferring the toolchain from the string value, so we can support
> `--offload-arch=
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/96657
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AlexVlx wrote:
> > > I'll need to play with this with my driver code. I'm guessing it's
> > > because it needs to generate an entirely separate toolchain? The OpenMP
> > > path basically does that by inferring the toolchain from the string
> > > value, so we can support `--offload-arch=sm_89,g
@@ -284,3 +284,48 @@ Example Usage
Base* basePtr = &obj;
basePtr->virtualFunction(); // Allowed since obj is constructed in
device code
}
+
+SPIR-V Support on HIPAMD ToolChain
+==
+
+The HIPAMD ToolChain supports targetting
+`AMDG
@@ -284,3 +284,48 @@ Example Usage
Base* basePtr = &obj;
basePtr->virtualFunction(); // Allowed since obj is constructed in
device code
}
+
+SPIR-V Support on HIPAMD ToolChain
+==
+
+The HIPAMD ToolChain supports targetting
+`AMDG
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/95728
>From 2b500ad9ef2baf27da29146b5a4123dcb75e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 17 Jun 2024 02:15:00 +0100
Subject: [PATCH 1/3] Add interface for exposing a target's flat address space,
if it
https://github.com/AlexVlx requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/96962
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@@ -270,5 +270,5 @@
// VE: target datalayout =
"e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64"
// RUN: %clang_cc1 -triple spirv64-amd -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=
@@ -270,5 +270,5 @@
// VE: target datalayout =
"e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64"
// RUN: %clang_cc1 -triple spirv64-amd -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=
@@ -270,5 +270,5 @@
// VE: target datalayout =
"e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64"
// RUN: %clang_cc1 -triple spirv64-amd -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/96657
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https://github.com/AlexVlx approved this pull request.
LTGM, thanks! Also, apologies for any inconvenience caused.
https://github.com/llvm/llvm-project/pull/96962
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https://github.com/llvm/llvm-project/pull/95728
>From 2b500ad9ef2baf27da29146b5a4123dcb75e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 17 Jun 2024 02:15:00 +0100
Subject: [PATCH 1/3] Add interface for exposing a target's flat address space,
if it
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/95728
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https://github.com/AlexVlx commented:
@jrtc27 @arsenm any additional comments? Are things more palatable in this
form? Should this be turned into an RFC? Thanks.
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@@ -251,6 +251,24 @@ SPIRV::MemorySemantics::MemorySemantics
getMemSemantics(AtomicOrdering Ord) {
llvm_unreachable(nullptr);
}
+SPIRV::Scope::Scope getMemScope(const LLVMContext &Ctx, SyncScope::ID ID) {
+ SmallVector SSNs;
+ Ctx.getSyncScopeNames(SSNs);
+
+ StringRef M
@@ -58,7 +58,35 @@ class SPIRVTargetCodeGenInfo : public
CommonSPIRTargetCodeGenInfo {
SPIRVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
: CommonSPIRTargetCodeGenInfo(std::make_unique(CGT)) {}
void setCUDAKernelCallingConvention(const FunctionType *&FT) const overri
AlexVlx wrote:
> @AlexVlx I don't see much objections against #108528 on a conceptual level,
> so what do you think about merging it into this PR in a way that I commented
> above, by changing `getMemScope()` and moving `getOrInsertSyncScopeID()` into
> its static vars initialization?
At a gl
@@ -245,6 +246,7 @@ class DataLayout {
unsigned getDefaultGlobalsAddressSpace() const {
return DefaultGlobalsAddrSpace;
}
+ unsigned getFlatAddressSpace() const { return FlatAddressSpace; }
AlexVlx wrote:
I think that for general ergonomics making thi
@@ -3050,6 +3050,19 @@ as follows:
address space 0, this property only affects the default value to be used
when creating globals without additional contextual information (e.g. in
LLVM passes).
+``T``
+Specifies the address space for a target's 'flat' address s
AlexVlx wrote:
> I updated the PR description. Hopefully it can make the motivation of this
> patch more clear. I think the central question is, why it can't be just
> address space 0. I don't have a clear answer to that. @arsenm first
> introduced this concept to LLVM at least 8 years ago. I
AlexVlx wrote:
> I think the default AS is expected to be losslessly converted to other AS but
> not the other way around, though I understand it is not clearly stated in
> LangRef or other places and a lot of code just assumes it can.
I don't think this expectation is thoroughly encoded anywh
AlexVlx wrote:
> > Running into an observable situation where this is a concern means that
> > either you've messed around with (non C/C++) attributes, or are linking in
> > something exciting. Neither of which constitutes valid C/C++, and I'm
> > leaning towards saying shouldn't be allowed to
AlexVlx wrote:
> > I'm thinking we could have a language option like
> > `-fimplicit-default-addrspace-cast` that allows all conversions to default.
> > Then if we want users to be aware that this even exists we could suggest it
> > in the error message if it would fix it.
> > I do understand
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
AlexVlx wrote:
> Should restrict this to just adding the basic pass, without the fancy assumed
> address space or assume handling. Leave those for later.
Any particular reason for this, asides from the concern around __constant__ /
UniformConstant? I'll re-iterate that for AMDGCN flavoured SPI
AlexVlx wrote:
> So we both agree, that the compiler must compile the OpenCL code from above
> to SPIR-V without erroring out. We can do it in 2 ways:
>
> 1. Regularize types in the backend (since the backend is based on top of
> global isel we should have here better luck then in the translat
@@ -1,12 +1,14 @@
; This test aims to check ability to support "Arithmetic with Overflow"
intrinsics
; in the special case when those intrinsics are being generated by the
CodeGenPrepare;
-; pass during translations with optimization (note -O3 in llc arguments).
+; pass during
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110897
>From 9f3cac44dde7d0adcf6cd090c0b91f57cb1c4dca Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Wed, 2 Oct 2024 11:18:36 +0100
Subject: [PATCH 1/2] Enable `InferAddressSpaces` for SPIR-V.
---
.../amdgpu-kernel-
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/110897
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https://github.com/AlexVlx commented:
> Move to separate change, not sure this is necessarily valid for spirv
I think that I'd prefer to keep this around, definitely for AMDGCNSPIRV where
we know it is both correct and empirically beneficial. For vanilla SPIR-V I'll
defer to folks on that si
@@ -1,12 +1,14 @@
; This test aims to check ability to support "Arithmetic with Overflow"
intrinsics
; in the special case when those intrinsics are being generated by the
CodeGenPrepare;
-; pass during translations with optimization (note -O3 in llc arguments).
+; pass during
@@ -1,12 +1,14 @@
; This test aims to check ability to support "Arithmetic with Overflow"
intrinsics
; in the special case when those intrinsics are being generated by the
CodeGenPrepare;
-; pass during translations with optimization (note -O3 in llc arguments).
+; pass during
@@ -1,12 +1,14 @@
; This test aims to check ability to support "Arithmetic with Overflow"
intrinsics
; in the special case when those intrinsics are being generated by the
CodeGenPrepare;
-; pass during translations with optimization (note -O3 in llc arguments).
+; pass during
AlexVlx wrote:
> > InstCombine's primary function is a canonicalization pass. You shouldn't be
> > modifying it for specifically SPIRV optimizations (with the exception of
> > SPIRV intrinsic support). SPIRV specific transforms belong in later backend
> > IR passes
>
> Does it mean, that the
AlexVlx wrote:
@arsenm what are you actually trying to fix and what do you expect this to do?
https://github.com/llvm/llvm-project/pull/111975
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https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/110447
When compiling HIP source for AMDGCN flavoured SPIR-V that is expected to be
consumed by the ROCm HIP RT, it's not desirable to set the OpenCL Kernel CC on
`__global__` functions. On one hand, this is not an Op
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110897
>From 9f3cac44dde7d0adcf6cd090c0b91f57cb1c4dca Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Wed, 2 Oct 2024 11:18:36 +0100
Subject: [PATCH 1/2] Enable `InferAddressSpaces` for SPIR-V.
---
.../amdgpu-kernel-
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110695
>From 758fb6e28844d89031b5497d651cb2a9b71b6a0e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 1 Oct 2024 17:10:50 +0100
Subject: [PATCH 1/2] Explicitly encode native integer widths for SPIR-V.
---
clang/
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110447
>From f65d933740225122d832a340b89fe4da0d80a204 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 30 Sep 2024 03:09:58 +0100
Subject: [PATCH] Don't use the OpenCLKernel CC when targeting AMDGCNSPIRV.
---
cla
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110695
>From 758fb6e28844d89031b5497d651cb2a9b71b6a0e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 1 Oct 2024 17:10:50 +0100
Subject: [PATCH 1/2] Explicitly encode native integer widths for SPIR-V.
---
clang/
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110695
>From 758fb6e28844d89031b5497d651cb2a9b71b6a0e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 1 Oct 2024 17:10:50 +0100
Subject: [PATCH] Explicitly encode native integer widths for SPIR-V.
---
clang/lib/
@@ -5903,7 +5904,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
auto Call = RValue::get(
EmitRuntimeCall(CGM.CreateRuntimeFunction(FTy, Name), Args));
if (TmpSize)
-EmitLifetimeEnd(TmpSize, TmpPtr);
+
@@ -1,67 +1,107 @@
-// RUN: %clang_cc1 -O0 -cl-std=CL1.2 -triple amdgcn---amdgizcl -emit-llvm %s
-o - | FileCheck -check-prefixes=CHECK,CL12 %s
-// RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn---amdgizcl -emit-llvm %s
-o - | FileCheck -check-prefixes=CHECK,CL20 %s
+// NOTE:
AlexVlx wrote:
> > I do believe that this is a necessary bit of query-able information,
> > especially from a Clang, for correctness reasons (more on that below).
>
> I don't think this buys frontends much. Clang still needs to understand the
> full language address space -> target address spa
AlexVlx wrote:
> Just a heads up, this change is gonna break some OpenMP tests, specifically
> those prefix with `ompx`.
Just to clarify, adding the deprecation warning will break them, or the
eventual, as-of-yet not-scheduled, removal, will?
https://github.com/llvm/llvm-project/pull/112849
_
AlexVlx wrote:
> I made #113156 to hopefully address the OpenMP issue. We use it in the
> runtime itself for a lot of stuff so removing it would definitely break that.
> The function call here matches what NVIDIA provides via PTX. I think we
> should have an optimization that replaces the intr
AlexVlx wrote:
> > More specifically, how do you expect Clang to figure this out when e.g.
> > compiling C++ for some AS rich target that decided to default to something
> > odd
>
> I do not expect clang to be using the datalayout to decide anything. That is
> not really the purpose of the da
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/112849
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@@ -337,9 +337,12 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (hasFastFMA())
Builder.defineMacro("FP_FAST_FMA");
- Builder.defineMacro("__AMDGCN_WAVEFRONT_SIZE__", Twine(WavefrontSize));
- // ToDo: deprecate this macro for naming consistency
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110695
>From 758fb6e28844d89031b5497d651cb2a9b71b6a0e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 1 Oct 2024 17:10:50 +0100
Subject: [PATCH 1/2] Explicitly encode native integer widths for SPIR-V.
---
clang/
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110695
>From 758fb6e28844d89031b5497d651cb2a9b71b6a0e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 1 Oct 2024 17:10:50 +0100
Subject: [PATCH 1/3] Explicitly encode native integer widths for SPIR-V.
---
clang/
@@ -1,9 +1,10 @@
-// RUN: %clang_cc1 %s -emit-llvm -o - -O0 -ffake-address-space-map -triple
i686-pc-darwin | FileCheck -enable-var-scope -check-prefixes=ALL,X86 %s
-// RUN: %clang_cc1 %s -emit-llvm -o - -O0 -triple amdgcn | FileCheck
-enable-var-scope -check-prefixes=ALL,AMDGCN
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/112554
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