[PATCH] D115942: [X86][MS] Change the alignment of f80 to 16 bytes on Windows 32bits to match with ICC

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115942/new/ https://reviews.llvm.org/D115942 ___ cfe-commits mailing list cfe-commits

[PATCH] D116994: [RISCV] Add bfp and bfpw intrinsic in zbf extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116994/new/ https://reviews.llvm.org/D116994 ___

[PATCH] D117098: [RISCV] update zfh and zfhmin extention to v1.0

craig.topper added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:207 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \ If it's not experimental no

[PATCH] D117130: [RISCV] Move Zba/Zbb/Zbc/Zbs out of experimental since they have been ratified.

craig.topper created this revision. craig.topper added reviewers: asb, luismarques, jrtc27, evandro. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, StephenFan, vkmr, frasercrmck, jdoerfert, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D117130: [RISCV] Move Zba/Zbb/Zbc/Zbs out of experimental since they have been ratified.

craig.topper abandoned this revision. craig.topper added a comment. Abandoning in favor of D117131 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117130/new/ https://reviews.llvm.org/D117130 __

[PATCH] D117131: [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117131/new/ https://reviews.llvm.org/D117131 ___

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:687 // TODO: This has been removed in later specs, which specify that D implies F if (HasD && !HasF) return createStringError(errc::invalid_argument, Do we need the equiv

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108694/new/ https://reviews.llvm.org/D108694 ___

[PATCH] D117098: [RISCV] update zfh and zfhmin extention to v1.0

craig.topper added a comment. A new test `inline-asm-zfh-constraint-f.ll` was added today that needs it's RUN line updated. Comment at: clang/test/Preprocessor/riscv-target-features.c:231 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ +

[PATCH] D117098: [RISCV] update zfh and zfhmin extention to v1.0

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117098/new/ https://reviews.llvm.org/D117098 ___

[PATCH] D117380: [RISCV] [Clang] Add attra for crc32_d/crc32c_d

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117380/new/ https://reviews.llvm.org/D117380 ___

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:184 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); +Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew)); +Builder.defineMacro("__riscv_v_max_eew_fp", Twine(MaxEewFp)); -

[PATCH] D112408: [RISCV][MC] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:91 void updateMinVLen(); + void updateMaxEew(); }; There's no definition for this Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:821 -let Pred

[PATCH] D112408: [RISCV][MC] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:353 + +multiclass VIndexLoadStore EEWList> { + foreach n = EEWList in { Why is this class only used for [64] Comment at: llvm/lib/Target/RISCV/RISCVInstrI

[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:65 +// Zbt extension +TARGET_BUILTIN(__builtin_riscv_cmov, "LiLiLiLi", "nc", "experimental-zbt") +TARGET_BUILTIN(__builtin_riscv_cmix, "LiLiLiLi", "nc", "experimental-zbt") ---

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

craig.topper added a comment. In D111617#3060377 , @HsiangKai wrote: > Although it reduces the header size, this patch will increase the binary size > of clang. > > Debug build: > Before this patch: > > textdatabss d

[PATCH] D115441: [X86][MS] Add 80bit long double support for Windows

craig.topper added a comment. Doesn’t icc also emit code into main to change the FPCW precision control field? Is making long double 80 bits useful if you don’t increase the precision in hardware? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1154

[PATCH] D115611: [X86][BF16] delete `typedef unsigned short __bfloat16`

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512vlbf16intrin.h:416 ///and fraction field is truncated to 7 bits. -static __inline__ __bfloat16 __DEFAULT_FN_ATTRS128 _mm_cvtness_sbh(float __A) { +static __inline__ short __DEFAULT_FN_ATTRS128 _mm_cvtnes

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:714 void RISCVISAInfo::updateImplication() { + const StringMap> Implications = { + {"v", {"zvlsseg", "zvl128b"}}, I think I'd like to see this as a static data structure rath

[PATCH] D115670: Correct behavior of Vector boolean-operations, implement vector operator-

craig.topper added inline comments. Comment at: clang/lib/AST/ExprConstant.cpp:2915 case BO_EQ: -Result = (LHSValue == RHSValue); +Result = -(LHSValue == RHSValue); break; erichkeane wrote: > efriedma wrote: > > Using "operator=" to assign an int

[PATCH] D115670: Correct behavior of Vector boolean-operations, implement vector operator-

craig.topper added inline comments. Comment at: clang/lib/AST/ExprConstant.cpp:2915 case BO_EQ: -Result = (LHSValue == RHSValue); +Result = -(LHSValue == RHSValue); break; craig.topper wrote: > erichkeane wrote: > > efriedma wrote: > > > Using "op

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:782 +if (IsZvlExt) { + ExtName.consume_back("b"); + unsigned ZvlLen; craig.topper wrote: > I think we should check the return value from consume_back and getAsInteger

[PATCH] D115611: [X86][BF16] delete `typedef unsigned short __bfloat16`

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512vlbf16intrin.h:416 ///and fraction field is truncated to 7 bits. -static __inline__ __bfloat16 __DEFAULT_FN_ATTRS128 _mm_cvtness_sbh(float __A) { +static __inline__ short __DEFAULT_FN_ATTRS128 _mm_cvtnes

[PATCH] D115409: [SelectionDAGBuilder] drop special handling for CallBr

craig.topper added inline comments. Comment at: llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll:23 +; CHECK-NEXT: t30: ch,glue = inlineasm_br t22, {{.*}}, t22:1 +; CHECK-NEXT: t32: ch = br t30, BasicBlock:ch nickdesaulniers wrote: > @craig.topper can you triple

[PATCH] D115670: Correct behavior of Vector boolean-operations, implement vector operator-

craig.topper added inline comments. Comment at: clang/lib/AST/ExprConstant.cpp:10393 + if (Elt.getKind() == APValue::Int) { +Elt.setInt(-Elt.getInt()); + } else { Can this be `Elt.getInt().negate()`? Comment at: clang/lib/AST/

[PATCH] D115670: Implement some constexpr vector unary operators, fix boolean-ops

craig.topper added inline comments. Comment at: clang/lib/AST/ExprConstant.cpp:10188 +bool VisitUnaryOperator(const UnaryOperator *E); +// FIXME: Missing: unary ~, conditional operator (for GNU // conditional select), shufflevector, ExtVectorElementEx

[PATCH] D115709: [RISCV] Remove Vamo Extention

craig.topper added a comment. In D115709#3194538 , @frasercrmck wrote: > I think it'd be helpful for the description to note why this is being > removed, what happened to the extension, etc. I agree Repository: rG LLVM Github Monorepo CHANGES SINC

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:739 static constexpr ImpliedExtsEntry ImpliedExts[] = { -{{"v"}, {ImpliedExtsV}}, -{{"zfh"}, {ImpliedExtsZfh}}, +{"v", {ImpliedExtsV}}, +{"zfh", {ImpliedExtsZfh}},

[PATCH] D115709: [RISCV] Remove Zvamo Extention

craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115709/new/ https://reviews.llvm.org/D115709 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D115804: [CodeGen] use saturating FP casts when compiling with "no-strict-float-cast-overflow"

craig.topper added a comment. What's the plan for constrained intrinsics versions of these intrinsics? The IRBuilder calls for CreateFPToSI and CreateFPToUI are strict FP aware, but this new code isn't. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:33 + bool operator!=(const RISCVExtensionVersion &Version) const { +return !operator==(Version); + } Use `!(*this == Version)` Comment at: llvm/lib/S

[PATCH] D114425: [clang] Add __builtin_bswap128

craig.topper added a comment. What does the builtin due if __int128 isn't supported? Even though the type isn't legal the builtin can still be called with a narrower type that would be implicitly converted. Does that work correctly? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACT

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:20 +#undef BUILTIN Can you undef TARGET_BUILTIN here too? I missed that when I added it on line 15. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM thanks! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98682/new/ https://reviews.llvm.org/D98682 ___ cfe-commits mailing

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96843/new/ https://reviews.llvm.org/D96843 _

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:700 +for (auto Idx : CTypeOrder) { + if (Seen.count(Idx)) +PrintFatalError( You can use ``` if (!Seen.insert(Idx).second) PrintFatalError ``` This avoids w

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM other than that one comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98388/new/ https://reviews.llvm.org/D98388

[PATCH] D98923: [Driver] Pass -fexperimental-strict-floating-point to cc1 if it is specified

craig.topper added a comment. Isn't OPT_fexperimental_strict_floating_point marked as a CC1Option in Options.td. Can the driver even recognize it? Can you use -Xclang -fexperimental-strict-floating-point for your use case? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION http

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c:5 + +#include + I don't think this include is needed. You're calling the __builtin names directly. Comment at: clang/test/CodeGen/RISCV/rvb-

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

craig.topper added a comment. Please note I asked that this patch be separate from D99009 because the rvintrin.h file name may not be the final filename we want to use. This https://github.com/riscv/riscv-c-api-doc/pull/14 suggests it should be riscv_intrinsic

[PATCH] D99082: [RISCV][NFC] Fix RVV intrinsic tests.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99082/new/ https://reviews.llvm.org/D99082 _

[PATCH] D98848: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:90 +// equivalent integer vector type with EEW and corresponding ELMUL (elmul = +// (eew/sew) * lmul). Fore example, vector type is __rvv_float16m4 +// (SEW=16, LMUL=4) and L

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rv32Zbr.ll:1 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \ jrtc27 wrote: >

[PATCH] D98848: [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:23 #include "llvm/ADT/Twine.h" +#include "llvm/Support/Regex.h" #include "llvm/TableGen/Error.h" ---

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

craig.topper added inline comments. Comment at: llvm/docs/CommandGuide/tblgen.rst:133 - Generate generic automata. + Generate overloaded automata. This looks like an unintended change Comment at: llvm/docs/CommandGuide/tblgen.rst:279 -

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added a comment. What are we gaining from making the intrinsics use vector types if no vector operations are supported other than the intrinsics? Why can't we just use an xlen integer type? Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setO

[PATCH] D99151: [RISCV][Clang] Add RVV vleff intrinsic functions.

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vle16ff.c:9 +// RUN: -target-feature +experimental-zfh -target-feature +m -fallow-half-arguments-and-returns -Werror -Wall -S -o - %s >/dev/null 2>%t +// RUN: FileCheck --check-prefix=ASM -

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

craig.topper added inline comments. Comment at: clang/lib/Headers/riscv_zbb_intrin.h:18 +// Zbb +static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) { + return __builtin_riscv_orc_b(rs1); I think rather than int_xlen_t we want an int32_t ve

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

craig.topper added a comment. Please upload the patch using arcanist or using -U99 when generating the diff. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99320/new/ https://reviews.llvm.org/D99320

[PATCH] D99319: [RISCV] [2/2] Add intrinsic for Zbb extension

craig.topper added inline comments. Comment at: clang/lib/Headers/riscv_zbb_intrin.h:18 +// Zbb +static __inline__ int_xlen_t __DEFAULT_FN_ATTRS _rv_orc_b(int_xlen_t rs1) { + return __builtin_riscv_orc_b(rs1); craig.topper wrote: > I think rather than int_xlen_t

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added a comment. Please reupload the patch using something like "git diff -U9". We should be able to expand the full diff here so that phabricator doesn't say "Context not available." Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3398 // message. + bool miss_feature_error = false; + SmallVector ReqFeatures; Variable names should start with a capital letter and use CamelCase. Comment at:

[PATCH] D99008: [RISCV] [2/2] Add intrinsic for Zbr extension

craig.topper added inline comments. Comment at: clang/lib/Headers/riscv_zbr_intrin.h:9 + */ + +#ifndef __RISCV_ZBR_INTRIN_H Please add ``` #ifndef __RVINTRIN_H

[PATCH] D99189: [RISCV][Clang] Update new overloading rules for RVV intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM other than those typos Comment at: clang/include/clang/Basic/riscv_vector.td:161 + // This builtin supports non-masked function overloading api. + // All m

[PATCH] D99151: [RISCV][Clang] Add RVV vleff intrinsic functions.

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vle16ff.c:9 +// RUN: -target-feature +experimental-zfh -target-feature +m -fallow-half-arguments-and-returns -Werror -Wall -S -o - %s >/dev/null 2>%t +// RUN: FileCheck --check-prefix=ASM -

[PATCH] D99465: [Clang][X86] Mark some VAES builtins as conditionally defined

craig.topper added a comment. We can't use preprocessor defines in the intrinsic header files. It prevents being able to use the intrinsics with attribute(target("avx512f,vaes")). What's preventing __m512i from being defined? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

[PATCH] D99465: [Clang][X86] Mark some VAES builtins as conditionally defined

craig.topper added a comment. I think I've fixed this in 3fb40ce167ff5f05afadf8f525ff9e17350d6d7f . We need to use the preprocessor define that says avx512fintrin.h was included rather than the feature define. We already did a

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:17865 +ID = Intrinsic::riscv_crc32_b; +IntrinsicTypes = {ResultType, Ops[0]->getType()}; +break; With the llvm_any_ty change, you'll only need ResultType here. =

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:21 +// Zbb extension +TARGET_BUILTIN(__builtin_riscv_orc_b, "LiLi", "nc", "experimental-zbb") +TARGET_BUILTIN(__builtin_riscv32_orc_b, "ZiZi", "nc", "experimental-zbb") Ca

[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98616/new/ https://reviews.llvm.org/D98616 _

[PATCH] D99524: [RISCV][Clang] Add some RVV Integer intrinsic functions.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:432 +["vv", "Uv", "UvUvUv"], +["vx", "Uv", "UvUvUe"]]>; + Should we have a common class for vadd/vsub/vand/vx

[PATCH] D99525: [RISCV][Clang] Add RVV vnsra, vnsrl and vwmul intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99525/new/ https://reviews.llvm.org/D99525 _

[PATCH] D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled.

craig.topper added inline comments. Comment at: clang/include/clang/Driver/Options.td:1642 +Group, Flags<[CoreOption, HelpHidden]>, +HelpText<"Enable transforming aligned vector move instruction to " + "unaligned vector move.">; As far the use

[PATCH] D99565: [X86] Support replacing aligned vector moves with unaligned moves when avx is enabled.

craig.topper added a comment. The only use I could really see for this is to prevent a developers code from crashing when it’s distributed to someone else. For paranoia because it’s possible you have a bug and got lucky with alignment in your internal testing before you shipped. If you need th

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3418 // message. + bool Feature_Missing = false; + SmallVector ReqFeatures; LLVM coding style does not allow _ in variable names. Comment at: clang/lib/Sema/Se

[PATCH] D99524: [RISCV][Clang] Add some RVV Integer intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99524/new/ https://reviews.llvm.org/D99524 _

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:28 +TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr") + Jim wrote: > I

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added a comment. I think this looks good to me. Anyone else have any comments? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99009/new/ https://reviews.llvm.org/D99009 ___ cfe-commits mailin

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

craig.topper added a comment. I think this looks good to me. Anyone else have any comments? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99320/new/ https://reviews.llvm.org/D99320 ___ cfe-commits mailin

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

craig.topper added a comment. In D99320#2661285 , @asb wrote: > Can I just check the reasoning on the naming? I see that the bitmanip 0.93 > spec proposes `_{rv,rv32,rv64}_{opname}` intrinsics. Does the > `__builtin__{riscv,riscv32,riscv64}_opname` forma

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:282 +} +// Encode vx/wx in the sufffix of mangled name +let Name = NAME # "_" # vx_suffixes_prototype[0], sufffix->suffix Comment at: clang/in

[PATCH] D99668: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions.

craig.topper requested changes to this revision. craig.topper added inline comments. This revision now requires changes to proceed. Comment at: clang/include/clang/Basic/riscv_vector.td:761 +defm vfdiv : RVVFloatingBinBuiltinSet; +defm vfrdiv : RVVFloatingBinBuiltinSet; + ---

[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

craig.topper added a comment. A user interrupt is different than a regular interrupt right? It doesn't make sense that we would change the behavior of the interrupt calling convention just because the the user interrupt instructions are enabled. That would occur just from passing a -march for a

[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

craig.topper added a comment. In D99708#2664164 , @hjl.tools wrote: > In D99708#2664076 , @LuoYuanke wrote: > >> In D99708#2663989 , @craig.topper >> wrote: >> >>> A user in

[PATCH] D99668: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99668/new/ https://reviews.llvm.org/D99668 _

[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

craig.topper added a comment. In D99708#2664351 , @hjl.tools wrote: > In D99708#2664218 , @craig.topper > wrote: > >> In D99708#2664164 , @hjl.tools >> wrote: >> >>> In D99

[PATCH] D99711: [RISCV] [1/2] Add intrinsic for Zbc extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:22 +TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc") +TARGET_BUILTIN(__builtin_riscv_clmul_h, "LiLiLi", "nc", "experimental-zbc") +TARGET_BUILTIN(__builtin_riscv_c

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. I'm going to approve this. If we need to change the builtin names in the future that's easy enough to do. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM. We can adjust the builtin names in the future if we need to do something different to match gcc. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://r

[PATCH] D99711: [RISCV] [1/2] Add intrinsic for Zbc extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM. We can adjust the builtin names in the future if we need to do something different to match gcc. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://r

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb001d574d7d9: [RISCV] Add IR intrinsic for Zbr extension (authored by LevyHsu, committed by craig.topper). Changed prior to commit: https://review

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:11190 +def err_riscv_builtin_requires_extension : Error< + "builtin requires %0 extension support to be enabled">; } // end of sema component. jrtc27 wrote: > This

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG944adbf28550: Recommit "[RISCV] Add IR intrinsic for Zbb extension" (authored by LevyHsu, committed by craig.topper). Changed prior to commit: htt

[PATCH] D99711: [RISCV] [1/2] Add intrinsic for Zbc extension

This revision was automatically updated to reflect the committed changes. Closed by commit rGf78d932cf23a: [RISCV] Add IR intrinsics for Zbc extension (authored by LevyHsu, committed by craig.topper). Changed prior to commit: https://reviews.llvm.org/D99711?vs=334882&id=335008#toc Repository:

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:17944 + + // P extension +#define EMIT_BUILTIN(NAME, INT) \ Please put this above the vector extension since the comment says "vector builtins are handled from here" =

[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

craig.topper added inline comments. Comment at: llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll:1 +; RUN: llc < %s | FileCheck %s -check-prefixes=CHECK,CHECK-USER +; RUN: llc -O0 < %s | FileCheck %s -check-prefixes=CHECK0,CHECK0-USER Please use update_llc_test_check

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c:35 +vint16mf4_t test_vwadd_vx_i16mf4(vint8mf8_t op1, int8_t op2, size_t vl) { + return vwadd_vx(op1, op2, vl); +} khchen wrote: > khchen wrote: > > craig.t

[PATCH] D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:315 +multiclass RVVFloatingWidenTerBuiltinSet { + let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in { +defm "" : RVVOutOp1Op2BuiltinSet HsiangKai wrote: > > why is there

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99741/new/ https://reviews.llvm.org/D99741 _

[PATCH] D99963: [RISCV][Clang] Add RVV merge intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99963/new/ https://reviews.llvm.org/D99963 _

[PATCH] D99742: [RISCV][Clang] Add RVV Type-Convert intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99742/new/ https://reviews.llvm.org/D99742 _

[PATCH] D99984: [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

craig.topper created this revision. craig.topper added reviewers: asb, frasercrmck, luismarques, jrtc27, evandro, HsiangKai, khchen, arcbbb. Herald added subscribers: StephenFan, vkmr, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01

[PATCH] D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99669/new/ https://reviews.llvm.org/D99669 _

[PATCH] D99526: [RISCV][Clang] Add RVV Widening Integer Add/Subtract intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99526/new/ https://reviews.llvm.org/D99526 _

[PATCH] D99964: [RISCV][Clang] Add all RVV Reduction intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99964/new/ https://reviews.llvm.org/D99964 _

[PATCH] D99965: [RISCV][Clang] Add more RVV load/store intrinsic functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99965/new/ https://reviews.llvm.org/D99965 _

[PATCH] D100074: [RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI

craig.topper created this revision. craig.topper added reviewers: khchen, HsiangKai, evandro, arcbbb. Herald added subscribers: StephenFan, vkmr, frasercrmck, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,

[PATCH] D100074: [RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI

This revision was automatically updated to reflect the committed changes. Closed by commit rG5f6b3d1833fd: [RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D100085: [X86] Support -march=rocketlake

craig.topper added inline comments. Comment at: compiler-rt/lib/builtins/cpu_model.c:101 INTEL_COREI7_ALDERLAKE, + INTEL_COREI7_ROCKETLAKE, AMDFAM19H_ZNVER3, This order is defined by libgcc. We can't insert in the middle unless ZNVER3 was in the wrong pla

[PATCH] D99984: [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:259 .Case("riscv64", Is64Bit) + .Case("64bit", Is64Bit) .Case("m", HasM) frasercrmck wrote: > What's the difference between this new feature and `riscv64` above?

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