[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-16 Thread Sam Elliott via cfe-commits
https://github.com/lenary ready_for_review https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-16 Thread Sam Elliott via cfe-commits
lenary wrote: I've updated this and gone with `rp2350-hazard3` as that's the prevailing consensus. This is stacked on #104601 because i got fed up with the invalid cpu note tests. Otherwise it's ready to review. https://github.com/llvm/llvm-project/pull/102452

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-16 Thread Sam Elliott via cfe-commits
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/102452 >From 0e9579c91242fc63eb2cb686adc105fd248fef91 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 16 Aug 2024 07:52:53 -0700 Subject: [PATCH 1/2] [clang][test] Split invalid-cpu-note tests This change does tw

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-16 Thread Sam Elliott via cfe-commits
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/102452 >From 0e9579c91242fc63eb2cb686adc105fd248fef91 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 16 Aug 2024 07:52:53 -0700 Subject: [PATCH 1/2] [clang][test] Split invalid-cpu-note tests This change does tw

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-16 Thread Luke Wren via cfe-commits
Wren6991 wrote: I think we are really compressing a three-tuple of something like `--`. For a two-tuple I prefer `rp2350-hazard3` over `raspberrypi-rp2350` because: * RP2350 is a SoC, not a CPU, so doesn't belong at the end of the tuple * RP2350 also has Cortex-M33s, so leaving `hazard3` out o

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-15 Thread Sam Elliott via cfe-commits
lenary wrote: I've reached out to Luke to ask his/RPi's opinion (but I think he might be away at the moment, so a reply might be slow). My preference remains `raspberrypi-rp2350` because it matches our `-` approach taken so far (for everything except rocket). https://github.com/llvm/llvm-proj

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-15 Thread Min-Yih Hsu via cfe-commits
mshockwave wrote: > So for this particular PR, we just need a name people are happy with (perhaps > check if the vendor has a preference?). Something like `-mcpu=rp2350-hazard3` > perhaps? +1 on `-mcpu=rp2350-hazard3` over `-mcpu=raspberrypi-rp2350` because the former is more specific to the

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-15 Thread Alex Bradbury via cfe-commits
asb wrote: I think our conclusion from the sync-up call discussion matches what we'd roughly concluded in this thread, which is that with an instantiation of Hazard3 shipping in the RP2350 this isn't really a good test case for questions about when it's worth including a CPU definition for an

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread Alex Bradbury via cfe-commits
asb wrote: > I do have some worries about the definition as-is, as the core in the repo > has optional features (configurable at tape-out time). Reading the RP2350 > datasheet, not all of the optional features for Hazard3 are enabled (and I'm > of the opinion that the lack of arm-like `-mcpu=+

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread Sam Elliott via cfe-commits
lenary wrote: I do have some worries about the definition as-is, as the core in the repo has optional features (configurable at tape-out time). Reading the RP2350 datasheet, not all of the optional features for Hazard3 are enabled (and I'm of the opinion that the lack of arm-like `-mcpu=++no`

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread Sam Elliott via cfe-commits
lenary wrote: I am happy to be point person on maintaining this core definition in LLVM, I communicate regularly with Luke, the core designer. As for the core itself, it's obviously maintained by Luke, and as Alex points out, it's just been announced to be in commercial products released by R

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread Michael Maitland via cfe-commits
michaelmaitland wrote: There was a prior discussion about what designs should go in. The initial quote from @asb was: > it's obvious that commercial designs with active support should go in, and > that some core design I hacked up over a weekend shouldn't but we haven't had > the need to disc

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread Yingwei Zheng via cfe-commits
dtcxzyw wrote: It looks like a toy project :( The RTL design is not frozen. https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread Sam Elliott via cfe-commits
https://github.com/lenary converted_to_draft https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread via cfe-commits
llvmbot wrote: @llvm/pr-subscribers-clang @llvm/pr-subscribers-clang-driver Author: Sam Elliott (lenary) Changes Luke Wren's Hazard3 is an open-source 32-bit RISC-V core. The core's source code and docs are available on github: https://github.com/wren6991/hazard3 The core has just hit 1.

[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

2024-08-08 Thread Sam Elliott via cfe-commits
https://github.com/lenary created https://github.com/llvm/llvm-project/pull/102452 Luke Wren's Hazard3 is an open-source 32-bit RISC-V core. The core's source code and docs are available on github: https://github.com/wren6991/hazard3 The core has just hit 1.0 today, which seems to me to be a g