https://github.com/lenary created https://github.com/llvm/llvm-project/pull/102452
Luke Wren's Hazard3 is an open-source 32-bit RISC-V core. The core's source code and docs are available on github: https://github.com/wren6991/hazard3 The core has just hit 1.0 today, which seems to me to be a good time to add it as a named CPU in LLVM. >From af4b4eba72c98c12b4e1afa1db58d68bf46d38e8 Mon Sep 17 00:00:00 2001 From: Sam Elliott <quic_aelli...@quicinc.com> Date: Thu, 8 Aug 2024 04:03:36 -0700 Subject: [PATCH] [RISCV] Add Hazard3 CPU Luke Wren's Hazard3 is an open-source 32-bit RISC-V core. The core's source code and docs are available on github: https://github.com/wren6991/hazard3 The core has just hit 1.0 today, which seems to me to be a good time to add it as a named CPU in LLVM. --- clang/test/Driver/riscv-cpus.c | 17 +++++++++++++++++ clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Target/RISCV/RISCVProcessors.td | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 29687ac4e1c83..dd135bb85ea84 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -402,6 +402,23 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s +// MCPU-HAZARD3: "-target-cpu" "hazard3" +// MCPU-HAZARD3-SAME: "-target-feature" "+m" +// MCPU-HAZARD3-SAME: "-target-feature" "+a" +// MCPU-HAZARD3-SAME: "-target-feature" "+c" +// MCPU-HAZARD3-SAME: "-target-feature" "+b" +// MCPU-HAZARD3-SAME: "-target-feature" "+zicsr" +// MCPU-HAZARD3-SAME: "-target-feature" "+zifencei" +// MCPU-HAZARD3-SAME: "-target-feature" "+zcb" +// MCPU-HAZARD3-SAME: "-target-feature" "+zcmp" +// MCPU-HAZARD3-SAME: "-target-feature" "+zba" +// MCPU-HAZARD3-SAME: "-target-feature" "+zbb" +// MCPU-HAZARD3-SAME: "-target-feature" "+zbc" +// MCPU-HAZARD3-SAME: "-target-feature" "+zbkb" +// MCPU-HAZARD3-SAME: "-target-feature" "+zbs" +// MCPU-HAZARD3-SAME: "-target-abi" "ilp32" + // Check failed cases // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 249bea2311549..7485730296e09 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -81,7 +81,7 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32{{$}} +// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, hazard3, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32{{$}} // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' @@ -89,7 +89,7 @@ // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, hazard3, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32, generic, rocket, sifive-7-series{{$}} // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 1ed860de6b9dc..579c1c1a37aab 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -108,6 +108,7 @@ Changes to the RISC-V Backend fill value) rather than NOPs. * Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64`` * ``-mcpu=sifive-p470`` was added. +* Added Hazard3 CPU: ``-mcpu=hazard3`` (32-bit only). Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index ec9322f3e9924..153ad0a661945 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -428,3 +428,21 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", FeatureStdExtZvkt, FeatureStdExtZvl256b]), [TuneDLenFactor2]>; + +def HAZARD3 : RISCVProcessorModel<"hazard3", + NoSchedModel, + [Feature32Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtB, + FeatureStdExtC, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs, + FeatureStdExtZbkb, + FeatureStdExtZcb, + FeatureStdExtZcmp]>; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
