llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder
`openmp-offload-libc-amdgpu-runtime` running on `omp-vega20-1` while building
`clang,llvm` at step 7 "Add check check-offload".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/73/builds/11787
Here is
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@V-FEXrt Congratulations on having your first Pull Request (PR) merged into the
LLVM Project!
Your changes will be combined with recent changes from other authors, then
tested by our [build bots](https://lab.llvm.org/buildbot/). If there is a
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V-FEXrt wrote:
Yeah I figured they weren't broken by me but I had assumed I needed all green
before merging so was waiting for the fix to make it into main but happy to
merge as is if that's acceptable
https://github.com/llvm/llvm-project/pull/116858
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s-perron wrote:
The spir-v test failures are unrelated to your change. It is caused by a
problem in spirv-val, and it has been fixed.Don't let that stop you from
merging.
https://github.com/llvm/llvm-project/pull/116858
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c
@@ -0,0 +1,219 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: [[glsl_450_ext:%.+]] = OpExtInstImport "GLSL.std.4
https://github.com/llvm-beanz approved this pull request.
https://github.com/llvm/llvm-project/pull/116858
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@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
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https://github.com/llvm/llvm-project/pull/116858
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@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
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@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
https://github.com/s-perron approved this pull request.
Generally looks good to me. Thanks for fixing up the vector size issue. I have
a couple minor issue, but I'm fine with this.
https://github.com/llvm/llvm-project/pull/116858
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@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3181,136 +3193,250 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -3139,136 +3151,269 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
return AcReg;
}
-bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
-const SPIRVType *ResType,
-
@@ -17,12 +17,10 @@ double test_int_builtin(double p0) {
double2 test_int_builtin_2(double2 p0) {
return __builtin_hlsl_elementwise_firstbithigh(p0);
- // expected-error@-1 {{1st argument must be a vector of integers
- // (was 'double2' (aka 'vector'))}}
+ // expected-err
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/116858
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@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff d5fe6332c9f25590b9878ad31d6461ea581e0fa5
e67adb99590fcc2fe256ec04e0f31c39ea315ab8 --e
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From a63e05d2e090edf7834fb62296bccd071a8e38b8 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/7] [HLSL] Implement elementwise firstbitlow builtin
---
clan
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
spall wrote:
I'd also update your description to mention fixing the vector > size 2 bug in
FirstBitHigh as well, by making this code general purpose for both firstbitlow
and firstbithigh.
https://github.com/llvm/llvm-project/pull/116858
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@@ -96,15 +96,20 @@ class SPIRVInstructionSelector : public InstructionSelector
{
bool selectFirstBitHigh(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I, bool IsSigned) const;
- bool selectFirstBitHigh16(Register ResVReg, const SPIRVT
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -0,0 +1,219 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: [[glsl_450_ext:%.+]] = OpExtInstImport "GLSL.std.4
@@ -0,0 +1,168 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: [[glsl_450_ext:%.+]] = OpExtInstImport "GLSL.std.4
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From eeb864972c48625fa56b96e6b018affe04d84e00 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/6] [HLSL] Implement elementwise firstbitlow builtin
---
clan
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From eeb864972c48625fa56b96e6b018affe04d84e00 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/5] [HLSL] Implement elementwise firstbitlow builtin
---
clan
https://github.com/V-FEXrt updated
https://github.com/llvm/llvm-project/pull/116858
>From eeb864972c48625fa56b96e6b018affe04d84e00 Mon Sep 17 00:00:00 2001
From: Ashley Coleman
Date: Thu, 14 Nov 2024 11:53:39 -0700
Subject: [PATCH 1/4] [HLSL] Implement elementwise firstbitlow builtin
---
clan
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/s-perron commented:
There is only potential problem with the vector sizes. Sorry I did not catch
that on the previous PR. I would also like to see the code refactored a little
to reduce the amount of repeated code. I think each step except for 2 in
`selectFirstBit*64` could
@@ -0,0 +1,104 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: [[glsl_450_ext:%.+]] = OpExtInstImport "GLSL.std.4
https://github.com/s-perron edited
https://github.com/llvm/llvm-project/pull/116858
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@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/s-perron edited
https://github.com/llvm/llvm-project/pull/116858
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@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/s-perron commented:
I hoping we can make this simpler than the Msb builtins. I'll double check that.
https://github.com/llvm/llvm-project/pull/116858
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@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/s-perron edited
https://github.com/llvm/llvm-project/pull/116858
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@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -17,12 +17,10 @@ double test_int_builtin(double p0) {
double2 test_int_builtin_2(double2 p0) {
return __builtin_hlsl_elementwise_firstbithigh(p0);
- // expected-error@-1 {{1st argument must be a vector of integers
- // (was 'double2' (aka 'vector'))}}
+ // expected-err
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
@llvm/pr-subscribers-clang-codegen
Author: Ashley Coleman (V-FEXrt)
Changes
Closes https://github.com/llvm/llvm-project/issues/99116
- [x] Implement firstbitlow clang builtin,
- [x] Link firstbitlow clang builtin with hlsl_intrinsics.h
https://github.com/V-FEXrt created
https://github.com/llvm/llvm-project/pull/116858
Closes https://github.com/llvm/llvm-project/issues/99116
- [x] Implement firstbitlow clang builtin,
- [x] Link firstbitlow clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for firstbitlow to CheckHL
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Ashley Coleman (V-FEXrt)
Changes
Closes https://github.com/llvm/llvm-project/issues/99116
- [x] Implement firstbitlow clang builtin,
- [x] Link firstbitlow clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for firstbitlow to Ch
llvmbot wrote:
@llvm/pr-subscribers-hlsl
Author: Ashley Coleman (V-FEXrt)
Changes
Closes https://github.com/llvm/llvm-project/issues/99116
- [x] Implement firstbitlow clang builtin,
- [x] Link firstbitlow clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for firstbitlow to Che
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