================
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling with a larger vec requires
+ // creating a param reg and return reg with an invalid vec size. If that is
+ // resolved then this function is valid for vectors of any component size.
unsigned ComponentCount = GR.getScalarOrVectorComponentCount(ResType);
- SPIRVType *BaseType = GR.retrieveScalarOrVectorIntType(ResType);
- bool ZeroAsNull = STI.isOpenCLEnv();
- Register ConstIntZero =
- GR.getOrCreateConstInt(0, I, BaseType, TII, ZeroAsNull);
- unsigned LeftComponentCount = ComponentCount / 2;
- unsigned RightComponentCount = ComponentCount - LeftComponentCount;
- bool LeftIsVector = LeftComponentCount > 1;
+ assert(ComponentCount < 5 && "Vec 5+ will generate invalid SPIR-V ops");
- // Split the SrcReg in half into 2 smaller vec registers
- // (ie i64x4 -> i64x2, i64x2)
+ bool ZeroAsNull = STI.isOpenCLEnv();
MachineIRBuilder MIRBuilder(I);
- SPIRVType *OpType = GR.getOrCreateSPIRVIntegerType(64, MIRBuilder);
- SPIRVType *LeftVecOpType;
- SPIRVType *LeftVecResType;
- if (LeftIsVector) {
- LeftVecOpType =
- GR.getOrCreateSPIRVVectorType(OpType, LeftComponentCount, MIRBuilder);
- LeftVecResType =
- GR.getOrCreateSPIRVVectorType(BaseType, LeftComponentCount,
MIRBuilder);
- } else {
- LeftVecOpType = OpType;
- LeftVecResType = BaseType;
- }
-
- SPIRVType *RightVecOpType =
- GR.getOrCreateSPIRVVectorType(OpType, RightComponentCount, MIRBuilder);
- SPIRVType *RightVecResType =
- GR.getOrCreateSPIRVVectorType(BaseType, RightComponentCount, MIRBuilder);
+ SPIRVType *BaseType = GR.retrieveScalarOrVectorIntType(ResType);
+ SPIRVType *I64Type = GR.getOrCreateSPIRVIntegerType(64, MIRBuilder);
+ SPIRVType *I64x2Type = GR.getOrCreateSPIRVVectorType(I64Type, 2, MIRBuilder);
+ SPIRVType *Vec2ResType =
+ GR.getOrCreateSPIRVVectorType(BaseType, 2, MIRBuilder);
- Register LeftSideIn =
- MRI->createVirtualRegister(GR.getRegClass(LeftVecOpType));
- Register RightSideIn =
- MRI->createVirtualRegister(GR.getRegClass(RightVecOpType));
+ std::vector<Register> PartialRegs;
- bool Result;
+ // Loops 0, 2, 4, ... but stops one loop early when ComponentCount is odd
+ unsigned CurrentComponent = 0;
+ for (; CurrentComponent + 1 < ComponentCount; CurrentComponent += 2) {
----------------
spall wrote:
I wonder if you can easily optimize this case.
https://github.com/llvm/llvm-project/pull/116858
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