[clang] [clang-format] Indent Verilog case statements with comments (PR #71353)

https://github.com/sstwcw closed https://github.com/llvm/llvm-project/pull/71353 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-format] Indent Verilog case statements with comments (PR #71353)

https://github.com/HazardyKnusperkeks approved this pull request. https://github.com/llvm/llvm-project/pull/71353 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-format] Indent Verilog case statements with comments (PR #71353)

llvmbot wrote: @llvm/pr-subscribers-clang-format Author: None (sstwcw) Changes If a line contains a comment outside of (fake) parentheses, the part following it is indented according to `CurrentState.Indent`. A Verilog case label and the statement that follows are broken with mustBreakB

[clang] [clang-format] Indent Verilog case statements with comments (PR #71353)

https://github.com/sstwcw created https://github.com/llvm/llvm-project/pull/71353 If a line contains a comment outside of (fake) parentheses, the part following it is indented according to `CurrentState.Indent`. A Verilog case label and the statement that follows are broken with mustBreakBefo